TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS Check for Samples: TPS650250-Q1 FEATURES 1 • • • • • Qualified for Automotive Applications 1.6A, 97% Efficient Step-Down Converter for System Voltage (VDCDC1) – 3.3V or 2.8V or Adjustable 0.8A, up to 95% Efficient Step-Down Converter for Memory Voltage (VDCDC2) – 1.8V or 2.5V or Adjustable 0.8A, 90% Efficient Step-Down Converter for Processor Core (VDCDC3) Adjustable Output Voltage on VDCDC3 • • • • • • • • 30mA LDO for Vdd_alive 2 × 200mA General Purpose LDOs (LDO1 and LDO2) Dynamic Voltage Management for Processor Core LDO1 and LDO2 Voltage Externally Adjustable Separate Enable Pins for Inductive Converters 2.25MHz Switching Frequency 85mA Quiescent Current Thermal Shutdown Protection DESCRIPTION The TPS650250 is an integrated Power Management IC for applications powered by one Li-Ion or Li-Polymer cell, which require multiple power rails. The TPS650250 provides three highly efficient, step-down converters targeted at providing the core voltage, peripheral, I/O and memory rails in a processor based system. All three step-down converters enter a low power mode at light load for maximum efficiency across the widest possible range of load currents. The converters can be forced into fixed frequency PWM mode by pulling the MODE pin high. The TPS650250 also integrates two general purpose 200mA LDO voltage regulators, which are enabled with an external input pin. Each LDO operates with an input voltage range between 1.5V and 6.5V allowing them to be supplied from one of the step-down converters or directly from the battery. The output voltage of the LDOs can be set with an external resistor divider for maximum flexibility. Additionally there is a 30mA LDO typically used to provide power in a processor based system to a voltage rail that is always on. TPS650250 comes in a small 5mm x 5mm 32-pin QFN package (RHB). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Functional Block Diagram TPS650250 1R VCC Vbat 1 mF VINDCDC1 Vbat DCDC1 (I/O) 10 mF STEP-DOWN CONVERTER 1600 mA EN_DCDC1 ENABLE VINDCDC2 Vbat DCDC2 (memory) 10 mF STEP-DOWN CONVERTER 800 mA EN_DCDC2 ENABLE VINDCDC3 Vbat 3.3 V / 2.8 V or adjustable L1 10 mF DCDC3 (core) ENABLE STEP-DOWN CONVERTER 800 mA EN_DCDC3 2.2 mH VDCDC1 R1 22 mF DEFDCDC1 PGND1 R2 2.5 V / 1.8 V or adjustable L2 2.2 mH VDCDC2 R3 22 mF DEFDCDC2 PGND2 R4 L3 2.2 mH VDCDC3 R5 22 mF DEFDCDC3 PGND3 R6 MODE PWM/ PFM VIN_LDO VIN VLDO1 VLDO1 200 mA LDO EN_LDO ENABLE FB_LDO1 R7 2.2 mF R8 VLDO2 200 mA LDO VLDO2 FB_LDO2 R9 R10 EN_Vdd_alive ENABLE VCC Vbat 2.2 mF VLDO3 30 mA LDO Vdd_alive 1V 2.2 mF R11 I/O voltage PWRFAIL_SNS R12 - PWRFAIL R19 + Vref = 1 V AGND1 AGND2 ORDERING INFORMATION (1) (1) (2) 2 TJ VOLTAGE AT DCDC3 OUTPUT CURRENT ON DCDC1 / DCDC2 / DCDC3 VOLTAGE AT VDD_ALIVE PACKAGE ORDERABLE PART NUMBER (2) TOP-SIDE MARKING –40°C to 125°C Adjustable 1.6A / 0.8A / 0.8A 1V 32-Pin QFN (RHB) TPS650250QRHBRQ1 TPS650250Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Input voltage range on all pins except A/PGND pins with respect to AGND Voltage range on pins VLDO1, VLDO2, FB_LDO1, FB_LDO2 Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 Peak current at all other pins Continuous total power dissipation VALUE UNIT –0.3 to 7 V –0.3 to 3.6 V 2000 mA 500 mA See Dissipation Ratings TJ Operating junction temperature –40 to 125 °C Tst Storage temperature –65 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS (1) PACKAGE (1) RqJA TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C RHB 35°C/W 2.85W 28mW/°C TA = 70°C TA = 85°C TA = 105°C POWER RATING POWER RATING POWER RATING 1.57W 1.14W 0.61W The thermal resistance junction to ambient of the RHB package is measured on a high K board. The thermal resistance junction to power pad is 1.5°C/W. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 3 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN VCC Input voltage range step-down converters, VINDCDC1, VINDCDC2, VINDCDC3 Output voltage range for step-down converter, VDCDC1 VO (1) Output voltage range for mem step-down converter, VDCDC2 (1) NOM MAX UNIT 2.5 6.0 V 0.6 VINDCDC1 V 0.6 VINDCDC2 V Output voltage range for core step-down converter, VDCDC3 0.6 VINDCDC3 V VI Input voltage range for LDOs, VINLDO1, VINLDO2 1.5 6.5 V VO Output voltage range for LDOs IO Output current at L, V1DCDC1 L1 Inductor at L1 (2) 1 1.5 CI Input capacitor at VINDCDC1 (2) 10 CO Output capacitor at VDCDC1 (2) 10 IO Output current at L2, VDCDC2 L2 Inductor at L2 (2) 1.5 CI Input capacitor at VINDCDC2 CO Output capacitor at VDCDC2 (2) IO Output current at L3, VDCDC3 L3 Inductor at L3 (2) 1.5 CI Input capacitor at VINDCDC3 (2) 10 CO Output capacitor at VDCDC3 (2) 10 Input capacitor at VCC Input capacitor at VINLDO (2) CO Output capacitor at VLDO1, VLDO2 (2) IO Output current at VLDO1, VLDO2 CO Output capacitor at Vdd_alive (2) IO Output current at Vdd_alive TJ Operating junction temperature RCC (1) (2) (3) 4 10 10 mF 22 mF 2.2 mF 22 mF 2.2 mA mH mF 22 mF 1 mF 1 mF mF 200 mA 30 mA 125 °C 10 Ω 2.2 mF –40 Resistor from VINDCDC3,VINDCDC2, VINDCDC1 to VCC used for filtering mA mH 2.2 (3) V mA mH 800 (2) CI 2.2 800 (2) CI 3.3 1600 1 When using an external resistor divider at DEFDCDC2, DEFDCDC1. See applications section for more information, for VO > 2.85V choose 3.3mH inductor. Up to 2.5mA can flow into VCC when all 3 converters are running in PWM, this resistor will cause the UVLO threshold to be shifted accordingly. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) CONTROL SIGNALS: EN_DCDC1, EN_DCDC2, EN_DCDC3, EN_LDO, MODE, EN_VDD_ALIVE PARAMETER VIH High level input voltage VIL Low level input voltage IH Input bias current TEST CONDITIONS MIN TYP MAX UNIT 1.45 VCC V 0 0.4 V 0.01 0.1 mA 135 170 75 100 SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3 PFM All 3 DCDC converters enabled, zero load and no switching, LDOs enabled I(qPFM) Operating quiescent current PFM All 3 DCDC converters enabled, zero load and no switching, LDO1, LDO2 = OFF, Vdd_alive = ON PFM DCDC1 and DCDC2 converters enabled, zero load and no switching, LDO1, LDO2 = OFF, Vdd_alive = ON VCC = 3.6V PFM DCDC1 converter enabled, zero load and no switching, LDO1, LDO2 = OFF, Vdd_alive = ON All 3 DCDC converters enabled & running in PWM, LDOs off IVCC(PWM) Current into VCC; PWM PWM DCDC1 converter enabled and running in PWM, LDOs off Iq Quiescent current All converters disabled, LDO1, LDO2 = OFF, Vdd_alive = ON 55 80 40 60 2 PWM DCDC1 and DCDC2 converters enabled and VCC = 3.6V running in PWM, LDOs off All converters disabled, LDO1, LDO2 = OFF, Vdd_alive = OFF mA 1.5 2.5 0.85 2 16 VCC = 3.6V 26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 mA mA 5 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC1 STEP-DOWN CONVERTER VI Input voltage range,VINDCDC1 IO Maximum output current VO = 3.3V ISD Shutdown supply current in VINDCDC1 EN_DCDC1 = GND 0.1 1 mA RDS(on) P-channel MOSFET on-resistance VINDCDC1 = VGS = 3.6V 125 261 mΩ ILP P-channel leakage current VINDCDC1 = 6V RDS(on) N-channel MOSFET on-resistance VINDCDC1 = VGS = 3.6V ILN N-channel leakage current VDS = 6V ILIMF Forward current limit (P- and N-channel) 2.5V < VINMAIN < 6V fS Oscillator frequency VDCDC1 Fixed output voltage MODE=0 (PWM/PFM) 2.8V Fixed output voltage MODE=1 (PWM) 2.8V 2.5 3.3V 3.3V 6 1600 130 2 mA 260 mΩ mA 7 10 1.7 1.97 2.22 A 1.95 2.25 2.55 MHz VINDCDC1 = 3.3V to 6V; 0 mA ≤ IO ≤ 1.0A –2% 2% –2% 2% VINDCDC1 = 3.7V to 6V; 0 mA ≤ IO ≤ 1.0A –1% 1% –1% 1% Adjustable output voltage with resistor divider at DEFDCDC1 MODE = 0 (PWM/PFM) VINDCDC1 = VDCDC1 +0.4V (min 2.5V) to 6V; 0mA ≤ IO ≤ 1.6A –2% 2% Adjustable output voltage with resistor divider at DEFDCDC1; MODE = 1 (PWM) VINDCDC1 = VDCDC1 +0.4V (min 2.5V) to 6V; 0mA ≤ IO ≤ 1.6A –1% 1% Line regulation VINDCDC1 = VDCDC1 + 0.3V (min. 2.5 V) to 6V; IO = 10mA Load regulation tSS Soft start ramp time R(L1) Internal resistance from L1 to GND 6 V mA 0 %/V IO = 10mA to 1.6A 0.25 %/A VDCDC1 ramping from 5% to 95% of target value 750 ms 1 MΩ Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC2 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC2 IO Maximum output current VO = 2.5V 2.5 6 ISD Shutdown supply current in VINDCDC2 EN_DCDC2 = GND 0.1 1 mA RDS(on) P-channel MOSFET on-resistance VINDCDC2 = VGS = 3.6V 140 300 mΩ ILP P-channel leakage current VINDCDC2 = 6.0V RDS(on) N-channel MOSFET on-resistance VINDCDC2 = VGS = 3.6V ILN N-channel leakage current VDS = 6V ILIMF Forward current limit (P- and N-channel) 2.5V < VINDCDC2 < 6V fS Oscillator frequency 800 150 2 mA 297 mΩ mA 7 10 1 1.16 1.29 A 1.95 2.25 2.55 MHz Fixed output voltage MODE = 0 (PWM/PFM) 1.8V VINDCDC2 = 2.5V to 6V; 0 mA ≤ IO ≤ 1.6A –2% 2% 2.5V VINDCDC2 = 3V to 6V; 0 mA ≤ IO ≤ 1.6A –2% 2% Fixed output voltage MODE = 1 (PWM) 1.8V VINDCDC2 = 2.5V to 6V; 0 mA ≤ IO ≤ 1.6A –2% 2% 2.5V VINDCDC2 = 3V to 6V; 0 mA ≤ IO ≤ 1.6A –1% 1% Adjustable output voltage with resistor divider at DEFDCDC2 MODE = 0 (PWM) VINDCDC2 = VDCDC2 + 0.5V (min 2.5V) to 6V; 0mA ≤ IO ≤ 1.6A –2% 2% Adjustable output voltage with resistor divider at DEFDCDC2; MODE = 1 (PWM) VINDCDC2 = VDCDC2 + 0.5V (min 2.5V) to 6V; 0mA ≤ IO ≤ 1.6A –1% 1% Line regulation VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V) to 6V; IO = 10mA Load regulation tSS Soft start ramp time R(L2) Internal resistance from L2 to GND VDCDC2 V mA 0.0 %/V IO = 10mA to 1.6A 0.25 %/A VDCDC2 ramping from 5% to 95% of target value 750 ms 1 MΩ Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 7 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC3 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC3 IO Maximum output current VO = 1.6V 2.5 6.0 ISD Shutdown supply current in VINDCDC3 EN_DCDC3 = GND 0.1 1 mA RDS(on) P-channel MOSFET on-resistance VINDCDC3 = VGS = 3.6V 310 698 mΩ ILP P-channel leakage current VINDCDC3 = 6V 0.1 2 mA RDS(on) N-channel MOSFET on-resistance VINDCDC3 = VGS = 3.6V 220 503 mΩ ILN N-channel leakage current VDS = 6.0V 7 10 mA ILIMF Forward current limit (P- and N-channel) 2.5V < VINDCDC3 < 6V 1.00 1.20 1.40 A fS Oscillator frequency 1.95 2.25 2.55 MHz 800 Adjustable output voltage with resistor divider at DEFDCDC2 MODE = 0 (PWM) VINDCDC3 = VDCDC3 + 0.5V (min 2.5V) to 6V; 0mA ≤ IO ≤ 0.8A –2% 2% Adjustable output voltage with resistor divider at DEFDCDC2; MODE = 1 (PWM) VINDCDC3 = VDCDC3 + 0.5V (min 2.5V) to 6V; 0mA ≤ IO ≤ 0.8A –1% 1% Line regulation VINDCDC3 = VDCDC3 + 0.3V (min. 2.5 V) to 6V; IO = 10mA Load regulation tSS Soft start ramp time R(L3) Internal resistance from L3 to GND VDCDC3 8 V mA 0.0 %/V IO = 10mA to 600mA 0.25 %/A VDCDC3 ramping from 5% to 95% of target value 750 ms 1 MΩ Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VLDO1 and VLDO2 Low Dropout Regulators I(q) Operating quiescent current Current per LDO into VINLDO 16 33 mA I(SD) Shutdown current Total current into VINLDO, VLDO = 0V 0.6 2 mA VI Input voltage range for LDO1, LDO2 1.5 6.5 V VO LDO1 output voltage range 1 3.3 V LDO2 output voltage range 1 3.3 V (1) VFB LDO1 and LDO2 feedback voltage See 1.0 IO Maximum output current for LDO1, LDO2 VI = 1.8V, VO = 1.3V V IO Maximum output current for LDO1, LDO2 VI = 1.5V; VO = 1.3V ISC LDO1 and LDO2 short circuit current limit VLDO1 = GND, VLDO2 = GND 400 mA Minimum voltage drop at LDO1, LDO2 IO = 50mA, VINLDO = 1.8V 120 mV Minimum voltage drop at LDO1, LDO2 IO = 50mA, VINLDO = 1.5V 150 mV Minimum voltage drop at LDO1, LDO2 IO = 200mA, VINLDO = 1.8V 300 mV Output voltage accuracy for LDO1, LDO2 IO = 10mA –2% 1% Line regulation for LDO1, LDO2 VINLDO1,2 = VLDO1,2 + 0.5V (min. 2.5V) to 6.5V, IO = 10mA –1% 1% Load regulation for LDO1, LDO2 IO = 0mA to 200mA –1% Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 ms IO = 0mA 1.0 V 200 mA 120 65 mA 1% Vdd_alive Low Dropout Regulator Vdd_alive Vdd_alive LDO output voltage, TPS6502500 to TPS6502504 IO Output current for Vdd_alive I(SC) Vdd_alive short circuit current limit Vdd_alive = GND Output voltage accuracy for Vdd_alive IO = 0mA –1% Line regulation for Vdd_alive VCC = Vdd_alive + 0.5 V to 6.5 V, IO = 0mA –1% Regulation time for Vdd_alive Load change from 10% to 90% 30 mA 100 mA 1% 1% 10 ms AnaLogic Signals DEFDCDC1, DEFDCDC2, DEFDCDC3 VIH High level input voltage 1.3 VCC VIL Low level input voltage 0 0.1 V IH Input bias current 0.05 mA 0.001 V THERMAL SHUTDOWN TSD Thermal shutdown Increasing junction temperature 160 °C Thermal shudown hysteresis Decreasing junction temperature 20 °C INTERNAL UNDER VOLTAGE LOCK OUT UVLO Internal UVLO VUVLO_HYST internal UVLO comparator hysteresis VCC falling –3% 2.35 3% 120 V mV VOLTAGE DETECTOR COMPARATOR PWRFAIL_SNS Comparator threshold Falling threshold Hysteresis VOL (1) –2% 1.0 2% V 40 50 60 mV Propagation delay 25mV overdrive 10 ms Power fail output low voltage IOL = 5 mA 0.3 V If the feedback voltage is forced higher than above 1.2V, a leakage current into the feedback pin may occur. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 9 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com DEVICE INFORMATION DEFDCDC3 AGND1 PWRFAIL_SNS Vcc VINDCDC2 L2 PGND2 VDCDC2 PIN ASSIGNMENTS 32 31 30 29 28 27 26 25 VDCDC3 PGND3 L3 VINDCDC3 VINDCDC1 L1 PGND1 VDCDC1 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 TPS650250 EN_Vdd_alive MODE DEFDCDC2 PWRFAIL EN_DCDC1 EN_DCDC2 EN_DCDC3 EN_LDO DEFDCDC1 FB_LDO2 FB_LDO1 Vdd_alive AGND2 VLDO2 VINLDO VLDO1 9 10 11 12 13 14 15 16 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION SWITCHING REGULATOR SECTION AGND1 31 Analog ground connection. All analog ground pins are connected internally on the chip. AGND2 13 Analog ground connection. All analog ground pins are connected internally on the chip. PowerPad – VINDCDC1 5 L1 6 VDCDC1 8 PGND1 7 VINDCDC2 28 L2 27 VDCDC2 25 PGND2 26 Connect the power pad to analog ground. I Input voltage for VDCDC1 step-down converter. This must be connected to the same voltage supply as VINDCDC2, VINDCDC3 and VCC. Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here. I VDCDC1 feedback voltage sense input, connect directly to VDCDC1 Power ground for VDCDC1 converter I Input voltage for VDCDC2 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC3 and VCC. Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here. I VDCDC2 feedback voltage sense input, connect directly to VDCDC2 Power ground for VDCDC2 converter I VINDCDC3 4 L3 3 VDCDC3 1 PGND3 2 Vcc 29 I DEFDCDC1 9 I DEFDCDC2 22 I Input voltage for VDCDC3 step-down converter. This must be connected to the same voltage supply as VINDCDC1, VINDCDC2 and VCC. Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here. I VDCDC3 feedback voltage sense input, connect directly to VDCDC3 Power ground for VDCDC3 converter Power supply for digital and analog circuitry of DCDC1, DCDC2 and DCDC3 DC-DC converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1 and VINDCDC2. Input signal indicating default VDCDC1 voltage, 0 = 2.8V, 1 = 3.3V This pin can also be connected to a resistor divider between VDCDC1 and GND. In this case the output voltage of the DCDC1 converter can be set in a range from 0.6V to VINDCDC1 Input signal indicating default VDCDC2 voltage, 0 = 1.8V, 1 = 2.5V 10 This pin can also be connected to a resistor divider between VDCDC2 and GND. In this case the output voltage of the DCDC2 converter can be set in a range from 0.6V to VINDCDC2. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION I This pin must be connected to a resistor divider between VDCDC3 and GND. The output voltage of the DCDC3 converter can be set in a range from 0.6V to VINDCDC3. 20 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator. 19 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator. 18 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator. DEFDCDC3 32 EN_DCDC1 EN_DCDC2 EN_DCDC3 LDO REGULATOR SECTION VINLDO 15 I Input voltage for LDO1 and LDO2 VLDO1 16 O Output voltage of LDO1 VLDO2 14 O Output voltage of LDO2 EN_LDO 17 I Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs EN_Vdd_alive 24 I Enable input for Vdd_alive LDO. Logic high enables the LDO, logic low disables the LDO Vdd_alive 12 O Output voltage for Vdd_alive FB_LDO1 11 I Feedback pin for LDO1 FB_LDO2 10 I Feedback pin for LDO2 CONTROL AND I2C SECTION MODE 23 I Select between Power Safe Mode and forced PWM Mode for DCDC1, DCDC2 and DCDC3. In Power Safe Mode PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level, then Device operates in Power Safe Mode. PWRFAIL 21 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition. PWRFAIL_SNS 30 I Input for the comparator driving the /PWRFAIL output Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 11 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM TPS650250 1R VCC Vbat 1 mF VINDCDC1 Vbat DCDC1 (I/O) 10 mF STEP-DOWN CONVERTER 1600 mA EN_DCDC1 ENABLE VINDCDC2 Vbat DCDC2 (memory) 10 mF STEP-DOWN CONVERTER 800 mA EN_DCDC2 ENABLE VINDCDC3 Vbat 3.3 V / 2.8 V or adjustable L1 2.2 mH VDCDC1 R1 22 mF DEFDCDC1 PGND1 R2 2.5 V / 1.8 V or adjustable L2 2.2 mH VDCDC2 R3 22 mF DEFDCDC2 PGND2 R4 L3 10 mF DCDC3 (core) 2.2 mH VDCDC3 DEFDCDC3 ENABLE STEP-DOWN CONVERTER 800 mA EN_DCDC3 PGND3 R5 22 mF R6 MODE PWM/ PFM VIN_LDO VIN VLDO1 200 mA LDO EN_LDO ENABLE VLDO1 FB_LDO1 R7 2.2 mF R8 VLDO2 200 mA LDO VLDO2 FB_LDO2 R9 R10 EN_Vdd_alive ENABLE VCC Vbat 2.2 mF VLDO3 30 mA LDO Vdd_alive 1V 2.2 mF R11 I/O voltage PWRFAIL_SNS R12 - PWRFAIL R19 + Vref = 1 V AGND1 12 AGND2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 TYPICAL CHARACTERISTICS Parameter Measurement Information Graphs were taken using the EVM with the following inductor/output capacitor combinations: CONVERTER INDUCTOR OUTPUT CAPACITOR OUTPUT CAPACITOR VALUE DCDC1 VLCF4020-3R3 C2012X5R0J226M 22mF DCDC2 VLCF4020-2R2 C2012X5R0J226M 22mF DCDC3 LPS3010-222 C2012X5R0J226M 22mF Table of Graphs FIGURE h Efficiency VDCDC1 vs Load current PWM/PFM; VO = 3.3V Figure 1 h Efficiency VDCDC1 vs Load current PWM; VO = 3.3V Figure 2 h Efficiency VDCDC2 vs Load current PWM/PFM; VO = 1.8V Figure 3 h Efficiency VDCDC2 vs Load current PWM; VO = 1.8V Figure 4 h Efficiency VDCDC3 vs Load current PWM/PFM; VO = 1.3V Figure 5 h Efficiency VDCDC3 vs Load current PWM; VO = 1.3V Figure 6 Line transient response VDCDC1 Figure 7 Line transient response VDCDC2 Figure 8 Line transient response VDCDC3 Figure 9 Load transient response VDCDC1 Figure 10 Load transient response VDCDC2 Figure 11 Load transient response VDCDC3 Figure 12 Output voltage ripple DCDC2; PFM mode Figure 13 Output voltage ripple DCDC2; PWM mode Figure 14 Load regulation for Vdd_alive Figure 15 Start-up VDCDC1 to VDCDC3 Figure 16 Start-up LDO1 and LDO2 Figure 17 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 13 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com DCDC1: EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 VI = 3.8 V 80 VI = 4.2 V 70 VI = 5 V 60 50 40 60 VI = 3.8 V 50 VI = 4.2 V 40 30 30 VI = 5 V TA = 25°C, VO = 3.3 V, PFM/PWM Mode 20 10 0 0.1 TA = 25°C, VO = 3.3 V, PWM Mode 80 Efficiency - % 70 Efficiency - % DCDC1: EFFICIENCY vs OUTPUT CURRENT 1 10 100 1k IO - Output Current - mA 20 10 0 0.1 10k 1 10 100 1k IO - Output Current - mA Figure 1. Figure 2. DCDC2: EFFICIENCY vs OUTPUT CURRENT DCDC2: EFFICIENCY vs OUTPUT CURRENT 10k VI = 2.5 V VI = 3.8 V Efficiency - % Efficiency - % VI = 3.8 V VI = 4.2 V VI = 4.2 V VI = 2.5 V VI = 5 V VI = 5 V TA = 25oC VO = 1.8 V PWM Mode o TA = 25 C VO = 1.8 V PWM / PFM Mode 0.01 0.1 1 10 100 1k 10 k 0.01 IO - Output Current - mA Figure 3. 14 0.1 1 10 100 1k 10 k IO - Output Current - mA Figure 4. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 DCDC3: EFFICIENCY vs OUTPUT CURRENT DCDC3: EFFICIENCY vs OUTPUT CURRENT 100 100 TA = 25°C, 90 VO = 1.5 V, PWM/PFM Mode 80 80 60 VI = 3 V 50 VI = 3.8 V 30 0 0.01 VI = 3 V VI = 3.8 V 60 50 VI = 4.2 V 40 VI = 5 V 30 VI = 4.2 V 20 20 10 VI = 2.5 V 70 VI = 2.5 V Efficiency - % Efficiency - % 70 40 TA = 25°C, VO = 1.5 V, PWM Mode 90 VI = 5 V 0.1 10 1 10 100 IO - Output Current - mA 1k 0 0.01 0.1 1 10 100 IO - Output Current - mA Figure 5. Figure 6. VDCDC1 LINE TRANSIENT RESPONSE VDCDC2 LINE TRANSIENT RESPONSE Ch1 = VI 1k Ch1 = VI Ch2 = VO Ch2 = VO IO = 100 mA VI = 3.8 V to 4.5 V VO = 3.3 V IO = 100 mA VI = 3 V to 4 V VO = 1.8 V PWM Mode Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 15 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com VDCDC3 LINE TRANSIENT RESPONSE VDCDC1 LOAD TRANSIENT RESPONSE Ch1 = VI Ch1 = VI Ch2 = VO Ch2 = VO IO = 160 mA to 14000 mA VI = 3.3 V VO = 4.2 V IO = 100 mA VI = 3 V to 4 V VO = 1.375 V Figure 9. Figure 10. VDCDC2 LOAD TRANSIENT RESPONSE VDCDC3 LOAD TRANSIENT RESPONSE Ch4 = IO Ch4 = IO Ch2 = VO Ch2 = VO IO = 100 mA to 900 mA VO = 1.8 V IO = 80 mA to 720 mA VO = 1.375 V Figure 11. 16 Figure 12. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 VDCDC2 OUTPUT VOLTAGE RIPPLE VI = 3.8 V VO = 1.8 V VDCDC2 OUTPUT VOLTAGE RIPPLE IO = 1 mA o TA = 25 C PFM Mode VI = 3.8 V VO = 1.8 V IO = 1 mA TA = 25oC PWM Mode Figure 13. Figure 14. VDD_ALIVE OUTPUT VOLTAGE vs OUTPUT CURRENT STARTUP VDCDC1, VDCDC2, VDCDC3 1.010 VCC = 3.6 V ENABLE VO - Output Voltage - V 1.000 0.990 VDCDC1 0.980 VDCDC2 0.970 0.960 VDCDC3 0.950 0.940 0 5 10 15 20 25 30 IO - Output Current - mA 35 40 Figure 15. Figure 16. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 17 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com STARTUP LDO1 AND LDO2 ENABLE LDO1 LDO2 Figure 17. 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 DETAILED DESCRIPTION STEP-DOWN CONVERTERS, VDCDC1, VDCDC2 AND VDCDC3 The TPS650250 incorporates three synchronous step-down converters operating typically at 2.25MHz fixed frequency PWM (Pulse Width Modulation) at moderate to heavy load currents. At light load currents the converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation). VDCDC1 delivers up to 1.6A, VDCDC2 and VDCDC3 are capable of delivering up to 0.8A of output current. The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The pins can either be connected to GND, VCC or to a resistor divider between the output voltage and GND. The VDCDC1 converter defaults to 2.8V or 3.3V depending on the DEFDCDC1 configuration pin, if DEFDCDC1 is tied to ground the default is 2.80V, if it is tied to VCC the default is 3.3V. When the DEFDCDC1 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6V to VINDCDC1 V. Reference the section on Output Voltage Selection for details on setting the output voltage range. The VDCDC2 converter defaults to 1.8V or 2.5V depending on the DEFDCDC2 configuration pin, if DEFDCDC2 is tied to ground the default is 1.8V, if it is tied to VCC the default is 2.5V. When the DEFDCDC2 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6V to VINDCDC2 V. On the DEFDCDC3 pin for the VDCDC3 converter, a resistor divider must be connected to set the output voltage. This pin does not accept a logic signal like DEFDCDC1 or DEFDCDC2. The value for the resistor divider can be changed during operation, so voltage scaling can be implemented by changing the resistor value. During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. After the adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the N-channel rectifier and turning on the P-channel switch. The three DC/DC converters operate synchronized to each other, with the VDCDC1 converter as the master. A 180° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3 switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7V to 3.3V, the VDCDC2 converter from 3.7V to 2.5V and the VDCDC3 converter from 3.7V to 1.5V. POWER SAVE MODE OPERATION As the load current decreases, the converters enter Power Save Mode operation. During Power Save Mode the converters operate in a burst mode (PFM mode) with a frequency between 1.125MHz and 2.25MHz for one burst cycle. However, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency, with a minimum quiescent current to maintain high efficiency. In order to optimize the converter efficiency at light load the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then Power Save Mode is entered. The typical threshold to enter Power Save Mode can be calculated as follows: I PFMDCDC1enter + VINDCDC 1 24 W I PFMDCDC2enter + VINDCDC 2 26 W I PFMDCDC3leave + VINDCDC 3 39 W (1) During Power Save Mode the output voltage is monitored with a comparator and by maximum skip burst width. As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter effectively delivers a constant current as defined below. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 19 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com I PFMDCDC1leave + VINDCDC 1 18 W I PFMDCDC2leave + VINDCDC 2 20 W I PFMDCDC3enter + VINDCDC 3 29 W (2) If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode if either of the following conditions are met: 1. The output voltage drops 2% below the nominal VO due to increased load current 2. The PFM burst time exceeds 16 × 1/fs (7.1ms typical) These control methods reduce the quiescent current to typically 14mA per converter and the switching activity to a minimum thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light load current results in a very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor values makes the output ripple tend to zero. Power Save Mode can be disabled by pulling the MODE pin high. This forces all DC/DC converters into fixed frequency PWM mode. SOFT START Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft start is realized by using a very low current to initially charge the internal compensation capacitor. The soft start time is typically 750ms if the output voltage ramps from 5% to 95% of the final target value. If the output is already pre-charged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a short delay of typically 170ms between the converter being enabled and switching activity actually starting. This is to allow the converter to bias itself properly, to recognize if the output is pre-charged, and if so, to prevent discharging of the output while the internal soft start ramp catches up with the output voltage. 100% DUTY CYCLE LOW DROPOUT OPERATION The TPS650250x converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage required to maintain DC regulation depends on the load current and output voltage and can be calculated as: Vin min + Vout min ) Iout max ǒRDSonmax ) R LǓ (3) With: Ioutmax = Maximum load current (note: ripple current in the inductor is zero under these conditions) RDSonmax = Maximum P-channel switch RDSon RL = DC resistance of the inductor Voutmin = Nominal output voltage minus 2% tolerance limit LOW DROPOUT VOLTAGE REGULATORS The low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors. They operate with input voltages down to 1.5V. The LDOs offer a maximum dropout voltage of 300mV at the rated output current. Each LDO sports a current limit feature. Both LDOs are enabled by the EN_LDO pin. The LDOs also have reverse conduction prevention. This allows the possibility to connect external regulators in parallel in systems with a backup battery. The TPS650250 step-down and LDO voltage regulators automatically power down when the Vcc voltage drops below the UVLO threshold or when the junction temperature rises above 160°C. 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 UNDERVOLTAGE LOCKOUT The undervoltage lockout circuit for the five regulators on the TPS650250x prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The UVLO circuit monitors the Vcc pin; the threshold is set internally to 2.35V with 5% (120mV) hysteresis. Note that when any of the DC/DC converters are running there is an input current at the Vcc pin, which can be up to 3mA when all three converters are running in PWM mode. This current needs to be taken into consideration if an external RC filter is used at the Vcc pin to remove switching noise from the TPS650250x internal analog circuitry supply. See the Vcc-Filter section for details on the external RC filter. POWER-UP SEQUENCING The TPS650250x power-up sequencing is designed to be entirely flexible and customer driven; this is achieved simply by providing separate enable pins for each switch-mode converter and a common enable signal for LDO1 and LDO2. The relevant control pins are described in Table 1. Table 1. Control Pins for DCDC Converters PIN NAME INPUT/ OUTPUT DEFDCDC3 I Defines the default voltage of the VDCDC3 switching converter set with an eternal resistor divider. DEFDCDC2 I Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to 1.8V, DEFDCDC2 = VCC defaults VDCDC2 to 2.5V. DEFDCDC1 I Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 2.80V, DEFDCDC1 = VCC defaults VDCDC1 to 3.3V. EN_DCDC3 I Set EN_DCDC3 = 0 to disable or EN_DCDC3 = 1 to enable the VDCDC3 converter EN_DCDC2 I Set EN_DCDC2 = 0 to disable or EN_DCDC2 = 1 to enable the VDCDC2 converter EN_DCDC1 I Set EN_DCDC1 = 0 to disable or EN_DCDC1 = 1 to enable the VDCDC1 converter FUNCTION PWRFAIL The PWRFAIL signal is generated by a voltage detector at the PWRFAIL_SNS input. The input signal is compared to a 1V threshold (falling edge) with 5% (50mV) hysteresis. PWRFAIL is an open drain output which is actively low when the input voltage at PWRFAIL_SNS is below the threshold. DESIGN PROCEDURE Inductor Selection for the dcdc Converters The three converters operate with 2.2uH output inductors. Larger or smaller inductor values can be used to optimize performance of the device for specific conditions. The selected inductor has to be rated for its dc resistance and saturation current. The dc resistance of the inductor influences directly the efficiency of the converter. Therefore, an inductor with the lowest dc resistance should be selected for the highest efficiency. For a fast transient response, a 2.2mH inductor in combination with a 22mF output capacitor is recommended. For an output voltage above 2.8V, an inductor value of 3.3mH minimum is required. Lower values result in an increased output voltage ripple in PFM mode. The minimum inductor value is 1.5mH, but an output capacitor of 22mF minimum is needed in this case. Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is recommended because during heavy load transient the inductor current rises above the calculated value. 1 * Vout DI Vin DI L + Vout I Lmax + I outmax ) L 2 L ƒ (4) With: f = Switching frequency (2.25 MHz typical) L = Inductor value ΔIL = Peak-to-peak inductor ripple current Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 21 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com ILmax = Maximum inductor current The highest inductor current occurs at maximum Vin. Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. Consideration must be given to the difference in the core material from inductor to inductor which has an impact on efficiency especially at high switching frequencies. See Table 2 and the typical applications for possible inductors. Table 2. Tested Inductors DEVICE INDUCTOR VALUE TYPE COMPONENT SUPPLIER 3.3mH LPS3015-332 (output current up to 1A) Coilcraft 2.2mH LPS3015-222 (output current up to 1A) Coilcraft 3.3mH VLCF4020T-3R3N1R5 TDK 2.2mH VLCF4020T-2R2N1R7 TDK 2.2mH LPS3010-222 Coilcraft 2.2mH LPS3015-222 Coilcraft 2.2mH VLCF4020-2R2 TDK DCDC3 converter Output Capacitor Selection The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the TPS650250x allows the use of small ceramic capacitors with a typical value of 10uF for each converter, without having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. Refer to Table 3 for recommended components. If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application requirements. For completeness, the RMS ripple current is calculated as: 1 * Vout 1 Vin I RMSCout + Vout L ƒ 2 Ǹ3 (5) At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: 1 * Vout 1 Vin DVout + Vout ) ESR 8 Cout ƒ L ƒ (6) ǒ Ǔ Where the highest output voltage ripple occurs at the highest input voltage, Vin. At light load currents the converters operate in Power Save Mode and output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. Typical output voltage ripple is less than 1% of the nominal output voltage. Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing interference with other circuits caused by high input voltage spikes. Each dcdc converter requires a 10uF ceramic input capacitor on its input pin VINDCDCx. The input capacitor can be increased without any limit for better input voltage filtering. The Vcc pin should be separated from the input for the DC/DC converters. A filter resistor of up to 10Ω and a 1mF capacitor should be used for decoupling the Vcc pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3mA can flow via this resistor into the Vcc pin when all converters are running in PWM mode. 22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 Table 3. Possible Capacitors CAPACITOR VALUE CASE SIZE 22mF 1206 TDK C3216X5R0J226M Ceramic 22mF 1206 Taiyo Yuden JMK316BJ226ML Ceramic 22mF 0805 TDK C2012X5R0J226MT Ceramic 22mF 0805 Taiyo Yuden JMK212BJ226MG Ceramic 10mF 0805 Taiyo Yuden JMK212BJ106M Ceramic 10mF 0805 TDK C2012X5R0J106M Ceramic COMPONENT SUPPLIER COMMENTS Output Voltage Selection The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down converter. See Table 4 for the default voltages if the pins are pulled to GND or to Vcc. Table 4. Voltage Options PIN LEVEL DEFDCDC1 DEFAULT OUTPUT VOLTAGE VCC 3.3V GND 2.80V DEFDCDC2 VCC 2.5V GND 1.8V DEFDCDC3 external voltage divider 0.6V to VinDCDC3 If a different voltage is needed, an external resistor divider can be added to the DEFDCDC1 or DEFDCDC2 pin as shown below: 10 R Vbat VCC 1 mF VDCDC1 L1 VINDCDC1 CIN VOUT L COUT EN_DCDC1 R1 DEFDCDC1 R2 AGND PGND When a resistor divider is connected to DEFDCDC1 or DEFDCDC2, the output voltage can be set from 0.6V up to the input voltage Vbat. The total resistance (R1+R2) of the voltage divider should be kept in the 1MΩ range in order to maintain a high efficiency at light load. VDEFDCDCx = 0.6V V OUT + VDEFDCDCx R1 ) R2 R2 R1 + R2 ǒ V OUT VDEFDCDCx Ǔ * R2 Voltage Change on VDCDC3 The output voltage of VDCDC3 is set with an external resistor divider at DEFDCDC3. This pin must not be connected to GND or VINDCDC3. The value of the resistor divider can be changed during operation to allow dynamic voltage scaling. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 23 TPS650250-Q1 SLVSAA7 – MARCH 2010 www.ti.com Vdd_alive Output The Vdd_alive LDO is typically connected to the Vdd_alive input of the Samsung application processor. It provides an output voltage of 1V at 30mA. It is recommended to add a capacitor of 2.2mF minimum to the Vdd_alive pin. The LDO can be disabled by pulling the EN_Vdd_alive pin to GND. LDO1 and LDO2 The LDOs in the TPS650250 are general purpose LDOs which are stable using ceramics capacitors. The minimum output capacitor required is 2.2mF. The LDOs output voltage can be changed to different voltages between 1V and 3.3V using an external resistor divider. Therefore they can also be used as general purpose LDOs in the application. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and therefore providing the highest efficiency. The total resistance (R5+R6) of the voltage divider should be kept in the 1MΩ range in order to maintain high efficiency at light load. VFBLDOx= 1.0V. V OUT + VFBLDOx R5 ) R6 R6 R5 + R6 ǒ V OUT VFBLDOx Ǔ * R6 Vcc-Filter An RC filter connected at the Vcc input is used to keep noise from the internal supply for the bandgap and other analog circuitry. A typical value of 1Ω and 1mF is used to filter the switching spikes, generated by the DC/DC converters. A larger resistor than 10Ω should not be used because the current into Vcc of up to 2.5mA causes a voltage drop at the resistor causing the undervoltage lockout circuitry connected at Vcc internally to switch off too early. 24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 TPS650250-Q1 www.ti.com SLVSAA7 – MARCH 2010 APPLICATION INFORMATION TYPICAL CONFIGURATION FOR THE SAMSUNG PROCESSOR S3C6400-533MHz The typical configuration for the Samsung processor S3C6400-533MHz is shown in Figure 18. TPS 650250 Vcc VIN 1 mF DCDC 1 1600 mA VINDCDC1 VIN L1 VDDHI (3.3V) 2.2 mH VDDLCD (3.3V) VDDPCM (3.3V) VINDCDC 2 DCDC 2 800 mA 10 mF VDDSYS (3.3V) 10 mF VDCDC2 VDD _MEM 0 (1.8V) VDD _MEM 1 (1.8V) VINDCDC 3 L3 10 mF DCDC 3 800 mA 2.2 mH VDDARM (0.9V / 1.1V) VDCDC3 10 mF R5 DEFDCDC3 DEFDCDC1 VIN VDDMMC (3.3V) VDCDC 1 L2 VIN VDDEXT (3.3V) 10 mF 10 mF VIN S3C6400 533 MHz 3.3 mH R6 DEFDCDC2 VLDO2 300 kW LDO 2 200 mA VDDADC (3.3V) 2.2 mF VDDDAC (3.3V) VDDOTG (3.3V) VDDUH (3.3V ) FB_LDO 2 130 kW VLDO1 EN_DCDC 1 LDO 1 200 mA EN_DCDC 2 EN_DCDC 3 VIN 33 kW VDDOTGI (1.1V) 2.2 mF FB_LDO1 330 kW VINLDO 1/2 1 mF Vdd_alive 1 V VIN VIN VDDALIVE 1 mF EN_LDO 1/2 VIO EN_VDDalive 1M R2 PWRFAIL PWRFAIL_SNS - R3 1V + GND APLL (1 V) AGND, PowerPAD EPLL (1 V) VIN VIN 10 mF 2.2 mH MPLL (1 V) VDDINT (1 V) SW EN EN MODE TPS62260 FB 22 pF GND 100 kW 10 mF 150 kW Figure 18. Samsung Processor Configuration Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS650250-Q1 25 PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPS650250QRHBRQ1 ACTIVE QFN RHB Pins Package Eco Plan (2) Qty 32 3000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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OTHER QUALIFIED VERSIONS OF TPS650250-Q1 : • Catalog: TPS650250 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS650250QRHBRQ1 Package Package Pins Type Drawing QFN RHB 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 5.3 1.5 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS650250QRHBRQ1 QFN RHB 32 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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