SN54/74LS196
SN54/74LS197
4-STAGE PRESETTABLE
RIPPLE COUNTERS
The SN54/74LS196 decade counter is partitioned into divide-by-two and divide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)
sequence or in a bi-quinary mode producing a 50% duty cycle output. The
SN54/74LS197 contains divide-by-two and divide-by-eight sections which
can be combined to form a modulo-16 binary counter. Low Power Schottky
technology is used to achieve typical count rates of 70 MHz and power dissipation of only 80 mW.
Both circuit types have a Master Reset (MR) input which overrides all other
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)
overrides clocked operations and asynchronously loads the data on the Parallel Data inputs (Pn) into the flip-flops. This preset feature makes the circuits
usable as programmable counters. The circuits can also be used as 4-bit
latches, loading data from the Parallel Data inputs when PL is LOW and storing the data when PL is HIGH.
•
•
•
•
•
•
•
4-STAGE PRESETTABLE
RIPPLE COUNTERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
14
1
Low Power Consumption — Typically 80 mW
High Counting Rates — Typically 70 MHz
Choice of Counting Modes — BCD, Bi-Quinary, Binary
Asynchronous Presettable
Asynchronous Master Reset
Easy Multistage Cascading
Input Clamp Diodes Limit High Speed Termination Effects
N SUFFIX
PLASTIC
CASE 646-06
14
1
CONNECTION DIAGRAM DIP (TOP VIEW)
D SUFFIX
SOIC
CASE 751A-02
14
1
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
CP1 (LS196)
CP1 (LS197)
MR
PL
P0–P3
Q0–Q3
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
LOADING (Note a)
HIGH
CP0
ORDERING INFORMATION
Clock (Active LOW Going Edge)
Input to Divide-by-Two Section
Clock (Active LOW Going Edge)
Input to Divide-by-Five Section
Clock (Active LOW Going Edge)
Input to Divide-by-Eight Section
Master Reset (Active LOW) Input
Parallel Load (Active LOW) Input
Data Inputs
Outputs (Notes b, c)
LOGIC SYMBOL
LOW
1.0 U.L.
1.5 U.L.
2.0 U.L.
1.75 U.L.
1.0 U.L.
0.8 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
c. In addition to loading shown, Q0 can also drive CP1.
FAST AND LS TTL DATA
5-372
Ceramic
Plastic
SOIC
SN54/74LS196 • SN54/74LS197
LOGIC DIAGRAM
LS196
LS197
FAST AND LS TTL DATA
5-373
SN54/74LS196 • SN54/74LS197
FUNCTIONAL DESCRIPTION
significant output.
The LS196 Decade Counter can be connected up to operate in two different count sequences, as indicated in the tables
of Figure 2. With the input frequency connected to CP0 and
with Q0 driving CP1, the circuit counts in the BCD (8, 4, 2, 1)
sequence. With the input frequency connected to CP1 and Q3
driving CP0, Q0 becomes the low frequency output and has a
50% duty cycle waveform. Note that the maximum counting
rate is reduced in the latter (bi-quinary) configuration because
of the interstage gating delay within the divide-by-five section.
The LS196 and LS197 have an asynchronous active LOW
Master Reset input (MR) which overrides all other inputs and
forces all outputs LOW. The counters are also asynchronously
presettable. A LOW on the Parallel Load input (PL) overrides
the clock inputs and loads the data from Parallel Data (P0 – P3)
inputs into the flip-flops. While PL is LOW, the counters act as
transparent latches and any change in the Pn inputs will be reflected in the outputs.
The LS196 and LS197 are asynchronously presettable decade and binary ripple counters. The LS196 Decade Counter
is partitioned into divide-by-two and divide-by-five sections
while the LS197 is partitioned into divide-by-two and divideby-eight sections, with all sections having a separate Clock input. In the counting modes, state changes are initiated by the
HIGH to LOW transition of the clock signals. State changes of
the Q outputs, however, do not occur simultaneously because
of the internal ripple delays. When using external logic to decode the Q outputs, designers should bear in mind that the unequal delays can lead to decoding spikes and thus a decoded
signal should not be used as a clock or strobe. The CP0 input
serves the Q0 flip-flop in both circuit types while the CP1 input
serves the divide-by-five or divide-by-eight section. The Q0
output is designed and specified to drive the rated fan-out plus
the CP1 input. With the input frequency connected to CP0 and
Q0 driving CP1, the LS197 forms a straightforward module-16
counter, with Q0 the least significant output and Q3 the most
Figure 2. LS196 COUNT SEQUENCES
DECADE (NOTE 1)
BI-QUINARY (NOTE 2)
COUNT
Q3
Q2
Q1
Q0
COUNT
Q0
Q3
Q2
Q1
0
1
2
3
4
5
6
7
8
9
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
8
9
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
NOTES:
1. Signal applied to CP0, Q0 connected to CP1.
2. Signal applied to CP1, Q3 connected to CP0.
MODE SELECT TABLE
INPUTS
RESPONSE
MR
PL
CP
L
H
H
X
L
H
X
X
Reset (Clear)
Parallel Load
Count
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
= HIGH to Low Clock Transition
FAST AND LS TTL DATA
5-374
SN54/74LS196 • SN54/74LS197
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
– 55
0
25
25
125
70
°C
IOH
Output Current — High
54, 74
– 0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Min
Parameter
Typ
Max
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
Data, PL
MR, CP0 (LS196)
MR, CP0, CP1 (LS197)
CP1 (LS196)
20
40
40
80
Data, PL
MR, CP0 (LS196)
MR, CP0, CP1 (LS197)
CP1 (LS196)
0.1
0.2
0.2
0.4
IIL
Input LOW Current
Data, PL
MR
CP0
CP1 (LS196)
CP1 (LS197)
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
Unit
2.0
54
0.7
74
0.8
– 0.65
– 1.5
Test Conditions
V
Guaranteed Input HIGH Voltage for
All Inputs
V
Guaranteed Input LOW Voltage for
All Inputs
V
VCC = MIN, IIN = – 18 mA
54
2.5
3.5
V
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
V
IOL = 4.0 mA
74
0.35
0.5
V
IOL = 8.0 mA
µA
VCC = MAX, VIN = 2.7 V
mA
VCC = MAX, VIN = 7.0 V
mA
VCC = MAX, VIN = 0.4 V
– 100
mA
VCC = MAX
27
mA
VCC = MAX
– 0.4
– 0.8
– 2.4
– 2.8
– 1.3
– 20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-375
SN54/74LS196 • SN54/74LS197
AC CHARACTERISTICS (TA = 25°C)
Limits
LS196
Symbol
Parameter
Min
Typ
30
40
LS197
Max
Min
Typ
30
40
Max
Unit
fMAX
Maximum Clock Frequency
tPLH
tPHL
CP0 Input to
Q0 Output
8.0
13
15
20
8.0
14
15
21
ns
tPLH
tPHL
CP1 Input to
Q1 Output
16
22
24
33
12
23
19
35
ns
tPLH
tPHL
CP1 Input to
Q2 Output
38
41
57
62
34
42
51
63
ns
tPLH
tPHL
CP1 Input to
Q3 Output
12
30
18
45
55
63
78
95
ns
tPLH
tPHL
Data to Output
20
29
30
44
18
29
27
44
ns
tPLH
tPHL
PL Input to
Any Output
27
30
41
45
26
30
39
45
ns
tPHL
MR Input to Any Output
34
51
34
51
ns
Max
Unit
Test Conditions
MHz
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Limits
LS196
Symbol
Parameter
Min
Typ
LS197
Max
Min
Typ
tW
CP0 Pulse Width
20
20
ns
tW
CP1 Pulse Width
30
30
ns
tW
PL Pulse Width
20
20
ns
tW
MR Pulse Width
15
15
ns
ts
Data Input Setup Time — HIGH
10
10
ns
ts
Data Input Setup Time — LOW
15
15
ns
th
Data Hold Time — HIGH
10
10
ns
th
Data Hold Time — LOW
10
10
ns
trec
Recovery Time
30
30
ns
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from HIGH to LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from HIGH to LOW that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from HIGH to
LOW and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from HIGH to LOW in order to recognize and transfer
LOW Data to the Q outputs.
FAST AND LS TTL DATA
5-376
SN54/74LS196 • SN54/74LS197
AC WAVEFORMS
Figure 1
NOTE: PL = LOW
Figure 2
Figure 3
* The shaded areas indicate when the input is permitted
* to change for predictable output performance
Figure 4
Figure 5
FAST AND LS TTL DATA
5-377
Case 751A-02 D Suffix
14-Pin Plastic
SO-14
"!
!! ( ( ! "
"
! " # %# (" ! "# !#
-A-
8
P
-B1
!
#!
"
#! !
* ! !" $ !"
M
J
F
R X 45°
K
D "
!
! "
*
C
G
"
7
& 14
"#! !
!
!
°
°
°
°
)
)
)
)
Case 632-08 J Suffix
14-Pin Ceramic Dual In-Line
-A-
"!
! "
!
& 14
8
"
! " "
-B1
! 7
* "
-T-
L
G
J "
!
&
# * !" $ !"
"
M
N
D ! " *
K
F
$ " $
" "
C
$
& !
!
!
!
°
!
°
°
°
)
)
)
)
Case 646-06 N Suffix
14-Pin Plastic
"!
14
"
B
1
A
! ( ! " # # F
L
C
J
N
K
M
FAST AND LS TTL DATA
5-378
! "
* !" $ !"
D
! $
!
H
#! "
"
! ( " "
7
G
! $" '' !" " !" " %#
8
*
!
!
!
°
°
!
°
°
#
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
◊
FAST AND LS TTL DATA
5-379