PIP212-12M DC-to-DC converter powertrain Rev. 04 — 23 October 2006 Product data sheet 1. General description The PIP212-12M is a fully optimized powertrain for high current high frequency synchronous buck DC-to-DC applications. The PIP212-12M replaces two power MOSFETs, a Schottky diode and a driver IC, resulting in a significant increase in power density. The integrated solution allows for optimization of individual components and greatly reduces the parasitics associated with conventional discrete solutions, resulting in higher system efficiencies at higher frequency operation. 2. Features n n n n n n n n n n n n n Input conversion ranges from 3.3 V to 16 V Output voltages from 0.8 V to 6 V Capable of up to 35 A maximum output current at 1 MHz Operating frequency up to 1 MHz Peak system efficiency > 90 % at 500 MHz Automatic Dead-time Reduction (ADR) for maximum efficiency Internal thermal shutdown Auxiliary 5 V output Power ready output flag Power sequencing functions Internal 6.5 V regulator for efficient gate drive Compatible for single and multi-phase Pulse Width Modulation (PWM) controllers Low-profile, surface-mounted package (8 mm × 8 mm × 0.85 mm) 3. Applications n n n n High-current DC-to-DC point-of-load converters Small form-factor voltage regulator modules Microprocessor and memory voltage regulators Intel DriverMOS (DrMOS) compatible PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 4. Ordering information Table 1. Ordering information Type number PIP212-12M Package Name Description Version HVQFN56 plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 × 8 × 0.85 mm SOT684-4 5. Block diagram CBN VDDO CBP 5 PIP212-12M VDDC VDDG_EN VDDG REG5V 10 4 2 6.5 V REG INTERNAL 5 V REG UVLO 8, 11 to 20 BOOST SWITCH 3 54 upper driver 5 V REG 5V VI 42 to 50 56 5V 30 kΩ DISABLE PRDY 55 CONTROL LOGIC AND DEAD-TIME CONTROL VO OTP VDDG 53 lower driver signal ground 1, 7, 51 22 to 41 VSSC VSSO 03ao37 power ground A bootstrap switch is integrated into the design of the PIP212-12M between VDDC and CBN Fig 1. Block diagram PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 2 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 6. Functional diagram conversion supply control circuit supply VDDG VDDC VDDO REG5V PWM input 100 nF CBP PIP212-12M CBN VI Lo(ext) output VO DISABLE Co(ext) VSSO VSSC signal ground power ground 03ao39 Fig 2. Simplified functional block diagram of a synchronous DC-to-DC converter output stage 7. Pinning information 43 VO 44 VO 45 VO 46 VO 47 VO 48 VO 49 VO 50 VO 51 VSSC 52 n.c 53 PRDY 54 REG5V terminal 1 index area 55 DISABLE 56 VI 7.1 Pinning VSSC 1 42 VO VDDG_EN 2 41 VSSO VDDG 3 VDDC 4 CBP 5 n.c 6 37 VSSO VSSC 7 36 VSSO VDDO 8 n.c. 9 40 VSSO VSSC PAD 1 39 VSSO PIP212-12M 38 VSSO 35 VSSO 34 VSSO VO PAD 3 CBN 10 33 VSSO VDDO PAD 2 VDDO 11 32 VSSO VSSO 28 VSSO 27 VSSO 26 VSSO 25 VSSO 24 VSSO 23 VSSO 22 VO_SENSE 21 VDDO 20 VDDO 19 VDDO 18 29 VSSO VDDO 17 30 VSSO VDDO 14 VDDO 16 31 VSSO VDDO 13 VDDO 15 VDDO 12 03ao38 Transparent top view Fig 3. Pin configuration PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 3 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 7.2 Pin description Table 2. Pin description Symbol Pin Type Description VDDC 4 - control circuit supply voltage VDDO 8, 11 to 20, pad 2 I output stage supply voltage VSSC 1, 7, 51, pad 1 - control circuit ground VSSO 22 to 41 - output stage ground supply voltage VI 56 I pulse width modulated input VO 42 to 50, pad 3 O output voltage VO_SENSE 21 O sense connection to VO often required by PWM for current sensing CBP 5 - connection to bootstrap capacitor CBN 10 - connection to bootstrap capacitor VDDG_EN 2 I enables internal 6.5 V regulator for VDDG VDDG 3 - gate driver supply voltage PRDY 53 O indicates that VDDC is above the UVLO (UnderVoltage Lockout) level (open drain) REG5V 54 O 5 V regulated supply output DISABLE 55 I/O disable driver function (active LOW) n.c. 6, 9, 52 - not connected - leave open or connected to GND on PCB (Printed-Circuit Board) layout 8. Functional description 8.1 Basic operation The PIP212-12M combines two MOSFET transistors and a MOSFET driver in a thermally enhanced low inductance package for use in high frequency and high efficiency synchronous buck DC-to-DC converters; see Figure 2. The two MOSFETs are connected in a half bridge configuration between VDDO and VSSO. The mid point of the two transistors is VO which is connected to the output of a DC-to-DC converter via an inductor. A logic HIGH signal on the VI pin causes the lower MOSFET to be switched off and the upper MOSFET to be switched on. Current will then flow from the supply (VDDO), through the upper MOSFET and the inductor (Lo(ext)) to the output. A logic LOW signal on the VI pin causes the upper MOSFET to be turned off and the lower MOSFET to be switched on. Current then flows from the power ground (VSSO), through the lower MOSFET and the inductor (Lo(ext)), to the output. The output voltage is determined by the ratio of time that the upper and lower MOSFETs conduct. 8.2 UnderVoltage Lockout (UVLO) The UVLO function ensures the correct operation of the control circuit during a power-up and power-down sequence. Power to the control circuit is provided by the VDDC pin. This voltage is internally monitored to ensure that if VDDC is below the UVLO threshold, the DISABLE pin is internally pulled LOW and both MOSFETs are off. This is indicated by the power ready (PRDY) flag, an open drain output that is pulled LOW whenever VDDC is below the UVLO threshold. PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 4 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 8.3 Upper driver operation The gate drive to the upper MOSFET is provided by a bootstrap capacitor (typically 100 nF) that is placed between the CBP and CBN pins. This capacitor is charged via an internal boost switch to a voltage within a few millivolts of VDDC up to a maximum of 12 V (this is to prevent excessive gate charge losses when VDDC > 12 V). The upper MOSFET will be switched according to PWM input once the boost capacitor voltage is above Vth(CBP-CBN) on. When ever the voltage is below Vth(CBP-CBN) off the upper MOSFET will remain off. 8.4 VDDG regulator The gate drive to the lower MOSFET is provided by the VDDG pin. A 1 µF capacitor should be connected between this pin and VSSC. For minimum power loss within the PIP212-12M, an external power supply of between 5 V and 12 V should be connected to this pin. The optimum value for this voltage is dependent on the application but in the majority of cases a 5 V supply is recommended; see Figure 11. In cases where the VDDG maximum voltage will not be exceeded, the VDDG pin can be connected to the VDDC pin and the VDDG capacitor can be omitted; see Figure 13. When VDDC is connected to a supply greater than 9 V, an internal 6.5 V regulator connected to VDDG can be used to provide the gate drive for the lower MOSFET; see Figure 12. The VDDG regulator is enabled by leaving the VDDG_EN pin open resulting in this pin being pulled internally to 5 V. If an external supply is to be connected to VDDG then the VDDG_EN pin must be connected to VSSC to disable the internal VDDG regulator. Table 3. VDDG biasing VDDG_EN VDDG Open circuit internal 6.5 V regulator used (VDDC > 9 V) VSSC connection to external supply required 8.5 3-state function If the input to VI from the PWM controller becomes high impedance, then the VI input is driven to 2.5 V by an internal voltage divider. A voltage on the VI pin that is in-between the VIH and VIL levels and present for longer than td(3-state), causes both MOSFETs to be turned off. Normal operation commences once the VI input is outside this window for longer than td(3-state). 8.6 Automatic Dead-time Reduction (ADR) Protection against cross-conduction (shoot-through) is achieved via the insertion of a delay (or dead-time) between the switching off of one MOSFET and the switching on of the other MOSFET. The automatic dead-time reduction feature continuously monitors the body diode of the lower MOSFET adjusting the dead-time to minimize body diode conduction. This reduces power loss in both the upper and lower MOSFETs due to the reduction in body diode conduction and reverse recovery charge. The lower power dissipation leads to higher system efficiency and enables higher frequency operation. PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 5 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 8.7 Over Temperature Protection (OTP) Protection against over temperature is provided by an internal thermal shutdown incorporated into the control circuit. When the control circuit die temperature exceeds the upper thermal trip level, both MOSFETs are switched off and the internal VDDG regulator disabled. This state continues until the die temperature falls below the lower trip temperature. This function is only operational when VDDC is above the UVLO level. 8.8 Disable This is the disable or enable function of the driver. Pulling the DISABLE pin LOW switches off both MOSFETs and disables the REG5V output. This pin is internally pulled LOW whilst VDDC remains below the UVLO threshold. Once VDDC exceeds the UVLO threshold, this pin is pulled HIGH by an internal resistor. In this way the driver will enable itself unless there is an external pull down. In multiphase applications, connecting the DISABLE pins of multiple PIP212-12M devices together will ensure that all devices will only become enabled when the voltage on the VDDC pins of all of the devices has exceeded the UVLO threshold; see Figure 10. 8.9 Reg5V This function provides a low current regulated 5 V output voltage suitable for providing power to a PWM controller. It is operational when both PRDY and DISABLE are HIGH. Operation as a 5 V power supply is only guaranteed when VDDC is > 7 V. This pin can also be used as part of an enable function for a PWM controller; this ensures that the PWM is enabled only when the PIP212-12M is fully operational (i.e. both PRDY and DISABLE are HIGH). PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 6 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 9. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDDC Conditions Min Max Unit control circuit supply voltage −0.5 +15 V VDDO output stage supply voltage −0.5 +24 V VI input voltage −0.5 +12.6 V VDDG gate driver supply voltage −0.5 +12.6 V VO output voltage −0.5 VDDO + 0.5 V −0.5 VO + 15 V - 35 A - 60 A Vc(bs) bootstrap capacitance voltage IO(AV) average output current VDDC = 12 V; Tpcb ≤ 90 °C; fi = 1 MHz IORM repetitive peak output current VDDC = 12 V; tp ≤ 10 µs VPRDY voltage on pin PRDY −0.5 +12.6 V VDISABLE voltage on pin DISABLE −0.5 +12.6 V VREG5V voltage on pin REG5V total power dissipation Ptot [1] −0.5 +12.6 V Tmb = 25 °C [2] - 25 W Tmb = 90 °C [2] - 12 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C [1] Pulse width and repetition rate limited by maximum value of Tj. [2] Assumes a thermal resistance from junction to mounting base of 5 K/W. 10. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base device tested with upper and lower MOSFETs in series - 3 5 K/W PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 7 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 11. Characteristics Table 6: Characteristics VDDC = 12 V; Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 25 °C ≤ Tj ≤ 150 °C 4.5 12 14 V 4.05 4.2 4.45 V turn off 3.7 3.9 4.1 V turn on 3.85 4.1 4.35 V Static characteristics VDDC control circuit supply voltage Vth(UVLO) undervoltage lockout threshold voltage turn on Vth(CBP-CBN) threshold voltage between pin CBP and pin CBN 2.35 2.6 2.85 V VIH HIGH-level input voltage turn off [1] 3.3 3.5 3.7 V VIL LOW-level input voltage [1] 1.4 1.5 1.6 V ILI input leakage current 0 V ≤ VI ≤ 5 V - 180 - µA IDDC control circuit supply current fi = 0 Hz, VI = 0 V - 8.4 - mA fi = 500 kHz, VDDG_EN = open - 50 - mA fi = 500 kHz, VDDG_EN = ground - 12 - mA VDDG gate driver supply voltage IL = 65 mA 5.75 6.5 7.25 V VREG5V voltage on pin REG5V IL ≤ IREG5V minimum, VDDC > 7 V 4.5 5.0 5.5 V IREG5V current on pin REG5V VREG5V = 4.5 V 18 - - mA Vth(en) enable threshold voltage on pin DISABLE, VDDC > 4.5 V 2.9 3.2 3.5 V Vth(dis) disable threshold voltage on pin DISABLE, VDDC > 4.5 V 1.4 1.6 1.8 V Ttrip(otp) over-temperature protection trip temperature - 160 - °C Ttrip(otp)hys hysteresis of over-temperature protection trip temperature - 40 - °C Ptot total power dissipation fi = 500 kHz - 4.5 - W fi = 1 MHz - 5.8 - W IO = 10 A; VCBP = 12 V - 6.5 - mΩ IO = 10 A; VDDG = 12 V - 1.9 - mΩ IO = 10 A; VDDG = 6.5 V - 2.1 - mΩ VDDO = 12 V; IO(AV) = 12.5 A - - 80 ns VDDO = 12 V; IO(AV) = 25 A; VO = 1.3 V; Tpcb = 90 °C; Upper MOSFET RDSon drain-source on-state resistance Lower MOSFET RDSon drain-source on-state resistance Dynamic characteristics td(on)(IH-OH) turn-on delay time from input HIGH to output HIGH td(off)(IL-OL) turn-off delay time from input LOW to output LOW - - 75 ns td(3-state) 3 state delay time - 90 - ns [1] If the input voltage remains between VIH and VIL (2.5 V typ) for longer than td(3-state), then both MOSFETs are turned off. PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 8 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 003aab391 12 Ptot (W) 10 003aaa834 1.3 a 1.2 8 fi = 1 MHz 1.1 6 fi = 500 KHz 4 1.0 2 0.9 0 0 10 20 30 IO (A) 0 40 VDDC = 12 V; VDDO = 12 V; VO = 1.3 V; VDDG = 5 V 4 8 12 16 VDDO (V) VDDC = 12 V; VO = 1.3 V; fi = 1 MHz; IO(AV) = 25 A; VDDG = 5 V P tot a = ---------------------------------------P tot ( V = 12 V) DDO Fig 4. Total power dissipation as a function of average output current; typical values 003aaa835 1.8 Fig 5. Normalized power dissipation as a function of output stage supply voltage; typical values 003aaa836 1.2 b c 1.6 1.0 1.4 1.2 0.8 1.0 0.8 0 2 4 VO (V) 6 0.6 200 600 800 1000 f (kHz) VDDC = 12 V; VDDO = 12 V; fi = 1 MHz; IO(AV) = 25 A; VDDG = 5 V VDDC = 12 V; VDDO = 1.3 V; VO = 1.3 V; IO(AV) = 25 A; VDDG = 5 V P tot c = -----------------------------------P tot ( f = 1 MHz ) P tot b = ----------------------------------P tot ( V = 1.3 V ) O i Fig 6. Normalized power dissipation as a function of output voltage; typical values Fig 7. Normalized power dissipation as a function of input frequency; typical values PIP212-12M_4 Product data sheet 400 © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 9 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 003aaa837 1.3 d e 1.2 1.2 1.1 1.1 1.0 1.0 0.9 003aaa838 1.3 0.9 6 8 10 12 VDDC (V) 14 VDDO = 12 V; VO = 1.3 V; fi = 1 MHz; IO(AV) = 25 A; VDDG = 5 V 4 8 10 12 VDDG (V) VDDC = 12 V; VDDO = 12 V; fi = 1 MHz; IO(AV) = 25 A; VDDG = 5 V P tot e = -------------------------------------P tot ( V = 5 V) P tot d = ---------------------------------------P tot ( V = 12 V ) DDC DDG Fig 8. Normalized power dissipation as a function of control circuit supply voltage; typical values Fig 9. Normalized power dissipation as a function of gate driver supply voltage; typical values PIP212-12M_4 Product data sheet 6 © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 10 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 12. Application information 12.1 Typical application conversion supply control circuit supply 22 µF (4×) 10 Ω 1 µF 1 µF VDDG VDDC REG5V 100 µF (2×) VSSO 22 µF (4×) 10 Ω 1 µF VDDG VDDC REG5V VDDO PIP212-12M CBN VI VCC 100 nF CBP 360 nH VO DISABLE VSSC 100 µF (2×) VSSO PWM 1 PWM CONTROLLER 360 nH VO DISABLE VSSC 1 µF 100 nF CBP PIP212-12M CBN VI 100 nF VDDO PWM 1 PWM 1 PWM 1 22 µF (4×) 10 Ω 1 µF 1 µF VDDG VDDC REG5V VDDO PIP212-12M CBN VI 360 nH VO DISABLE 100 µF (2×) VSSO VSSC 22 µF (4×) 10 Ω 1 µF 100 nF CBP 1 µF VDDG signal ground VDDC REG5V power ground VI VDDO PIP212-12M CBN 360 nH VO DISABLE VSSC 100 nF CBP VSSO voltage output 100 µF (2×) 03ao41 Fig 10. Typical application circuit using the PIP212-12M in a four-phase converter A typical four-phase buck converter is shown in Figure 10. This system uses four PIP212-12M devices to deliver a continuous output current of 120 A at an operating frequency of 500 kHz. PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 11 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 12.2 VDDG supply options The following options can be used for the lower MOSFET driver supply (VDDG). conversion supply control circuit supply 5 V external gate drive VDDC VDDG VDDO 100 nF CBP PWM input VI PIP212-12M CBN Lo(ext) VDDG_EN VSSC Co(ext) VSSO signal ground output VO power ground 03ar56 Fig 11. Dual supply operation using 5 V external supply for VDDG conversion supply control circuit supply VDDC VDDG VDDO 100 nF CBP PWM input VI PIP212-12M CBN Lo(ext) open circuit VDDG_EN VSSC Co(ext) VSSO signal ground output VO power ground 03ar57 Fig 12. Single supply operation using internal supply for VDDG conversion supply control circuit supply VDDC VDDG VDDO 100 nF CBP PWM input VI PIP212-12M VDDG_EN VSSC signal ground CBN Lo(ext) output VO Co(ext) VSSO power ground 03ar55 Fig 13. Single supply operation using external supply for VDDG PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 12 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 12.3 DrMOS compatibility The PIP212-12M can be configured to be compatible with the Intel DrMOS specification. Conformance to the Intel DrMOS specification requires that an external power supply to the VDDG pin is used and hence the internal VDDG regulator must be disabled by connecting the VDDG_EN pin to VSSC. The PRDY flag is not used and should be left unconnected on the PCB. The external boost capacitor should also be connected between CBP and VO and not CBP and CBN with the CBN pin being left unconnected on the PCB. In addition, VSSC pin 7 and VSSO pin 39 to pin 41 should be left unconnected on the PCB. Note that the sizes of PAD 1, PAD 2 and PAD 3 can vary between different DrMOS vendors. The PCB footprint must be modified to take the pinning modifications and pad size differences into account. To ensure footprint compatibility with other DrMOS products, it is recommended that the latest multiple vendor compatibility PCB footprint contained within the Intel DrMOS specification is used and that the relevant DrMOS product data sheet is checked for compatibility. 13. Marking terminal 1 index area TYPE No. RoHS compliant G = RoHS indicator Mask code N1I = Mask layout version DIFFUSION LOT No. Diffusion centre h = Hazel Grove, UK MANUFACTURING CODE COUNTRY OF ORIGIN Assembly centre f = Amkor Korea hfGYYWWN1I Date code YY = last two digits of year WW = week number 03ai72 03ao89 TYPE No: PIP212-12M_NN (NN is revision number) DIFFUSION LOT No: 7 characters MANUFACTURING CODE; see Figure 15 COUNTRY OF ORIGIN: Korea Fig 14. SOT684-4 marking Fig 15. Interpretation of manufacturing code PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 13 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 14. Package outline HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm SOT684-4 B D D1 A terminal 1 index area A E1 A4 c E A1 detail X C e1 1/2 e e 15 28 L y y1 C v M C A B w M C b 29 14 e Eh1 Eh e2 1/2 e Eh2 1 terminal 1 index area 42 56 43 Dh1 Dh2 0 2.5 X 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A4 b c D D1 D h1 D h2 E E1 Eh E h1 E h2 e e1 e2 L v w y y1 mm 0.9 0.05 0.00 0.70 0.65 0.30 0.18 0.2 8.1 7.9 7.8 7.7 2.65 2.35 3.55 3.25 8.1 7.9 7.8 7.7 6.45 6.15 3.25 2.95 2.85 2.55 0.5 6.5 6.5 0.5 0.3 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT684-4 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 03-10-23 04-09-14 Fig 16. Package outline SOT684-4 (HVQFN56) PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 14 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 15. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 15 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 17) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 7 and 8 Table 7. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 8. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 17. PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 16 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Mounting 16.1 PCB design guidelines The terminals on the underside of the package are rectangular in shape with a rounded edge on the inside. Electrical connection between the package and the printed-circuit board is made by printing solder paste onto the PCB footprint followed by component placement and reflow soldering. The PCB footprint shown in Figure 18 is designed to form reliable solder joints. The use of solder resist between each solder land is recommended. PCB tracks should not be routed through the corner areas shown in Figure 18. This is because there is a small, exposed remnant of the leadframe in each corner of the package, left over from the cropping process. Good surface flatness of the PCB lands is desirable to ensure accuracy of placement after soldering. Printed-circuit boards that are finished with a roller tin process tend to leave small lumps of tin in the corners of each land. Levelling with a hot air knife improves flatness. Alternatively, an electro-less silver or silver immersion process produces completely flat PCB lands. PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 17 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 9.25 (2×) 8.30 (2×) 6.20 (2×) 0.475 1.40 0.50 0.30 1.60 0.45 7.04 (4×) 0.25 0.40 0.70 (3×) 0.525 e = 0.50 0.05 0.615 0.80 (2×) 1.90 0.50 0.29 (56×) solder lands Cu pattern 0.425 2.00 0.075 clearance 0.50 7.20 (2×) 9.00 (2×) 001aaa064 0.150 solder paste 0.025 placement area occupied area All dimensions in mm Fig 18. PCB footprint for SOT684-4 package (reflow soldering) 16.2 Solder paste printing The process of printing the solder paste requires care because of the fine pitch and small size of the solder lands. A stencil thickness of 0.125 mm is recommended. The stencil apertures can be made the same size as the solder lands in Figure 18. The type of solder paste recommended for MLF (Micro Lead-Frame) packages is “No clean”, Type 3, due to the difficulty of cleaning flux residues from beneath the MLF package. PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 18 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 17. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PIP212-12M_4 20061023 Product data sheet ECN 211443 PIP212-12M_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. PIP212-12M_3 20060803 Product data sheet - PIP212-12M_2 PIP212-12M_2 (9397 750 14586) 20050302 Preliminary data sheet - PIP212-12M_1 PIP212-12M_1 (9397 750 14464) 20041223 Objective data sheet - - PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 19 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] PIP212-12M_4 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 04 — 23 October 2006 20 of 21 PIP212-12M NXP Semiconductors DC-to-DC converter powertrain 20. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 10 11 12 12.1 12.2 12.3 13 14 15 15.1 15.2 15.3 15.4 16 16.1 16.2 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . 4 UnderVoltage Lockout (UVLO) . . . . . . . . . . . . . 4 Upper driver operation . . . . . . . . . . . . . . . . . . . 5 VDDG regulator . . . . . . . . . . . . . . . . . . . . . . . . . 5 3-state function . . . . . . . . . . . . . . . . . . . . . . . . . 5 Automatic Dead-time Reduction (ADR) . . . . . . 5 Over Temperature Protection (OTP) . . . . . . . . . 6 Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reg5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal characteristics. . . . . . . . . . . . . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . 11 Typical application. . . . . . . . . . . . . . . . . . . . . . 11 VDDG supply options . . . . . . . . . . . . . . . . . . . . 12 DrMOS compatibility . . . . . . . . . . . . . . . . . . . . 13 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Introduction to soldering . . . . . . . . . . . . . . . . . 15 Wave and reflow soldering . . . . . . . . . . . . . . . 15 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PCB design guidelines . . . . . . . . . . . . . . . . . . 17 Solder paste printing. . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 23 October 2006 Document identifier: PIP212-12M_4