PIP212-12M DC-to-DC converter powertrain Rev. 02 — 2 March 2005 Preliminary data sheet 1. General description The PIP212M-12M is a fully optimized powertrain for high current high frequency synchronous buck DC-to-DC applications. The PIP212M-12M replaces two power MOSFETs, a Schottky diode and a driver IC, resulting in a significant increase in power density. The integrated solution allows for optimization of individual components and greatly reduces the parasitics associated with conventional discrete solutions, resulting in higher system efficiencies at higher frequency operation. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Input conversion range from 3.3 V to 16 V Output voltages from 0.8 V to 6 V Capable of up to 30 A maximum output current Operating frequency up to 1 MHz Peak system efficiency > 90 % at 500 kHz Automatic Dead-time Reduction (ADR) for maximum efficiency Internal thermal shutdown Auxiliary 5 V output Power ready output flag Power sequencing functions Fault flag for lost phase detection Internal 6.5 V regulator for efficient gate drive Compatible with single and multi-phase PWM controllers Internal boost switch for high efficiency and low noise Low-profile, surface-mounted package (8 mm × 8 mm × 0.85 mm) 3. Applications ■ ■ ■ ■ ■ High-current DC-to-DC point-of-load converters Small form-factor voltage regulator modules Microprocessor and memory voltage regulators Intel® compatible VRM (VRM9 and VRM10) Intel® Driver MOS (DrMOS) compatible PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 4. Ordering information Table 1: Ordering information Type number PIP212-12M Package Name Description Version HVQFN56 plastic thermal enhanced very thin quad flat package; no leads; SOT684-4 56 terminals; body 8 × 8 × 0.85 mm 5. Block diagram CBN VDDO CBP 5 PIP212-12M VDDC VDDG_EN VDDG REG5V 10 4 2 6.5 V REG INTERNAL 5 V REG UVLO 8, 11 to 20 BOOST SWITCH 3 54 upper driver 5 V REG 5V VI 42 to 50 56 5V 30 kΩ DISABLE PRDY AIS 55 CONTROL LOGIC AND DEAD-TIME CONTROL OTP VDDG 53 lower driver 52 signal ground VO 1, 7, 51 22 to 41 VSSC VSSO 03ao37 power ground A bootstrap switch is integrated into the design of the PIP212-12M between VDDC and CBN Fig 1. Block diagram 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 2 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 6. Pinning information 43 VO 44 VO 45 VO 46 VO 47 VO 48 VO 49 VO 50 VO 51 VSSC 52 AIS 53 PRDY terminal 1 index area 54 REG5V 56 VI 55 DISABLE 6.1 Pinning VSSC 1 42 VO VDDG_EN 2 41 VSSO VDDG 3 VDDC 4 CBP 5 n.c 6 37 VSSO VSSC 7 36 VSSO VDDO 8 n.c. 9 40 VSSO VSSC PAD 1 39 VSSO PIP212-12M 38 VSSO 35 VSSO 34 VSSO VO PAD 3 CBN 10 33 VSSO VDDO PAD 2 VDDO 11 32 VSSO VSSO 28 VSSO 27 VSSO 26 VSSO 25 VSSO 24 VSSO 23 VSSO 22 VO_SENSE 21 VDDO 20 VDDO 19 VDDO 18 29 VSSO VDDO 17 30 VSSO VDDO 14 VDDO 16 31 VSSO VDDO 13 VDDO 15 VDDO 12 03ao38 Transparent top view Fig 2. Pin configuration 6.2 Pin description Table 2: Pin description Symbol Pin Type Description VDDC 4 - VDDO 8, 11 to 20, pad 2 I output stage supply voltage VSSC 1, 7, 51, pad 1 - control circuit ground VSSO 22 to 41 - output stage (supply) ground VI 56 I pulse width modulated input VO 42 to 50, pad 3 O output voltage O sense connection to VO often required by PWM for current sensing VO_SENSE 21 control circuit supply voltage CBP 5 - connection for bootstrap capacitor CBN 10 - connection for bootstrap capacitor VDDG_EN 2 I enables internal 6.5 V regulator for VDDG VDDG 3 - gate drive supply voltage AIS 52 O indicates the switching status of VO (open drain) PRDY 53 O indicates that VDDC is above the UVLO level (open drain) 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 3 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain Table 2: Pin description …continued Symbol Pin Type Description REG5V 54 O 5 V regulated supply output DISABLE 55 I/O disable driver function (active LOW) n.c. 6, 9 - not connected 7. Functional description 7.1 Basic operation conversion supply control circuit supply VDDG VDDC REG5V PWM input VDDO 100 nF CBP PIP212-12M CBN VI DISABLE VSSC signal ground Lout output VO Cout VSSO power ground 03ao39 Fig 3. Simplified functional block diagram of a synchronous DC-to-DC converter output stage The PIP212-12M combines two MOSFET transistors and a MOSFET driver in a thermally enhanced low inductance package for use in high frequency and high efficiency synchronous buck DC-to-DC converters; see Figure 3. The two MOSFETs are connected in a half bridge configuration between VDDO and VSSO. The mid point of the two transistors is VO which is connected to the output of a DC-to-DC converter via an inductor. A logic HIGH signal on the VI pin causes the lower MOSFET to be switched off and the upper MOSFET to be switched on. Current will then flow from the supply (VDDO), through the upper MOSFET and the inductor (Lout) to the output. A logic LOW signal on the VI pin causes the upper MOSFET to be turned off and the lower MOSFET to be switched on. Current then flows from the power ground (VSSO), through the lower MOSFET and the inductor (Lout), to the output. The output voltage is determined by the ratio of time that the upper and lower MOSFETs conduct. 7.2 Undervoltage Lockout (UVLO) The UVLO function ensures the correct operation of the control circuit during a power-up and power-down sequence. Power to the control circuit is provided by the VDDC pin. This voltage is internally monitored to ensure that if VDDC is below the UVLO threshold, the DISABLE pin is internally pulled LOW and both MOSFETs are off. This is indicated by the power ready (PRDY) flag, an open drain output that is pulled LOW whenever VDDC is below the UVLO threshold. 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 4 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 7.3 Boost switch The gate drive to the upper MOSFET is provided by a bootstrap capacitor (typically 100 nF) that is placed between the CBP and CBN pins. This capacitor is charged via an internal boost switch to a voltage within a few millivolts of VDDC up to a maximum of 12 V (this is to prevent excessive gate charge losses when VDDC > 12 V). The upper MOSFET will be switched according to PWM input once the boost capacitor voltage is above 4.3 V. When ever the voltage is below 2.7 V, the upper MOSFET will remain off. 7.4 VDDG regulator The gate drive to the lower MOSFET is provided by the VDDG pin. A 1 µF capacitor should be connected between this pin and VSSC. For minimum power loss within the PIP212-12M, an external power supply of between 5 V and 12 V should be connected to this pin. The optimum value for this voltage is dependent on the application but in the majority of cases a 5 V supply is recommended; see Figure 11. In cases where the VDDG maximum voltage will not be exceeded, the VDDG capacitor can be omitted by connecting the VDDG and VDDC pins; see Figure 13. When VDDC is connected to a supply greater than 9 V, an internal 6.5 V regulator connected to VDDG can be used to provide the gate drive for the lower MOSFET; see Figure 12. The VDDG regulator is enabled by leaving the VDDG_EN pin open resulting in this pin being pulled internally to 5 V. If an external supply is to be connected to VDDG then the VDDG_EN pin must be connected to VSSC to disable the internal VDDG regulator. Table 3: VDDG biasing VDDG_EN VDDG Open circuit internal 6.5 V regulator used (VDDC > 9 V) VSSC connection to external supply required 7.5 3-state function If the input to VI from the PWM controller becomes high impedance, then the VI input is driven to 2.5 V by an internal voltage divider. A voltage on the VI pin that is in-between the VIH and VIL levels and present for longer than td(3-state), causes both MOSFETs to be turned off. Normal operation commences once the VI input is outside this window for longer than td(3-state). 7.6 Automatic Dead-time Reduction (ADR) Protection against cross-conduction (shoot-through) is achieved via the insertion of a delay (or dead-time) between the switching off of one MOSFET and the switching on of the other MOSFET. The automatic dead-time reduction feature continuously monitors the body diode of the lower MOSFET adjusting the dead-time to minimize body diode conduction. This reduces power loss in both the upper and lower MOSFETs due to the reduction in body diode conduction and reverse recovery charge. The lower power dissipation leads to higher system efficiency and enables higher frequency operation. 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 5 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 7.7 Over Temperature Protection (OTP) Protection against over temperature is provided by an internal thermal shutdown incorporated into the control circuit. When the control circuit die temperature exceeds the upper thermal trip level, both MOSFETs are switched off and the internal VDDG regulator disabled. This state continues until the die temperature falls below the lower trip temperature. This function is only operational when VDDC is above the UVLO level. 7.8 Am I Switching (AIS) The AIS flag is designed for use with lost phase detection circuitry. During normal operation (i.e. when PRDY and DISABLE are HIGH and VI is either HIGH or LOW), the AIS pin is pulled LOW if no voltage transients have been detected on the VO pin for a period of approximately 40 µs. If DISABLE is LOW or the driver is in 3-state mode, the AIS pin will become floating (open drain) irrespective of any previous state. False signals during start-up are prevented by activating this function approximately 200 µs after either the DISABLE pin becoming HIGH or the driver leaving the 3-state mode. 7.9 Disable This is the disable or enable function of the driver. Pulling the DISABLE pin LOW switches off both MOSFETs, disables the REG5V output, and makes the AIS flag open drain. This pin is internally pulled LOW whilst VDDC remains below the UVLO threshold. Once VDDC exceeds the UVLO threshold, this pin is pulled HIGH by an internal resistor. In this way the driver will enable itself unless there is an external pull down. In multiphase applications, connecting the DISABLE pins of multiple PIP212-12M devices together will ensure that all devices will only become enabled when the voltage on the VDDC pins of all of the devices has exceeded the UVLO threshold; see Figure 10. 7.10 Reg5V This function provides a low current regulated 5 V output voltage suitable for providing power to a PWM controller. It is operational when both PRDY and DISABLE are HIGH. Operation as a 5 V power supply is only guaranteed when VDDC is > 7 V. This pin can also be used as part of an enable function for a PWM controller; this ensures that the PWM is enabled only when the PIP212-12M is fully operational (i.e. both PRDY and DISABLE are HIGH). 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 6 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 8. Limiting values Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDDC Conditions Min Max Unit control circuit supply voltage −0.5 +15 V VDDO output stage supply voltage −0.5 +24 V VI input voltage −0.5 +12.6 V VDDG gate drive supply voltage −0.5 +12.6 V VO output voltage −0.5 VDDO + 0.5 V −0.5 VO + 15 V - 30 A - 60 A VCB bootstrap capacitor voltage IO(AV) average output current VDDC = 12 V; Tpcb ≤ 90 °C; fi = 1 MHz IORM repetitive peak output current VDDC = 12 V; tp ≤ 10 µs VPRDY power ready voltage at pin PRDY −0.5 +12.6 V VDISABLE driver enable voltage at pin DISABLE −0.5 +12.6 V VREG5V 5 V regulated supply output voltage at pin REG5V −0.5 +12.6 V VAIS output voltage at pin AIS Ptot total power dissipation [1] −0.5 +12.6 V Tpcb = 25 °C [2] - 25 W Tpcb = 90 °C [2] - 12 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C [1] Pulse width and repetition rate limited by maximum value of Tj. [2] Assumes a thermal resistance from junction to printed-circuit board of 5 K/W. 9. Thermal characteristics Table 5: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base device tested with upper and lower MOSFETs in series - 3 5 K/W 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 7 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 10. Characteristics Table 6: Characteristics VDDC = 12 V; Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 25 °C ≤ Tj ≤ 150 °C 6 12 14 V 4.1 4.2 4.4 V 3.75 3.9 4.0 V 3.3 3.5 3.7 V 1.6 V Static characteristics VDDC control circuit supply voltage Vth(UVLO) undervoltage lockout threshold voltage turn on turn off HIGH-level input voltage [1] VIL LOW-level input voltage [1] 1.4 1.5 ILI input leakage current 0 V ≤ VI ≤ 5 V - 170 IDDC control circuit supply current fi = 0 Hz, VI = 0 V - 8.2 - mA fi = 500 kHz, VDDG_EN = open - 50 - mA VIH µA fi = 500 kHz, VDDG_EN = ground - 12 - mA VDDG gate driver supply voltage IL = 65 mA 6 6.5 7 V VREG5V 5 V regulated supply output voltage at pin REG5V IL = 10 mA 4.5 5.0 5.5 V IREG5V 5 V regulated supply output current from pin REG5V VREG5V = 4.5 V - 24.0 - mA Vth(en) enable threshold voltage at pin DISABLE VDDC > 4.5 V - 3.1 - V Vth(dis) disable threshold voltage at pin DISABLE VDDC > 4.5 V - 1.6 - V Totp over temperature trip point 165 - 180 °C Totp(hys) over temperature trip hysteresis - 15 - °C Ptot total power dissipation fi = 500 kHz - 4.5 - W fi = 1 MHz - 5.8 - W - - 85 ns VDDO = 12 V; IO(AV) = 25 A; VO = 1.3 V; Tpcb = 90 °C; Dynamic characteristics td(on)(IH-OH) turn-on delay time input HIGH to output HIGH td(off)(IL-OL) turn-off delay time input LOW to output LOW - - 45 ns td(3-state) 3-state delay time - 100 - ns [1] VDDO = 12 V; IO(AV) = 12.5 A If the input voltage remains between VIH and VIL (2.5 V typ) for longer than td(3-state), then both MOSFETs are turned off. 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 8 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 003aaa833 10 Ptot (W) 003aaa834 1.3 a 8 1.2 6 1.1 4 1.0 2 0 0.9 0 10 20 IO (A) 30 0 VDDC = 12 V; VDDO = 12 V; VO = 1.3 V; fi = 1 MHz 4 8 12 16 VDDO (V) VDDC = 12 V; VO = 1.3 V; fi = 1 MHz; IO(AV) = 25 A P tot a = ---------------------------------------P tot ( V = 12 V) DDO Fig 4. Total power dissipation as a function of average output current; typical values 003aaa835 1.8 Fig 5. Normalized power dissipation as a function of output stage supply voltage; typical values 003aaa836 1.2 b c 1.6 1.0 1.4 1.2 0.8 1.0 0.8 0 2 4 VO (V) 6 0.6 200 600 800 1000 f (kHz) VDDC = 12 V; VDDO = 12 V; fi = 1 MHz; IO(AV) = 25 A VDDC = 12 V; VDDO = 1.3 V; VO = 1.3 V; IO(AV) = 25 A P tot c = -----------------------------------P tot ( f = 1 MHz ) P tot b = ----------------------------------P tot ( V = 1.3 V ) O i Fig 6. Normalized power dissipation as a function of output voltage; typical values Fig 7. Normalized power dissipation as a function of input frequency; typical values 9397 750 14586 Preliminary data sheet 400 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 9 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 003aaa837 1.3 d e 1.2 1.2 1.1 1.1 1.0 1.0 0.9 003aaa838 1.3 0.9 6 8 10 12 VDDC (V) 14 VDDO = 12 V; VO = 1.3 V; fi = 1 MHz; IO(AV) = 25 A 4 8 10 12 VDDG (V) VDDC = 12 V; VDDO = 12 V; fi = 1 MHz; IO(AV) = 25 A P tot e = -------------------------------------P tot ( V = 5 V) P tot d = ---------------------------------------P tot ( V = 12 V ) DDC DDG Fig 8. Normalized power dissipation as a function of control circuit supply voltage; typical values Fig 9. Normalized power dissipation as a function of gate drive supply voltage; typical values 9397 750 14586 Preliminary data sheet 6 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 10 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 11. Application information 11.1 Typical application conversion supply control circuit supply 22 µF (4×) 10 Ω 1 µF 1 µF VDDG VDDC REG5V 100 µF (2×) VSSO 22 µF (4×) 10 Ω 1 µF VDDG VDDC REG5V VDDO PIP212-12M CBN VI VCC 100 nF CBP 360 nH VO DISABLE VSSC 100 µF (2×) VSSO PWM 1 PWM CONTROLLER 360 nH VO DISABLE VSSC 1 µF 100 nF CBP PIP212-12M CBN VI 100 nF VDDO PWM 1 PWM 1 PWM 1 22 µF (4×) 10 Ω 1 µF 1 µF VDDG VDDC REG5V VDDO PIP212-12M CBN VI 100 µF (2×) VSSO VSSC 22 µF (4×) 10 Ω 1 µF VDDG signal ground VDDC REG5V power ground 360 nH VO DISABLE 1 µF 100 nF CBP VI VDDO PIP212-12M CBN 360 nH VO DISABLE VSSC 100 nF CBP VSSO voltage output 100 µF (2×) 03ao41 Fig 10. Typical application circuit using the PIP212-12M in a four-phase converter A typical four-phase buck converter is shown in Figure 10. This system uses four PIP212-12M devices to deliver a continuous output current of 120 A at an operating frequency of 500 kHz. 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 11 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 11.2 VDDG supply options The following options can be used for the lower MOSFET driver supply (VDDG). conversion supply control circuit supply 5 V external gate drive VDDC VDDG VDDO 100 nF CBP PWM input VI PIP212-12M CBN Lout VDDG_EN VSSC Cout VSSO signal ground output VO power ground 03ar56 Fig 11. Dual supply operation using 5 V external supply for VDDG conversion supply control circuit supply VDDC VDDG VDDO 100 nF CBP PWM input VI PIP212-12M CBN Lout open circuit VDDG_EN VSSC Cout VSSO signal ground output VO power ground 03ar57 Fig 12. Single supply operation using internal supply for VDDG conversion supply control circuit supply VDDC VDDG VDDO 100 nF CBP PWM input VI PIP212-12M VDDG_EN VSSC signal ground CBN Lout output VO Cout VSSO power ground 03ar55 Fig 13. Single supply operation using external supply for VDDG 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 12 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 12. Marking terminal 1 index area TYPE No. Design centre k = Hazel Grove, UK DIFFUSION LOT No. Diffusion centre h = Hazel Grove, UK MANUFACTURING CODE COUNTRY OF ORIGIN Assembly centre f = Anam Korea Release status code blank = Released for Supply X = Development Sample Y = Customer Qualification Sample hfkYYWWY Date code YY = last two digits of year WW = week number 03ai72 03ao89 TYPE No: PIP212-12M-NN (NN is revision number) DIFFUSION LOT No: 7 characters MANUFACTURING CODE; see Figure 15 COUNTRY OF ORIGIN: Korea Fig 14. SOT684-4 marking Fig 15. Interpretation of manufacturing code 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 13 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 13. Package outline HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm SOT684-4 B D D1 A terminal 1 index area A E1 A4 c E A1 detail X C e1 1/2 e e 15 28 L y y1 C v M C A B w M C b 29 14 e Eh1 Eh e2 1/2 e Eh2 1 terminal 1 index area 42 56 43 Dh1 Dh2 0 2.5 X 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A4 b c D D1 D h1 D h2 E E1 Eh E h1 E h2 e e1 e2 L v w y y1 mm 0.9 0.05 0.00 0.70 0.65 0.30 0.18 0.2 8.1 7.9 7.8 7.7 2.65 2.35 3.55 3.25 8.1 7.9 7.8 7.7 6.45 6.15 3.25 2.95 2.85 2.55 0.5 6.5 6.5 0.5 0.3 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT684-4 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 03-10-23 04-09-14 Fig 16. Package outline SOT684-4 (HVQFN56) 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 14 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 14. Soldering 14.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 15 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 14.5 Package related soldering information Table 7: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] Soldering method Wave Reflow [2] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable [4] suitable PLCC [5], SO, SOJ suitable suitable not recommended [5] [6] suitable SSOP, TSSOP, VSO, VSSOP not recommended [7] suitable CWQCCN..L [8], PMFP [9], WQCCN..L [8] not suitable LQFP, QFP, TQFP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 9397 750 14586 Preliminary data sheet not suitable © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 16 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 15. Mounting 15.1 PCB design guidelines The terminals on the underside of the package are rectangular in shape with a rounded edge on the inside. Electrical connection between the package and the printed-circuit board is made by printing solder paste onto the PCB footprint followed by component placement and reflow soldering. The PCB footprint shown in Figure 17 is designed to form reliable solder joints. The use of solder resist between each solder land is recommended. PCB tracks should not be routed through the corner areas shown in Figure 17. This is because there is a small, exposed remnant of the leadframe in each corner of the package, left over from the cropping process. Good surface flatness of the PCB lands is desirable to ensure accuracy of placement after soldering. Printed-circuit boards that are finished with a roller tin process tend to leave small lumps of tin in the corners of each land. Levelling with a hot air knife improves flatness. Alternatively, an electro-less silver or silver immersion process produces completely flat PCB lands. 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 17 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 9.25 (2×) 8.30 (2×) 6.20 (2×) 0.475 1.40 0.50 0.30 1.60 0.45 7.04 (4×) 0.25 0.40 0.70 (3×) 0.525 e = 0.50 0.05 0.615 0.80 (2×) 1.90 0.50 0.29 (56×) solder lands Cu pattern 0.425 0.50 2.00 0.075 7.20 (2×) 9.00 (2×) clearance 001aaa064 0.150 solder paste 0.025 placement area occupied area All dimensions in mm Fig 17. PCB footprint for SOT684-4 package (reflow soldering) 15.2 Solder paste printing The process of printing the solder paste requires care because of the fine pitch and small size of the solder lands. A stencil thickness of 0.125 mm is recommended. The stencil apertures can be made the same size as the solder lands in Figure 17. The type of solder paste recommended for MLF packages is “No clean”, Type 3, due to the difficulty of cleaning flux residues from beneath the MLF package. 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 18 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 16. Revision history Table 8: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes PIP212-12M_2 20050302 Preliminary data sheet - 9397 750 14586 PIP212-12M_1 9397 750 14464 - Modifications: PIP212-12M_1 • Data sheet status changed to Preliminary data sheet 20041223 Objective data sheet - 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 19 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 17. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20. Trademarks Intel — is a registered trademark of Intel Corporation. 19. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 14586 Preliminary data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 2 March 2005 20 of 21 PIP212-12M Philips Semiconductors DC-to-DC converter powertrain 22. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 11.1 11.2 12 13 14 14.1 14.2 14.3 14.4 14.5 15 15.1 15.2 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . 4 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . 4 Boost switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VDDG regulator . . . . . . . . . . . . . . . . . . . . . . . . . 5 3-state function . . . . . . . . . . . . . . . . . . . . . . . . . 5 Automatic Dead-time Reduction (ADR) . . . . . . 5 Over Temperature Protection (OTP) . . . . . . . . . 6 Am I Switching (AIS). . . . . . . . . . . . . . . . . . . . . 6 Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reg5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal characteristics. . . . . . . . . . . . . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . 11 Typical application. . . . . . . . . . . . . . . . . . . . . . 11 VDDG supply options . . . . . . . . . . . . . . . . . . . . 12 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . 15 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 16 Package related soldering information . . . . . . 16 Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PCB design guidelines . . . . . . . . . . . . . . . . . . 17 Solder paste printing. . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information . . . . . . . . . . . . . . . . . . . . 20 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 2 March 2005 Document number: 9397 750 14586 Published in The Netherlands