PHILIPS SAA4960

INTEGRATED CIRCUITS
DATA SHEET
SAA4960
Integrated PAL comb filter
Preliminary specification
File under Integrated Circuits, IC02
1996 Oct 15
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
FEATURES
GENERAL DESCRIPTION
• One chip adaptive PAL comb filter
The SAA4960 is an adaptive alignment-free one chip
comb filter compatible with PAL systems and provides
high performance in Y/C separation.
• Time discrete but continuous amplitude signal
processing with analog interfaces
• Internal delay lines, filters, clock processing and signal
switches
• Alignment-free
• No hanging dots or residual cross colour on vertical
transients
• Few external components.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
4.75
5
5.5
V
VDDD
digital supply voltage
4.75
5
5.5
V
VCCO
analog supply voltage output buffer
4.75
5
5.5
V
VCCPLL
analog supply voltage PLL
4.75
5
5.5
V
ICCO
analog supply current output buffer
−
70
90
mA
IDDD
digital supply current
−
10
20
mA
ICCA
analog supply current
−
35
40
mA
ICCPLL
analog supply current PLL
−
1.5
3.0
mA
V17(p-p)
CVBS and Y input signal (peak-to-peak value)
0.7
1
1.4
V
V10(p-p)
chrominance input signal (peak-to-peak value)
−
0.7
1
V
V1(p-p)
subcarrier input signal (peak-to-peak value)
100
200
400
mV
V14(p-p)
luminance output signal (peak-to-peak value)
0.6
1
1.54
V
V12(p-p)
chrominance output signal (peak-to-peak value)
−
0.7
1.1
V
V15(p-p)
CVBS and Y output signal (peak-to-peak value)
0.6
1
1.54
V
ORDERING INFORMATION
TYPE
NUMBER
SAA4960
1996 Oct 15
PACKAGE
NAME
DIP28
DESCRIPTION
plastic dual in-line package; 28 leads (600 mil)
2
VERSION
SOT117-1
1996 Oct 15
FSC 1
CSY 19
3
Cext 10
n.c. 20
n.c. 23
LPFION 18
+5 V
CLAMP
BIAS
CONT2
LPFI
SYNC
SEPARATOR
CLOCK
CONTROL
S1
VDET
HDET
STOPS
CL3
SYSPAL
A
11
OGND
CL3
16
i.c.
CL3
i.c.
2
COMB
FILTER
CL3
8
CL3
D
28
i.c.
−1
21
22
VDDD
+5 V
CONT1
LPFO2
CONT1
LPFO1
CONT1
LPFO1
CCOMB
YCOMB
5
REFBP
A
24
STOPS
SAA4960
S2C
S2B
S2A
100 nF
MHA366
12
CO
14 YO
15 CVBSO
REFDL
VOLTAGE
REFERENCE
CVBSDL
47 Ω
A
100 nF
CURRENT
REFERENCE
100 nF
100 µF
DGND
CL3
CONT2
CONT1
VCCO
+5 V
BPF
100 nF
100 µF
LPF
CONTROL
A
DELAY
COMPENSATION
4
CL3
BPF
CL3
BPF
CL3
BPF
LPFO1
7
VCCA
+5 V
i.c.
9
AGND
100 nF
100 µF
Fig.1 Block diagram.
HSEL CL3
SYSPAL
DELAY
LINES
27
26
HSEL
VCCPLL
PLLGND
+5 V
Integrated PAL comb filter
Remark: all switches in LOW position.
100 nF
100 nF
Yext/CVBS 17
100 nF
A
COMBENA 25
FSCSW 13
SSYN 6
BYP 3
A
100 nF
100 µF
handbook, full pagewidth
HDET VDET
D
A
Philips Semiconductors
Preliminary specification
SAA4960
BLOCK DIAGRAM
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
PINNING
SYMBOL
PIN
DESCRIPTION
FSC
1
subcarrier frequency input
i.c.
2
internally connected
BYP
3
bypass mode forcing input
i.c.
4
internally connected
5
decoupling capacitor for band-pass
filter reference
SSYN
6
bypass definition input
FSC
1
28 i.c.
VCCA
7
analog supply voltage
i.c.
2
27 VCCPLL
VCCO
8
analog supply voltage output buffer
BYP
3
26 PLLGND
AGND
9
analog ground (signal reference)
i.c.
4
25 COMBENA
Cext
10
external chrominance input signal
REFBP
5
24 REFDL
OGND
11
analog ground output buffer
CO
12
chrominance output signal
SSYN
6
23 n.c.
FSCSW
13
fsc reference selection input
VCCA
7
YO
14
luminance output signal
VCCO
8
21 DGND
CVBSO
15
uncombed CVBS output signal
AGND
9
20 n.c.
i.c.
16
internally connected
REFBP
Yext/CVBS
17
CVBS (VBS) input signal
LPFION
18
disable alias-filter
CSY
19
storage capacitor
n.c.
20
not connected
DGND
21
digital ground
VDDD
22
digital supply voltage
n.c.
23
not connected
REFDL
24
decoupling capacitor for delay lines
COMBENA
25
COMB-mode output signal
PLLGND
26
analog ground PLL
VCCPLL
27
analog supply voltage PLL
i.c.
28
internally connected
1996 Oct 15
handbook, halfpage
22 VDDD
SAA4960
Cext 10
19 CSY
18 LPFION
OGND 11
CO 12
17 Yext/CVBS
FSCSW 13
16 i.c.
YO 14
15 CVBSO
MHA365
Fig.2 Pin configuration.
4
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
FUNCTIONAL DESCRIPTION
Pin description
Functional requirements
FSC (PIN 1)
The PAL comb filter processes the video standards PAL B,
G and H. PAL D and I signals can also be processed but
with the drawback of a slightly reduced bandwidth.
Input for the reference frequency fsc (see note 2 of Chapter
“Characteristics”) or 2 × fsc. For SECAM standard signals
the best signal performance in BYPASS-mode is achieved
by switching the FSC input signal off externally.
For SECAM and SVHS signals, the input signals can be
bypassed to the output without processing by selecting the
BYPASS-mode.
BYP (PIN 3)
Input signal that controls the operation mode. A low-pass
filter is added to the input for suppression of subcarrier
frequencies. Thus applications are supported where the
operation mode (COMB or BYPASS) is controlled by the
DC-level of the FSC input signal at pin 1. For those
applications the BYP input can be externally connected to
FSC (pin 1).
A sync separation circuit is incorporated to generate
control signals for the internal clock processing. With a
sync compression of up to 12 dB the sync separator works
properly (see Fig.4).
The IC is controlled via four pins:
1. BYP forces the IC into the BYPASS-mode (comb filter
function off)
Depending on SSYN (pin 6) the function of BYP can be
adapted to a certain application with respect to the polarity
of the logic level and with respect to the behaviour when
entering the COMB-mode.
2. SSYN defines whether the COMB-mode is entered
synchronously or not and defines the polarity of the
BYP pin
3. FSCSW selects the reference frequency fsc or 2 × fsc
Dependent on SSYN the BYP input can be either inverted
or non-inverted with the function as shown in Table 2:
4. LPFION enables the internal pre-filter.
It is possible to select the following modes of operation:
Table 2
COMB-mode: Luminance and chrominance comb filter
function active if BYPASS-mode not active.
SSYN
BYPASS-mode: Signal processing not active, all clocks
inactive, Cext (pin 10) is bypassed to CO (pin 12) and
Yext/CVBS (pin 17) is bypassed to YO (pin 14) and
CVBSO (pin 15). This mode is forced via BYP (pin 3).
If the stimulus of the mode is changed, the IC is following
the new mode after the stabilization time given in Table 1.
Table 1
BYP
SELECTED MODE
LOW
LOW
COMB-mode
LOW
HIGH
BYPASS-mode
HIGH
LOW
BYPASS-mode
HIGH
HIGH
COMB-mode
Dependent on SSYN the behaviour when entering the
COMB-mode is different for the both selectable logic
polarities while the BYPASS-mode is always entered
asynchronously (immediately).
Stabilization time after mode change
MODE CHANGE
Bypass function
MAXIMUM
STABILIZATION
TIME
Table 3
Behaviour when entering the COMB-mode
COMB-mode to BYPASS-mode
1 line
SSYN
BYPASS-mode to COMB-mode
1 field
LOW
immediately if BYP = LOW
HIGH
synchronized by vertical pulse if BYP = HIGH
The mode change from BYPASS to COMB depends on
SSYN (pin 6) and can be asynchronous or synchronous
related to the vertical pulse. The mode change from
COMB to BYPASS is always performed asynchronously.
1996 Oct 15
ENTERING COMB-MODE
The PLL and the clock processing are always stopped if
the selected level for BYPASS is applied to BYP
(independent of the vertical pulse).
5
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
REFBP (PIN 5)
Table 6
Decoupling capacitor for the band-pass filter reference
voltage.
YO output signal
YO OUTPUT SIGNAL
MODE
SSYN (PIN 6)
COMB
comb filtered luminance signal
BYPASS
external CVBS signal of Yext/CVBS input
Input signal that controls the function of BYP (pin 3).
CVBSO (PIN 15)
VCCA, VCCO, VDDD AND VCCPLL (PINS 7, 8, 22 AND 27)
CVBS output signal directly from the input in
BYPASS-mode or delayed by the signal processing time
of 2 lines and an additional processing delay.
Supply voltages.
AGND, OGND, DGND AND PLLGND (PINS 9, 11,
21 AND 26)
Table 7
CVBSO output signal
MODE
Ground connection. AGND is used as signal reference for
all analog input and output signals.
CVBSO OUTPUT SIGNAL
COMB
delay compensated CVBS signal
BYPASS
external CVBS signal of Yext/CVBS input
Cext (PIN 10)
Yext/CVBS (PIN 17)
Input for an external chrominance signal which is
correlated to the external VBS signal.
Input for the CVBS signal or for an external VBS signal.
CO (PIN 12)
LPFION (PIN 18)
Chrominance output signal. This output can be switched
between the comb filtered chrominance from the CVBS
signal and the external chrominance signal from the input
Cext if the IC is forced into BYPASS-mode.
Input signal to disable the internal pre-filter LPFI.
Table 4
Table 8
LPFION
CO output signal
MODE
CO OUTPUT SIGNAL
COMB
comb filtered chrominance signal
BYPASS
external chrominance signal of Cext input
Pre-filter mode
SELECTED MODE
LOW
LPFI inactive
HIGH
LPFI active
Floating
LPFI active
CSY (PIN 19)
FSCSW (PIN 13)
Sync top capacitor for the sync separator.
Input signal to select between fsc or 2 × fsc as reference at
the FSC input pin.
REFDL (PIN 24)
Table 5
Decoupling capacitor for the delay line reference voltage.
Reference frequency selection
FSCSW
COMBENA (PIN 25)
SELECTED REFERENCE
HIGH
2 × fsc
LOW
fsc
Output signal that indicates the current mode of operation.
This output is forced to LOW if the comb filter is in
BYPASS-mode.
Table 9
YO (PIN 14)
COMBENA
VBS output signal. This output can be switched between
the comb filtered luminance signal (including
synchronization) and the external (C)VBS signal from the
input Yext/CVBS. In COMB-mode the output signal is
delayed by 2 lines and by an additional processing delay.
1996 Oct 15
Mode of operation
6
SELECTED MODE
LOW
BYPASS-mode; PLL and clock processing
stopped
HIGH
COMB-mode
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
Internal functional description
LPF CONTROL
SWITCHED CAPACITOR DELAY LINE
Automatic tuning of the low-pass filters is achieved by
adjusting the filter delays. The control information for all
filters (CONT1 and CONT2) is derived from a built-in
reference filter (LPFO1-type) that is part of a control loop.
The control loop tunes the reference filter delay and thus
all other filter delays to a time constant derived from the
system clock CL3.
Delays the CVBS input signal by 2 lines and 4 lines. Input
signals for the delay lines are the CVBS signal, the clock
CL3 (3 × fsc), the control signal HSEL and the standard
selection signal SYSPAL.
Output signals are the non-delayed, the 2-line delayed and
the 4-line delayed CVBS signal.
CONTROL AND CLOCK PROCESSING (CLOCK CONTROL)
SWITCHED CAPACITOR BAND-PASS FILTERS (BPF)
The control and clock processing block (see Fig.7)
consists of the sub-blocks PLL, the clock processing and
the mode control. The PLL and the clock processing are
released for operation if the input level at BYP selects the
COMB-mode.
The comb filter input BPFs attenuate the low frequencies
to guarantee a correct signal processing within the logical
comb filter.
The comb filter output BPF reduces the alias components
that are the result of the non-linear signal processing within
the logical comb filter.
Main tasks of the control and clock processing are:
• Clock generation of system clock CL3
• Delay line start control
LOGICAL COMB FILTER
• Mode control.
Separates the chrominance from the band-pass filtered
CVBS signal.
The signal processing is based on a 3 × fsc system clock
(CL3), that is generated by the clock processing from the
fsc signal at FSC (pin 1) via a PLL. Because the subcarrier
frequency divided by the line frequency results not in an
integer value a clock phase correction of 180° is necessary
every second line for PAL standards. The clock phase
correction is controlled by the input signals horizontal
sync. Additionally the delay line start is synchronized once
a field to the input signals horizontal sync. The 25 Hz PAL
offset is corrected in this way.
COMPENSATION DELAY
Compensates the internal processing time of the
band-pass filters and the logical comb filter section.
ADDER
The comb filtered luminance output signal is obtained by
adding the delayed CVBS signal and the inverted comb
filtered chrominance signal.
The PLL provides a master clock MCK of 6 × fsc, which is
locked to the subcarrier frequency at FSC (pin 1).
LOW-PASS FILTER INPUT (LPFI)
The system clock CL3 (3 × fsc) is obtained from MCK by a
divide-by-two circuit. The 180° phase shift is generated by
stopping the divide-by-two circuit for one MCK clock cycle.
Analog input low-pass filter to reduce the outband
frequencies of EMC. The input low-pass filter is included in
the signal path but it can be switched off via the input
signal LPFION.
The generated clock is a pseudo-line-locked clock that is
referenced to fsc. The sync separator generates the
necessary signals HDET and VDET indicating the line (H)
and the field (V) sync periods.
LOW-PASS FILTER OUTPUT (LPFO1 AND LPFO2)
Two different types of output low-pass filters (LPFO1 and
LPFO2) are necessary to get equal signal delays within the
luminance path and the chrominance path (important for
good transient behaviour). The low-pass output filter type
LPFO1 is used for the luminance output while LPFO2 is
used for the chrominance output. The filters are analog 3rd
order elliptic low-pass filters that convert the output signals
from the time discrete to the time continuous domain
(reconstruction filter).
1996 Oct 15
The current mode of operation (BYPASS or COMB) is
external readable via COMBENA (pin 25).
7
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
The input signals of the control and clock processing
(CLOCK CONTROL) are:
Table 11 Function of signal switch S1
LPFION-STATE
HDET: analog horizontal pulse from sync separator
DELAY LINE INPUT
LOW
FSC: subcarrier frequency (fsc or 2 × fsc)
non-pre-filtered input signal
Yext/CVBS
HIGH
pre-filtered input signal Yext/CVBS
FSCSW: reference frequency selection
Floating
pre-filtered input signal Yext/CVBS
VDET: analog vertical pulse from sync separator
BYP: BYPASS control signal
SIGNAL SWITCH S2A
SSYN: vertical synchronous mode selection for BYP
and polarity selection of BYP.
For the CVBSO output two signals can be selected via the
signal switch S2A.
The output signals are:
CL3: system clock (3 × fsc)
Table 12 CVBSO output signal
HSEL’s: line start signals for the delay lines
STOPS: forces the comb filter via the switches S2A,
S2B and S2C into the BYPASS-mode (always
asynchronous) or COMB-mode (synchronous or
asynchronous with VINT; depending on SSYN)
STOPS-STATE
CVBSO OUTPUT
SIGNAL
MODE
LOW
delayed input CVBSDL
COMB
HIGH
non-delayed input
Yext/CVBS
BYPASS
COMBENA: HIGH during COMB-mode; otherwise
LOW.
SIGNAL SWITCHES S2B AND S2C
Table 10 Function of STOPS signal
STOPS-STATE
Two switches are included to bypass the comb filter signal
processing. The input video signal Cext for the switch S2C
is internally biased.
SELECTED MODE
LOW
COMB
HIGH
BYPASS
For the YO output two signals can be selected via S2B.
Table 13 YO output signal
HORIZONTAL AND VERTICAL SYNC SEPARATOR
STOPS-STATE
A build-in sync separator circuit generates the HDET and
VDET signals from the Yext/CVBS input signal. This circuit
is still working properly at input signals with a 12 dB
attenuated sync in a normal 700 mV black-to-white video
signal (see Fig.4).
MODE
LOW
YCOMB
(combed luminance)
COMB
HIGH
input Yext/CVBS
BYPASS
For the CO output two signals can be selected via S2C.
CLAMP
The black level clamping of the video input signal is
performed by the sync separator stage. The clamping level
is nearly adequate to the voltage at REFDL (pin 24).
Table 14 CO output signal
STOPS-STATE
SIGNAL SWITCH S1
The switch is included to bypass the low-pass input filter.
For the CVBS input of the delay line block two signals can
be selected via the slow signal switch S1.
1996 Oct 15
YO OUTPUT SIGNAL
8
CO OUTPUT SIGNAL
MODE
LOW
CCOMB
(combed chrominance)
COMB
HIGH
input Cext
BYPASS
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−
6.5
−0.3
VCC + 0.3 V
−
155
mA
−
±15
mA
−
10
mA
−
900
mW
operating ambient temperature
0
70
°C
storage temperature
−25
+150
°C
VCC
supply voltage
V
input voltage protection threshold
ICC
total supply current
IO
output current (CO, YO and CVBSO)
output current (COMBENA)
Ptot
total power dissipation
Tamb
Tstg
Ves
electrostatic handling
except pin 1
V
note 1
Note
1. Human Body Model: C = 100 pF; R = 1.5 kΩ; V = 2 kV; charge device model: C = 200 pF; R = 0 Ω; V = 300 V.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1996 Oct 15
PARAMETER
thermal resistance from junction to ambient in free air
9
VALUE
UNIT
31
K/W
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
CHARACTERISTICS
VDDD = VCCA = VCCO = VCCPLL = 5 V; Tamb = 25 °C; input signal Yext/CVBS = 1 V (p-p) (0 dB); input signal
C = 0.7 V (p-p) (0 dB); input signal FSC = 200 mV (p-p), sine wave, DC level = 2 V; input signal LPFION = 5 V; test
signal: EBU colour bar 100/0/75/0 “CCIR471-1”; source impedance for Yext/CVBS, Cext = 75 Ω decoupled with 100 nF;
source impedance for FSC = 75 Ω; load impedance for CVBSO, YO, CO = 1 kΩ and 20 pF in parallel; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply voltage
VCCA
analog supply voltage (pin 7)
note 1
4.75
5
5.5
V
VCCO
analog supply voltage output buffer
(pin 8)
note 1
4.75
5
5.5
V
VDDD
digital supply voltage (pin 22)
note 1
4.75
5
5.5
V
VCCPLL
analog supply voltage PLL (pin 27)
note 1
4.75
5
5.5
V
100
200
400
mV
sine wave
−
−
−
−
square wave
0.4
0.5
0.6
duty
cycle
FSC (pin 1)
V1(p-p)
input AC voltage (peak-to-peak value)
input AC voltage is valid for
V1
input DC level
0
−
5.3
V
C1
input capacitance
−
−
10
pF
Ileak
input leakage current
−
−
10
µA
Z1
source impedance
−
−
800
Ω
VIH
HIGH level input voltage
2.4
−
VCC
V
VIL
LOW level input voltage
0
0.85
1.5
V
Ileak
input leakage current
−
−
10
µA
C3
input capacitance
−
−
10
pF
DC voltage
1.1
1.25
1.4
V
VIH
HIGH level input voltage
2.4
−
VCC
V
VIL
LOW level input voltage
0
0.85
1.5
V
Ileak
input leakage current
−
−
10
µA
C6
input capacitance
−
−
10
pF
analog supply current
−
35
40
mA
supply current
−
70
90
mA
BYP (pin 3)
REFBP (pin 5)
V5
SSYN (pin 6)
VCCA (pin 7)
ICCA
VCCO (pin 8)
ICCO
1996 Oct 15
10
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SYMBOL
SAA4960
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Cext (pin 10)
−
V10
input voltage (AC coupled)
R10
input resistance
500
700
1000
kΩ
C10
input capacitance
−
−
10
pF
Z10
source impedance
−
−
1
kΩ
−1
0
+1
dB
1.25 V
0
3
dB
CO (pin 12)
V10/V12
BYPASS-mode: CO/Cext
fsc ±0.3fsc; note 2
COMB-mode: transfer function C-path see Fig.8
V12
DC offset voltage related to input
−400
0
+400
mV
∆V12
DC jump when forcing into
BYPASS-mode
−
100
450
mV
R12
output resistance
−
10
100
Ω
RL
load resistance (to ground)
0.3
−
−
kΩ
CL
load capacitance (to ground)
−
−
25
pF
V17/V12
suppression (comb depth)
283 × fH
26
30
−
dB
(283 − 43) × fH
20
24
−
dB
(283 + 35) × fH
20
24
−
dB
0.75fsc
−
−
−30
dB
fsc
−
−
−50
dB
1.5fsc
−
−
−37
dB
2fsc
−
−
−30
dB
FPN
fixed pattern noise for divided clock
frequencies referenced to 0.7 V (p-p)
see Fig.5 and
note 3
αcr
crosstalk suppression at vertical
transients no-colour ↔ colour
see Fig.3
26
30
−
dB
S/N
signal-to-noise ratio (0.7 V/Veff noise)
unweighted;
fsc ±0.3fsc; note 2
56
72
−
dB
αcr
crosstalk between different inputs
0 to 5 MHz
−
−60
−40
dB
V12(p-p)
FSC residue in BYPASS-mode related
to 700 mV (p-p)
−
−
−60
dB
Gd
differential gain
0.95
−
−
FSCSW (pin 13)
VIH
HIGH level input voltage
2
−
VCC
V
VIL
LOW level input voltage
0
−
0.8
V
C13
input capacitance
−
−
10
pF
Ileak
input leakage current
−
−
10
µA
1996 Oct 15
11
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SYMBOL
SAA4960
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
YO (pin 14)
V14/V17
BYPASS-mode: CO/Cext
0 to 5 MHz
−1
0
+1
dB
COMB-mode: transfer function Y-path see Fig.9
V14
DC offset voltage related to input
−400
0
+400
mV
∆V14
DC jump when forcing into
BYPASS-mode
−
200
450
mV
R14
output resistance
−
10
100
Ω
RL
load resistance (to ground)
0.3
−
−
kΩ
CL
load capacitance (to ground)
−
−
25
pF
V17/V14
suppression (comb depth)
26
30
−
dB
(283.75 − 43) × fH 10
12
−
dB
see Fig.6 and
note 3
283.75 × fH
24
−
dB
0.75fsc
−
−
−40
dB
fsc
−
−
−30
dB
1.5fsc
−
−
−30
dB
2fsc
−
−
−20
dB
(283.75 + 35) × fH 18
FPN
fixed pattern noise for divided clock
frequencies referenced to 0.7 V (p-p)
black-to-white
αcr
crosstalk suppression at vertical
transients gray ↔ multi-burst
see Fig.3
26
30
−
dB
S/N
signal-to-noise ratio (0.7 V/Veff noise)
unweighted;
200 kHz to 5 MHz
56
72
−
dB
αcr
crosstalk between different inputs
0 to 5 MHz
−
−60
−40
dB
V14(p-p)
FSC residue in BYPASS-mode related
to 700 mV (p-p)
−
−
−60
dB
Gd
differential gain
0.95
−
−
−1
0
+1
dB
CVBSO (pin 15)
V15/V17
BYPASS-mode: CVBSO/CVBS
0 to 5 MHz
COMB-mode: transfer function CVBS-path see Fig.9
V15
DC offset voltage
−400
0
+400
mV
∆V15
DC jump when forcing into
BYPASS-mode
−
200
450
mV
R15
output resistance
−
10
100
Ω
RL
load resistance (to ground)
0.3
−
−
kΩ
CL
load capacitance (to ground)
−
−
25
pF
FPN
fixed pattern noise for divided clock
frequencies referenced to 0.7 V (p-p)
black-to-white
S/N
1996 Oct 15
signal-to-noise ratio (0.7 V/Veff noise)
0.75fsc
−
−
−40
dB
fsc
−
−
−30
dB
1.5fsc
−
−
−30
dB
2fsc
−
−
−20
dB
unweighted;
200 kHz to 5 MHz
56
72
−
dB
12
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SYMBOL
PARAMETER
αcr
crosstalk between different inputs
V15(p-p)
SAA4960
CONDITIONS
MIN.
TYP.
MAX.
UNIT
−
−60
−40
dB
FSC residue in BYPASS-mode related
to 700 mV (p-p)
−
−
−60
dB
Gd
differential gain
0.95
−
−
Pd
differential phase
−
2
3
deg
−3
0
+3
dB
0 to 5 MHz
Yext/CVBS (pin 17)
V17
input voltage (AC coupled)
12 dB sync
attenuation
possible; see Fig.4
I17
input current during sync pulse
−10
−8.0
−
µA
input current during active video
−
0.84
1.5
µA
V17
DC voltage during black level
1.1
1.25
1.4
V
Z17
source impedance
−
−
1
kΩ
LPFION (pin 18)
VIH
HIGH level input voltage
2
−
VCC
V
VIL
LOW level input voltage
0
−
0.8
V
I18
input current
−
8
20
µA
−
8
20
µA
C18
input capacitance
−
−
10
pF
DC voltage
0
2.45
VCC
V
supply current
−
10
20
mA
1.1
1.25
1.4
V
0.26
0.4
0.55
V
4
−
VCC
V
−55
−24
−
µA
−
1.5
3
mA
0.8 V
2.0 V
CSY (pin 19)
V19
VDDD (pin 22)
IDDD
REFDL (pin 24)
V24
DC voltage
COMBENA (pin 25)
VOL
LOW level output voltage
VOH
HIGH level output voltage
IOH
HIGH level output current
3 mA
2.4 V
VCCPLL (pin 27)
I27
supply current
Notes to the characteristics
1.
∆V = V CCA – V DDD ≤ 300 mV
∆V = V CCA – V CCPLL ≤ 300 mV
∆V = V CCA – V CCO ≤ 300 mV
∆V = V CCO – V CCPLL ≤ 300 mV
∆V = V CCO – V DDD ≤ 300 mV
∆V = V DDD – V CCPLL ≤ 300 mV
All voltages are related to AGND.
2. Subcarrier frequency fsc = 4.43361875 MHz.
3. Line frequency fH = 15.625 kHz.
1996 Oct 15
13
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
handbook, full pagewidthinput
line 1
line 2
line 3
line 4
line 5
line 6
line 7
line 8
output
vertical transient
MHA367
Fig.3 Vertical transmission by different video signals from line to line.
handbook, full pagewidth
1.0
(V)
0.45
0.3
0.225
0.15
0
MHA370
Fig.4 EBU colour bar 100/0/75/0 with 12 dB sync attenuation.
1996 Oct 15
14
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
handbook, full pagewidth
U, V: PAL B, G, H, D, I
fsc
U
V
Y
(n − 1)fH
Y
(n − 0.75)fH
(n − 0.25)fH
MHA368
nfH
Fig.5 Principle frequency response of a comb filtered PAL chrominance signal.
handbook, full pagewidth
U, V: PAL B, G, H, D, I
fsc
Y
(n − 1)fH
Y
V
U
(n − 0.75)fH
(n − 0.25)fH
nfH
Fig.6 Principle frequency response of a comb filtered PAL luminance signal.
1996 Oct 15
15
MHA369
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
handbook, full pagewidth
SAA4960
1
1
SSYN
&
VINT
1
&
=1
COMBENA
BYP
STOPS
1
CL3
CL3
HDET
4
CLOCK
PROCESSING
VINT
VDET
FSC
PLL
HSEL
MCK
FSCSW
STOP
Fig.7 Clock control.
1996 Oct 15
16
MHA371
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
gain
handbook, full pagewidth
(dB)
+1
0
−1
−3
−25
−30
0.4
0.66
0.85 1 1.12 1.35
2.0
2.26
2.7
frequency (fsc)
MHA372
Fig.8 Chrominance path: tolerance band with anti-alias filter.
gain
handbook, full pagewidth
(dB)
+1
0
−1
−2
−3
−5
−32
0.7
1
1.12
1.5
2.26
2.7
frequency (fsc)
MHA373
Fig.9 Luminance and CVBSO path: tolerance band with anti-alias filter.
1996 Oct 15
17
1996 Oct 15
18
SVHS
1
2
3
4
10 kΩ
10 kΩ
SVHS-Y
VDDD
SVHS-C
75 Ω
100 nF
VCCO
VCCA
100 nF
47 Ω
75 Ω
YO
FSCSW
CO
OGND
Cext
AGND
VCCO
VCCA
SSYN
REFBP
i.c.
BYP
i.c.
FSC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
17
18
19
20
21
100
nF
CVBSO
i.c.
VDDD
10 kΩ
100
µF
75 Ω
VCCA
VCCO
VDDD
VCCPLL
CVBS
100 nF
COMBENA
VCCPLL
100 nF
Yext/CVBS
LPFION
CSY
n.c.
DGND
VDDD
n.c.
REFDL
COMBENA
PLLGND
VCCPLL
i.c.
10
nF
10
nF
10
nF
10
nF
100
nF
100
nF
100
nF
100
nF
2
2
2
100
µF
MHA374
2
VCCPLLS
33 µH 1
100
µF
VCCAS
33 µH 1
100
µF
VCCOS
33 µH 1
100
µF
VDDDS
33 µH 1
Integrated PAL comb filter
Fig.10 Test circuit.
SAA4960
22
23
24
25
26
27
28
handbook, full pagewidth
Cext
FSC
Philips Semiconductors
Preliminary specification
SAA4960
TEST AND APPLICATION INFORMATION
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
5.6 kΩ
handbook, full pagewidth
COMBENA BYP
25
3
FSC
1
Cext
10
SVHS-C
12
SAA4960
14
SVHS-VBS
TDA8540
CVBS1
Yext/CVBS
SWITCH
17
15
6
−(R − Y)
TDA9141
MSD
YO
−(B − Y)
COMB FILTER
CVBS2
TDA4665
BBDL
CVBSO
VB
13
SSYN
I2C-bus
CO
FSCSW
CVBSO
+5 V
I2C-bus
MHA375
Fig.11 Application diagram: SAA4960 with TDA9141.
+5 V
handbook, full pagewidth
I2C-bus
3.3 kΩ
PCF8574
1 kΩ
I2C-I/O PORT
BC548
4.43 MHZ
FSC
COMBENA BYP
25
3
1
Cext
10
SVHS-C
12
SAA4960
14
SVHS-VBS
TDA8540
CVBS1
SWITCH
CVBS2
Yext/CVBS
COMB FILTER
17
TDA9160/62
MSD
TDA4665
BBDL
−(R − Y)
−(B − Y)
VB
TXT
13
SSYN
I2C-bus
YO
CVBSO
15
6
CO
FSCSW
I2C-bus
+5 V
MHA376
Fig.12 Application diagram: SAA4960 with TDA9160/62.
1996 Oct 15
19
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
handbook, full pagewidth
I2C-bus
PCF8574
I2C-I/O PORT
IF input
FSC
BYP
3
1
Cext
10
SVHS-C
12
SAA4960
14
SVHS-VBS
TDA8540
Yext/CVBS
CVBS1
SWITCH
CO
YO
COMB FILTER
17
CVBSint
15
6
CVBSO
R
TDA8366
MSD
G
TDA4665
BBDL
B
13
SSYN
FSCSW
CVBSO
I2C-bus
I2C-bus
MHA377
Fig.13 Application diagram: SAA4960 with TDA8366.
handbook, full pagewidth
I2C-bus
PCF8574
I2C-I/O PORT
2 × FSC
BYP
3
FSC
Cext
10
SVHS-C
CHROMINANCE
BANDPASS
1
12
CO
TDA4665
BBDL
SAA4960
CVBS1
SWITCH
CVBS2
Yext/
COMB FILTER
CVBS
17
14
6
15
13
SSYN
I2C-bus
YO
CVBSO
−(B − Y)
VBS
CVBSO
FSCSW
MHA378
+5 V
Remark: all switches in LOW position.
Fig.14 Application diagram: SAA4960 with TDA4655.
1996 Oct 15
−(R − Y)
LUMINANCE
TRAP
SVHS-VBS
TDA8540
TDA4655
MSD
20
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
PACKAGE OUTLINE
seating plane
handbook, full
pagewidthdual in-line package; 28 leads (600 mil)
DIP28:
plastic
SOT117-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
15
28
pin 1 index
E
1
14
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
5.1
0.51
4.0
1.7
1.3
0.53
0.38
0.32
0.23
36.0
35.0
14.1
13.7
2.54
15.24
3.9
3.4
15.80
15.24
17.15
15.90
0.25
1.7
inches
0.20
0.020
0.16
0.066
0.051
0.020
0.014
0.013
0.009
1.41
1.34
0.56
0.54
0.10
0.60
0.15
0.13
0.62
0.60
0.68
0.63
0.01
0.067
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT117-1
051G05
MO-015AH
1996 Oct 15
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-01-14
21
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Oct 15
22
Philips Semiconductors
Preliminary specification
Integrated PAL comb filter
SAA4960
NOTES
1996 Oct 15
23
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/01/pp24
Date of release: 1996 Oct 15
Document order number:
9397 750 01366