PHILIPS TDA9847

INTEGRATED CIRCUITS
DATA SHEET
TDA9847
TV and VTR stereo/dual sound
processor with digital identification
Preliminary specification
Supersedes data of September 1993
File under Integrated Circuits, IC02
1995 May 23
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
FEATURES
GENERAL DESCRIPTION
• Supply voltage 5 to 8 V
The TDA9847 is a stereo/dual sound processor for TV and
VTR sets. Its identification ensures safe operation by using
internal digital PLL technique with extremely small
bandwidth, synchronous detection and digital integration
(switching time maximum 2.0 s; identification concerning
the main functions).
• Source selector
• Stereo matrix
• AF inputs for external stereo AF signals
(SCART or NICAM)
• AF outputs for main and SCART
• LED operation mode indication (stereo and dual)
• High identification reliability.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
VP
supply voltage (pin 22)
IP
supply current (pin 22)
without LED current
Vi(rms)
nominal input signal voltage
Vi1 to Vi4 (RMS value)
54% modulation
Vo(rms)
nominal output signal voltage
(RMS value)
54% modulation
Vo(rms)
clipping level of the output signal
voltages (RMS value)
THD ≤ 1.5%; B/G or L
MIN.
TYP.
MAX.
UNIT
4.5
5
8.8
V
14
15
20
mA
B/G
−
250
−
mV
L
−
500
−
mV
−
500
−
mV
VP = 5 V
1.4
1.60
−
V
VP = 8 V
2.4
2.65
−
V
ILon
input current
LED on
−
−
12
mA
Vi pil
input voltage sensitivity of pilot
frequency
unmodulated
5
−
100
mV
S/N(W)
weighted signal-to-noise ratio
“CCIR468-3”
66
75
−
dB
THD
total harmonic distortion
−
0.2
0.3
%
Tamb
operating ambient temperature
fident
identification window width
0
−
+70
°C
stereo
2.2
−
2.2
Hz
dual
2.3
−
2.3
Hz
tident on
total identification time on
0.35
−
2.0
s
Vi tuner
identification voltage sensitivity
−
28
−
dBµV
∆fpil
pull-in frequency range of pilot PLL
fosc = 10.008 MHz
lower side
−296
−
−296
Hz
upper side
302
−
302
Hz
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
TDA9847
SDIP24
TDA9847T
1995 May 23
SO24
DESCRIPTION
VERSION
plastic shrink dual in-line package; 24 leads (400 mil)
SOT234-1
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
2
2.2 µF
Vi1
3 dB
9
3 dB
6 dB
6 dB
A/mono
10 kΩ
6 dB
13
500 mV RMS
16
Vo3
15
Vo4
SCART
R/B
250 mV RMS
0 dB
2.2 µF
500 mV RMS
Vo2
L/A/mono
250 mV RMS
L
Vref
50 kΩ
Vo1
main
AM
250 mV RMS
10 kΩ
14
500 mV RMS
50 kΩ
5 kΩ
35 kΩ
10
2.2 µF
11
50 kΩ
Vref
0 dB
Vref
R, B
12
Vref
3 dB
250 mV RMS
(AM: 500 mV RMS)
Vi2
21
15 kΩ
2.2 kΩ
L+R
,A
2
2.2 µF
5 kΩ
6 dB
250 mV RMS
500 mV RMS
TDA9847
3
RFP
CFP
mute
DIGITAL PLL
AND
DEMODULATOR
47 pF
7
3.3 nF
tan δ ≤ 0.002
CDCL
stereo transmission
30 kΩ
dual bit
DIGITAL
INTEGRATOR
(274 Hz)
Qo= 70
DIGITAL
PLL
2.5 mH
6
Vref
Vref
100 nF
4
1 kΩ
stereo
bit
DIGITAL PLL
AND
DEMODULATOR
dual transmission
25 kΩ
1
25 kΩ
Vref
10 µF
SUPPLY
POWER-ON
RESET
VP
18
DIGITAL
INTEGRATOR (117 Hz)
OSCILLATOR
CAGC
19
Philips Semiconductors
2.2 kΩ
250 mV RMS
10 nF
±5%
17
6 dB (AM)
SCART
Vi4 Vi3
TV and VTR stereo/dual sound processor
with digital identification
CD2
10 nF
±5%
BLOCK DIAGRAMS
1995 May 23
CD1
250 mV
RMS
CONTROL
LOGIC
2
24
3
C1
C2
C3
C4
5
CLP
23
10 nF
8
22
20
1/2 VP
100 µF/
16 V
VP
Fig.1 Block diagram of the bipolar TV/VTR-stereo decoder.
TDA9847
Input and output levels are nominal values related to the SCART norm (AM: m = 0.54, FM: ∆f = ±27 kHz).
Preliminary specification
10 MHz
MED803
Cref
17
6 dB (AM)
2.2 kΩ
2.2 µF
Vi1
3 dB
9
3 dB
6 dB
10 kΩ
6 dB
500 mV RMS
13
Vo2
500 mV RMS
16
Vo3
15
Vo4
SCART
R/B
250 mV RMS
0 dB
2.2 µF
Vo1
L/A/mono
250 mV RMS
L
10 kΩ
14
main
A/mono
Vref
500 mV RMS
50 kΩ
AM
250 mV RMS
50 kΩ
R, B
6 dB
5 kΩ
35 kΩ
10
2.2 µF
11
50 kΩ
Vref
0 dB
Vref
Vi2
12
Vref
3 dB
250 mV RMS
(AM: 500 mV RMS)
2.2 µF
21
15 kΩ
2.2 kΩ
L+R
,A
2
250 mV RMS
10 nF
5%
5 kΩ
6 dB
250 mV RMS
500 mV RMS
TDA9847
RFP
mute
4
CFP
DIGITAL PLL
AND
DEMODULATOR
180 pF
7
1.8 nF
±2%
tan δ ≤ 0.01
CDCL
stereo transmission
27 kΩ
4.7 mH
±5%
Qo= 25
6
Vref
Vref
100 nF
DIGITAL
PLL
dual bit
DIGITAL
INTEGRATOR
(274 Hz)
4
1 kΩ
stereo
bit
DIGITAL PLL
AND
DEMODULATOR
dual transmission
25 kΩ
1
25 kΩ
Vref
SUPPLY
10 µF
POWER-ON
RESET
VP
18
DIGITAL
INTEGRATOR (117 Hz)
OSCILLATOR
CAGC
19
Philips Semiconductors
CD2
10 nF
5%
SCART
Vi4 Vi3
TV and VTR stereo/dual sound processor
with digital identification
1995 May 23
CD1
250 mV
RMS
CONTROL
LOGIC
2
24
3
C1
C2
C3
C4
5
CLP
23
10 nF
8
22
20
1/2 VP
100 µF/
16 V
VP
Fig.2 Block diagram of the bipolar TV/VTR-stereo decoder with fixed coil (alignment-free).
TDA9847
Input and output levels are nominal values related to the SCART norm (AM: m = 0.54, FM: ∆f = ±27 kHz).
The components of the external LC band-pass filter have the following order-No.: Philips Germany only No: 4312 020 17525 or Fastron Sdn. Bha., Malaysia type SMCC 472 J
for L = 4.7 MHz (±5%) Philips Components No: 2222 429 71802, C = 1.8 nF (±2%).
Preliminary specification
10 MHz
MED804
Cref
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
PINNING
SYMBOL
PIN
DESCRIPTION
C1
1
control input Port C1
C2
2
control input Port C2
C4
3
control input Port C4
CAGC
4
AGC capacitor of pilot frequency amplifier
CLP
5
identification low-pass capacitor
C1
1
24 C3
CDCL
6
DC loop capacitor
C2
2
23 XTAL
Vi pil
7
pilot frequency input voltage
3
8
capacitor of reference voltage (1⁄2VP)
C4
Cref
22 VP
Vi1
9
AF input signal voltage 1 [from sound carrier 1 or
AM sound (standard L)]
CAGC
4
21 CD2
CLP
5
20 GND
CDCL
6
Vi pil
7
18 LEDDU
Cref
8
17 CD1
Vi1
9
16 Vo3
Vi2 10
15 Vo4
Vi2
10
AF input signal voltage 2 (from sound carrier 2)
19 LEDST
TDA9847
Vi3
11
AF input signal voltage 3 (SCART)
Vi4
12
AF input signal voltage 4 (SCART)
Vo2
13
AF output signal voltage 2 (main)
Vo1
14
AF output signal voltage 1 (main)
Vo4
15
AF output signal voltage 4 (SCART)
Vo3
16
AF output signal voltage 3 (SCART)
Vi3 11
14 Vo1
CD1
17
50 µs de-emphasis capacitor of AF Channel 1
Vi4 12
13 Vo2
LEDDU
18
LED (dual)
LEDST
19
LED (stereo)
GND
20
ground (0 V)
CD2
21
50 µs de-emphasis capacitor of AF Channel 2
VP
22
supply voltage (5 to 8 V)
XTAL
23
10 MHz crystal input
C3
24
control input Port C3
1995 May 23
MED805
Fig.3 Pin configuration.
5
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
to obtain the AGC voltage for controlling the gain of the
pilot signal amplifier.
FUNCTIONAL DESCRIPTION
AF signal handling
The identification stages consist of two digital PLL circuits
with digital synchronous demodulation and digital
integrators to generate the stereo or dual sound
identification bits which can be indicated via LEDs.
The input AF signals, derived from the two sound carriers,
are processed in analog form using operational amplifiers.
De-matrixing uses the technique of two amplifiers
processing the AF signals. Finally, a source selector
provides the facility to route the mono signal through to the
outputs (‘forced mono’).
A 10 MHz crystal oscillator provides the reference clock
frequency. The corresponding detection bandwidth is
larger than ±50 Hz for the pilot carrier signal, so that
fp-variations from the transmitter can be tracked in the
event of missing synchronization with the horizontal
frequency fH. However the detection bandwidth for the
identification signal is made small (±1 Hz) to reduce
mis-identification.
De-emphasis is performed by two RC low-pass filter
networks with internal resistors and external capacitors.
This provides a frequency response with the tolerances
given in Fig.4.
A source selector, controlled via the control input ports
allows selection of the different modes of operation in
accordance with the transmitted signal. The device was
designed for a nominal input signal (FM: 54% modulation
is equivalent to ∆f = ±27 kHz) of 250 mV RMS value (Vi1
and Vi2) and for a nominal input signal (AM: m = 0.54) of
500 mV RMS value (Vi1), respectively 250 mV RMS (Vi3
and Vi4). A nominal gain of 6 dB for Vi1 and Vi2 signals
(0 dB for Vi1 signal (AM sound)) and 6 dB for Vi3 and Vi4
signals is built-in. By using rail-to-rail operational
amplifiers, the clipping level (THD ≤ 1.5%) is 1.60 V RMS
for VP = 5 V and 2.65 V RMS for VP = 8 V at outputs
Vo1 to Vo3 and Vo4. Care has been taken to minimize
switching plops. Also total harmonic distortion and random
noise are considerably reduced.
Figure 2 shows an example of the alignment-free fp
band-pass filter. To achieve the required QL of around 12,
the Q0 at fp of the coil was chosen to be around 25
(effective Q0 including PCB influence). Using coils with
other Q0, the RC-network (RFP and CFP) has to be adapted
accordingly. It is assumed that the loss factor tan δ of the
resonance capacitor is ≤0.01 at fp.
Copper areas under the coil might influence the loaded Q
and have to be taken into account. Care has also to be
taken in environments with strong magnetic fields when
using coils without magnetic shielding.
Control input ports
The complete IC is controlled by the four control input ports
C1, C2, C3 and C4. Which AF output channel pair can be
selected is determined by the control input Port C4 [LOW:
main; HIGH: SCART; 3-state: preset position
(see Section “General information”)]. With the other
control input ports C1, C2 and C3 the user can select
between different AF sources in accordance with the
transmitter status (see Tables 1 and 2). Finally,
Schmitt triggers are added in the input Port interfaces to
suppress spikes on the control lines C1, C2, C3 and C4.
Identification
The pilot signal is fed via an external RC high-pass filter
and single tuned LC band-pass filter to the input of a gain
controlled amplifier. The external LC band-pass filter in
combination with the external RC high-pass filter should
have a loaded Q-factor of approximately 40 to 50 to
ensure the highest identification sensitivity. By using a
fixed coil (±5%) to save the alignment (see Fig.2), a
Q-factor of approximately 12 is proposed. This may cause
a loss in sensitivity of approximately 2 to 3 dB. A digital
PLL circuit generates a reference carrier, which is
synchronized with the pilot carrier. This reference carrier
and the gain controlled pilot signal are fed to the
AM-synchronous demodulator. The demodulator detects
the identification signal, which is fed through a low-pass
filter with external capacitor CLP (pin 5) to a
Schmitt trigger for pulse shaping and suppression of LOW
level spurious signal components. This is a measure
against mis-identification.
After a Power-On Reset (POR) both registers are reset
(mute mode for both AF channel pairs). After some time
(≤1 ms), when the POR is automatically deactivated, the
switch positions of the main channel (C4 = LOW) are
changed in accordance with the other control input Port
levels. If C4 is HIGH after a POR, the switch positions of
the SCART channel cannot change. The reason is, that
the main register is reset (mute mode; see Table 1). Thus,
at first the main register byte has to be changed out of the
mute function, e.g. sound mute.
The identification signal is amplified and fed through an
AGC low-pass filter with external capacitor CAGC (pin 4)
1995 May 23
TDA9847
6
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
After that, when C4 is HIGH (see Table 2), the switch
positions of the SCART channel are changed in
accordance with the other control line levels.
TDA9847
EXTERNAL MODE
External sound sources, e.g. from SCART input, are fed to
both AF channel pair outputs. When the user chooses the
external mode of the main channel (see Table 1), the
identification circuit is still running, but the LEDs are
switched-off.
When the supply voltage of the TDA9847 is not connected
(standby function), the control lines remain undisturbed.
The logic level combination 1000 of the control input ports
(C4, C3, C2 and C1) is not allowed (see Tables 1 and 2).
Programming of the main and SCART register
Operating mode selection
GENERAL INFORMATION
Tables 1 and 2 show the different operating modes of this
stereo decoder.
The switch positions of both AF channels are directly
controlled by the data of the main and SCART register.
These registers are programmable by a microcontroller.
MUTE MODE
In the 3-state mode the logic content of the C1, C2 and C3
control lines remains stored in the registers for main and
SCART, so the switch positions in the source selector do
not change. The logic content of these control lines can be
changed without changing the switch positions of the
source selector (preset position) to prepare the new
operating mode selection for the main or SCART channel.
The execution of this new mode is achieved by leaving the
preset position (3-state): When the C4 level goes LOW,
the logic content of the control lines C1, C2 and C3 are
valid for the main channel (see Table 1) and in the event
of HIGH the C1, C2 and C3 are valid for the SCART
channel (see Table 2).
This IC has two different mute modes:
1. Mute mode.
2. Sound mute mode.
In the mute mode, when all control input lines are set LOW,
all AF channels are muted (‘fast mute’). Finally, the
integrators are reset provided the user does not leave this
mode (identification is disabled). When the user changes
this mode, the identification circuit starts with the
detection.
In the sound mute mode each AF channel can be
separately muted (0100 = main and 1100 = SCART). The
identification circuit is activated and the LEDs are on or off
in accordance with the detection status of this circuit.
The identification bits and the control lines influence the
operating mode selection for the AF switches in the source
selector and de-matrix, e.g. both AF channels are
programmed in the mono mode (X001,
see Tables 1 and 2). The LEDs are switched-off. When
the identification circuit detects the stereo identification
frequency (fs = 117 Hz) the de-matrix is immediately
switched in the stereo mode without changing the control
line levels. The stereo signals are routed to all AF outputs.
In the event of dual frequency detection (fD = 274 Hz) both
dual sounds are fed to the AF output pairs.
MONO MODE
For the transmitter status mono the user must set the
TDA9847 in the mono mode with X001 or X010
(see Tables 1 and 2). The level combination X011 is
reserved for the AM sound (standard L), because in this
mode the de-emphasis is deactivated and the gain of the
AF signal from input to output is reduced from
6 dB to 0 dB. At the AF outputs the signal has the same
level for standards with FM or AM modulated sound
assuming the same modulation degree.
MICROCONTROLLER WITH 3-STATE OUTPUT PORTS
Figure 10 shows an example of an application circuit for
TDA9847 (VP = 4.5 to 8.8 V) in conjunction with a
microcontroller, which has a LOW/high-ohmic/HIGH
output port to control the main and SCART channel (C4
control line). For the C1, C2 and C3 line the microcontroller
requires only LOW/HIGH output ports. Two resistors RC4A
and RC4B are necessary for the C4 line to generate the
3-state voltage. The values and tolerances of these
components are given in Fig.10.
STEREO MODE
In this mode the choice between stereo and mono (‘forced
mono’) signals is common for both AF channel pairs. The
mode for main and SCART is achieved by control of the
main channel (see Tables 1 and 2).
DUAL MODE
In this mode there is no restriction to select AF inputs and
outputs independently in both channels.
1995 May 23
7
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
When the microcontroller has only open drain ports
available for the C1, C2 and C3 control line, external
pull-up resistors must be connected to these control lines.
Figure 5 shows the hold and set-up time of the C1,
C2 and C3 control line in the 3-state mode,
see Chapter “Characteristics”.
Figure 7 shows an example of a timing diagram to program
the main and SCART register of the TDA9847 with a
microcontroller via the control lines C1, C2, C3 and C4.
Both registers are programmed with the same control line
levels: C1 = LOW, C2 = HIGH and C3 = LOW. The dual
identification frequency is detected and the dual LED is
switched-on. The A-signal (dual mode) is fed to all
AF outputs (see Tables 1 and 2). This is shown in the
beginning of this timing diagram.
MICROCONTROLLER WITH LOW/HIGH OUTPUT PORTS
Figure 11 shows an example of an application circuit for
TDA9847 (VP = 4.5 to 8.8 V) in conjunction with a
microcontroller, which has open drain output ports to
control the main and SCART channel. Four resistors and
two output ports of the microcontroller are necessary to
generate the 3-state voltage. The other control lines have
a pull-up resistor (10 kΩ) in the event of open drain output
stages. These resistors are not necessary for LOW/HIGH
output ports of the microcontroller having internal pull-up
or push-pull stages. The values and tolerances of these
components are given in this figure. Table 4 shows the
conversion logic truth table.
The second period of time shows the programming of the
external mode (C3 goes to HIGH: CC-signal) for the main
channel. The switch positions are immediately changed to
the external AF source, because the C4 level is LOW. The
dual LED is switched-off by the logic (see Section
“External mode”).
For information about programming the different operation
mode selections see Section “Operating mode selection”.
The next periods of time show the way to change the
switch positions for the SCART channel to route B-signals
to the AF outputs (dual mode: BB). At first the control
output Port of the microcontroller for the C4 line goes into
the high ohmic state. The changing of the C1, C2 or C3
level has no influence on the register data. In the timing
diagram the C1 level changes from LOW-to-HIGH and the
C3 level goes from HIGH-to-LOW. In the next steps the C4
line goes from 3-state-to-HIGH, and the level of the other
control lines are valid for the SCART channel, and the
B-signals are fed (dual mode: BB) to the AF outputs of the
main channel.
Power supply
The different supply voltages and currents required for the
analog and digital circuits are derived from an internal
band-gap reference circuit. The AF reference voltage is
1⁄ V . For a fast setting to 1⁄ V an internal start-up circuit
2 P
2 P
is added. A good ripple rejection is achieved with the
external capacitor Cref = 100 µF/16 V in conjunction with
the high ohmic input of the 1⁄2VP pin (pin 8). No additional
DC load on this pin is allowed.
Power-On Reset (POR)
After some time in this example the C1 and C2 levels
change from HIGH-to-LOW and the C3 level goes from
LOW-to-HIGH (sound mute). The SCART channel is
immediately muted, because the level of the C4 line is
HIGH.
When a POR is activated by switching on the supply
voltage or because of a supply voltage breakdown, the
117/274 Hz DPLL, the 117/274 Hz integrator and the logic
will be reset. Both AF channels (main and SCART) are
muted (≤1 ms).
The last period of time shows the programming of the dual
mode (AA) for the main channel. At first the control output
Port of the microcontroller for the C4 line goes into the high
ohmic state. The changing of the C1, C2 or C3 level has
no influence on the register data. The switch positions of
the SCART channel stay in the sound mute.
ESD protection
All pins are ESD protected. The protection circuits
represent the latest state of the art.
Internal circuit
In the 3-state mode the C2 level changes from
LOW-to-HIGH, and the C3 level goes from HIGH-to-LOW.
When the C4 level is LOW, the level of the other control
lines are valid for the main channel. The A-signal (dual
mode) is fed to the main outputs.
The internal pin configuration is given in Fig.7.
The operation mode mute (see Table 1) can be achieved
from any position of the C4 control line without going via
3-state.
1995 May 23
TDA9847
8
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VP
supply voltage (pin 22)
−0.3
+10
V
Vi
input voltage at pins 1 to 3 and 24
−0.3
+9.0
V
Vi
input voltage at pins 4 to 17, 21 and 23
−0.3
VP
V
Vi
input voltage at pins 18 and 19
−0.3
+10
V
Tstg
storage temperature
−25
+150
°C
Tamb
operating ambient temperature
0
+70
°C
Ves
electrostatic handling for all pins
−
±300
V
note 1
Note
1. Charge device model class B: discharging a 200 pF capacitor through a 0 Ω series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE
UNIT
SDIP24
69
K/W
SO24
95
K/W
thermal resistance from junction to ambient in free air
CHARACTERISTICS
VP = 5 V; Tamb = 25 °C; nominal input signal Vi1, 2 = 0.25 V RMS value (FM: 54% modulation is equivalent to
∆f = ±27 kHz); nominal input signal Vi1 = 0.5 V RMS value (AM: m = 0.54); nominal input signal
Vi3, 4 = 0.25 V RMS value (AM: m = 0.54); nominal output signal Vo1, 2, 3, 4 = 0.5 V RMS value; fAF = 1 kHz;
Vi pil = 16 mV RMS value; fpil = 54.6875 kHz (identification frequencies: stereo = 117.48 Hz, dual = 274.12 Hz), 50 µs
pre-emphasis; noise measurement in accordance with “CCIR468-3”, operating oscillator frequency fosc = 10.008 MHz;
currents into the IC positive; measured in test circuit Fig.8; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VP
supply voltage (pin 22)
IP
supply current (pin 22)
Ptot
total power dissipation
63
75
176
mW
Vn(DC)
DC voltage
(pins 9 to 17 and 21)
1⁄
2VP − 0.1
1⁄
2VP
1⁄
2VP + 0.1
V
Vref(DC)
DC reference voltage (pin 8)
1⁄
2VP
− 0.1
1⁄
2VP
1⁄
2VP
V
lL(DC)
DC leakage current (pin 8)
−
1995 May 23
without LED current
9
4.5
5
8.8
V
14
15
20
mA
−
±1
+ 0.1
µA
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
SYMBOL
PARAMETER
TDA9847
CONDITIONS
MIN.
TYP.
MAX.
UNIT
AF Inputs (Vi1 and Vi2 [pins 9 and 10)]
Vi(rms)
Vi(rms)
Gv
nominal input signal voltage
(RMS value)
clipping voltage level
(RMS value)
AF signal voltage gain
Ri
input resistance
Rdeem
internal de-emphasis resistor
(pins 17 and 21)
54% modulation
B/G
−
0.25
−
V
L (only Vi1)
−
0.5
−
V
VP = 5 V; B/G
0.625
0.715
−
V
VP = 8 V; B/G
1.050
1.200
−
V
VP = 5 V; L (only Vi1) 1.200
1.400
−
V
VP = 8 V; L (only Vi1) 2.100
2.350
−
V
THD ≤1.5%
G = Vo/Vi; note 1
B/G
5
6
7
dB
L (only Vi1)
−1
0
+1
dB
40
50
60
kΩ
see Fig.4
4.25
5.0
5.75
kΩ
−
0.25
−
V
VP = 5 V
0.625
0.715
−
V
VP = 8 V
1.050
1.200
5
6
7
dB
40
50
60
kΩ
−
0.5
−
V
VP = 5 V
1.4
1.6
−
V
VP = 8 V
2.4
2.65
−
V
350
450
Ω
Additional AF inputs (pins 11 and 12)
Vi(rms)
nominal input signal voltage
(RMS value)
54% modulation
Vi(rms)
clipping voltage level
(RMS value)
THD ≤ 1.5%
Gv
AF signal voltage gain
Ri
input resistance
G = Vo/Vi; note 1
V
AF outputs (pins 13 to 16)
Vo(rms)
nominal output signal voltage
(RMS value)
THD ≤ 0.3%;
54% modulation
Vo(rms)
clipping voltage level
(RMS value)
THD ≤ 1.5%
Ro
output resistance
250
CL
load capacitor on output
−
−
1.5
nF
RL
load resistor on output
(AC-coupled)
10
−
-
kΩ
B
frequency response
(bandwidth)
fi = 40 to 20000 Hz;
note 2
−0.5
−
+0.5
dB
B−3 dB
frequency response
−3 dB; note 2
300
350
400
kHz
THD
total harmonic distortion
note 1
−
0.2
0.3
%
S/N(W)
weighted signal-to-noise ratio
“CCIR468-3”
(quasi-peak)
66
75
−
dB
1995 May 23
10
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
SYMBOL
αcr
PARAMETER
crosstalk attenuation for
TDA9847
CONDITIONS
MIN.
TYP.
MAX.
UNIT
notes 1 and 3
dual
Zs ≤ 1 kΩ
70
75
−
dB
stereo
Zs ≤ 1 kΩ
40
45
−
dB
αmute
mute attenuation
Zs ≤ 1 kΩ; note 1
76
80
−
dB
∆VDC
change of DC level output
voltage between any two
modes of operation
after switching
−
−
±10
mV
PSRR
power supply ripple rejection
fr = 70 Hz; see Fig.9
50
65
−
dB
IO(DC)
DC output current
−
−
±20
µA
10 MHz crystal oscillator (pin 23)
fr
series resonant frequency of
crystal (fundamental mode)
CL = 20 pF
9.995
10.008
10.021
MHz
fosc
operating oscillator frequency
(running in parallel resonance
mode)
over operating
temperature range
including ageing and
influence of drive
circuit
9.988
10.008
10.028
MHz
Rxtal
equivalent crystal series
resistance
even at extremely low
drive level (<1 pW)
over operating
temperature range
with C0 = 6 pF
−
60
200
Ω
Rn
crystal series resistance of
unwanted mode
2 × Rr
−
−
Ω
C0
crystal parallel capacitance
−
6
10
pF
C1
crystal motional capacitance
with Rr ≤ 100 Ω
−
25
50
fF
Pxtal
level of drive in operation
−
−
5
µW
Vosc(p-p)
oscillator operating voltage
(peak-to-peak value)
500
550
600
mV
−
100
mV
Pilot processing
Vi pil(rms)
pilot input voltage level at pin 7 unmodulated
(RMS value)
5
Ri pil
pilot input resistance
500
1000
−
kΩ
Ci pil
pilot input capacitance
−
−
3
pF
m
modulation depth
25
50
75
%
1995 May 23
AM
11
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
SYMBOL
∆fpil
PARAMETER
pilot PLL pull-in frequency
range (referenced to
fpil = 54.6875 kHz)
TDA9847
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fosc = 9.988 MHz
lower side
−405
−
−405
Hz
upper side
192
−
192
Hz
lower side
−296
−
−296
Hz
upper side
302
−
302
Hz
lower side
−188
−
−188
Hz
upper side
411
−
411
Hz
0
−
1.7
ms
450
600
750
Hz
fosc = 10.008 MHz
fosc = 10.028 MHz
tpil
pilot PLL pull-in time
fLP
low-pass frequency response
−3 dB
R5
low-pass output resistance
18.75
25
31.25
kΩ
V5(rms)
identification threshold voltage
(RMS value)
−
−
70
mV
QL
loaded quality factor of
resonance circuit
high sensitivity;
see Fig.1
40
−
50
loaded quality factor of
resonance circuit with fixed
coil
sensitivity loss
2 to 3 dB; see Fig.2
−
12
−
AGC acquisition time
Vi pil(rms) switched from
0 to 100 mV (RMS
value)
−
−
0.1
s
tacqui AGC
Identification (internal functions)
Vi tuner
identification voltage sensitivity note 4
−
28
−
dBµV
C/N
pilot carrier-to-noise ratio for
start of identification
note 5
−
33
-
dB/Hz
−
−
2
dB
stereo
−0.63
−
−0.63
Hz
dual
−0.69
−
−0.69
Hz
stereo
0.63
−
0.63
Hz
dual
0.69
−
0.69
Hz
H
hysteresis
note 4
fdet
pull-in frequency range of
identification PLL (referred to
fdet stereo = 117.48 Hz and
fdet dual = 274.12 Hz)
lower side
tdet
fident
tintegr
upper side
pull-in time of identification
PLL (referenced to
fdet stereo = 117.48 Hz and
fdet dual = 274.12 Hz)
stereo
0
−
0.8
s
dual
0
−
0.8
s
identification window
frequency width (referred to
fdet stereo = 117.48 Hz and
fdet dual = 274.12 Hz)
stereo; note 6
2.2
−
2.2
Hz
dual; note 6
2.3
−
2.3
Hz
0.94
−
0.94
s
integrator time constant
1995 May 23
12
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
SYMBOL
PARAMETER
tident(on)
total identification time on
tident(off)
total identification time off
TDA9847
CONDITIONS
MIN.
TYP.
−
MAX.
2.0
UNIT
stereo; note 7
0.35
s
dual; note 7
0.35
−
2.0
s
stereo; note 8
0.60
−
1.5
s
dual; note 8
0.60
−
1.5
s
LED (pins 18 and 19)
VL(off)
output voltage
LED off
−
−
8.8
V
VL(on)
output voltage
LED on
−
−
0.7
V
IL(off)
input current
LED off
−
−
1
µA
IL(on)
input current
LED on
−
−
12
mA
−
0.8
V
Control input ports C1 to C3 (pins 1, 2 and 24)
VIL
LOW level input voltage
0
VIH
HIGH level input voltage
2.0
5.0
8.8
V
IIL
LOW level input current
−
−
-1
µA
IIH
HIGH level input current
−
−
1
µA
Control input Port C4 (pin 3)
VIL
LOW level input voltage
0
−
0.8
V
VCT
3-state level input voltage
1.5
1.8
2.1
V
VIH
HIGH level input voltage
2.8
5.0
8.8
V
IIL
LOW level input current
−
−
−1
µA
ICT
3-state level input current
−
−
−1
µA
IIH
HIGH level input current
−
−
1
µA
th1
HIGH level hold time
see Fig.5
5
−
−
µs
th2
LOW level hold time
see Fig.5
5
−
−
µs
tsu1
HIGH level set-up time
see Fig.5
0.25
−
−
µs
tsu2
LOW level set-up time
see Fig.5
0.25
−
−
µs
Notes to the characteristics
1. Vo = 0.5 V (RMS value); f = 1 kHz.
2. Without de-emphasis capacitors with respect to nominal gain.
3. In dual mode: A (B)-signal into B (A) channel; in stereo mode: R-signal into left channel; L-signal = 0.
4. Tuner input signal, measured with PCALH reference front end (1⁄2EMF, 75 Ω, 2T/20T/white bar, 100% video) and
PC/SC1 = 13 dB; PC/SC2 = 20 dB. The pilot band-pass has to be aligned.
5. Bandwidth of the pilot BP-filter B−3 dB = 1.2 kHz. Vi2 input driven with identification-modulated pilot carrier and white
noise.
6. Identification window is defined as twice the pull-in frequency range (lower plus upper side) of identification PLL
(steady detection) plus window increase due to integrator (fluctuating detection).
7. The maximal total system identification time on is equal to tident(on) plus tacqui AGC.
8. The maximal total system identification time off is equal to tident(off).
1995 May 23
13
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
Table 1
TDA9847
Control input Port matrix to select AF inputs and AF outputs (main channel)
INPUT SIGNAL
ST/DS/M
MODE
OUTPUT SIGNAL
SCART
Vi1
9
Vi2
10
Vi3
11
Vi4
12
MAIN
Vo1
14
Vo2
13
SCART
Vo3
16
Vo4
15
CONTROL INPUT
PORT(1)
C4
3
C3
24
C2
2
C1
1
LED
DUAL
18
STEREO
19
off
Mute(2)
−
−
−
−
−
no signal
no signal
0
0
0
0
off
Sound mute
−
−
−
−
−
no signal
note 3
0
1
0
0
note 4 note 4
Mono
M
M
−
−
−
M
M
note 3
0
0
0
1
off
off
M
−
−
−
M
M
0
0
1
0
off
off
AM
−
−
−
AM
AM
0
0
1
1
off
off
S
R
−
−
L
R
L
R
0
0
0
1
off
on
S
R
−
−
S
S
S
S
0
0
1
0
off
on
S
R
−
−
S
S
S
S
0
0
1
1
off
on
A
B
−
−
A
B
0
0
0
1
on
off
A
B
−
−
A
A
0
0
1
0
on
off
A
B
−
−
B
B
0
0
1
1
on
off
−
−
C
D
C
D
0
1
0
1
off
off
−
−
C
D
C
C
0
1
1
0
off
off
−
−
C
D
D
D
0
1
1
1
off
off
Stereo
Dual
External
ST
DS
−
note 3
note 3
Notes
1. The combination 1000 is not allowed.
2. In mute mode the content of the 117 Hz/274 Hz integrator will be reset. The LEDs are switched-off.
3. The previous state is unchanged.
4. The LED shows the identification status.
1995 May 23
14
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
Table 2
TDA9847
Control input Port matrix to select AF inputs and AF outputs (SCART channel)
INPUT SIGNAL
ST/DS/M
MODE
OUTPUT SIGNAL
SCART
Vi1
9
Vi2
10
Vi3
11
Vi4
12
MAIN
Vo1
14
−
−
−
−
−
note 2
Mono
M
M
−
−
−
note 2
Stereo
ST
Dual
DS
−
External
SCART
Vo2
13
Sound mute
CONTROL INPUT
PORT(1)
Vo3
16
Vo4
15
C4
3
C3
24
C2
2
C1
1
1
1
0
0
1
0
0
1
no signal
M
M
M
−
−
−
M
M
1
0
1
0
AM
−
−
−
AM
AM
1
0
1
1
S
R
−
−
−
−
1
0
0
1
note 2
S
R
−
−
−
−
1
0
1
0
S
R
−
−
−
−
1
0
1
1
A
B
−
−
A
B
1
0
0
1
A
B
−
−
A
A
1
0
1
0
A
B
−
−
−
−
C
D
−
−
C
−
−
C
note 2
B
B
1
0
1
1
C
D
1
1
0
1
D
C
C
1
1
1
0
D
D
D
1
1
1
1
note 2
Notes
1. The combination 1000 is not allowed.
2. The previous state is unchanged.
Table 3
Explanation of Tables 1 and 2
SIGNAL
DESCRIPTION
R
right
L
left
S
( L + R)
-------------------2
A and B
dual sound A/B
C and D
external sound source (SCART)
AM
AM sound (standard L)
M
mono sound
DS
dual sound
ST
stereo sound
1995 May 23
Table 4
Conversion logic truth table for the C4 control
line (see Fig.11)
MICROPROCESSOR
OUTPUT
CONTROL PORTS
15
TDA9847
C41
C42
C4
C4-level
0
0
1
≥3.2 V
1
0
3-state
1.8 ±0.25 V
1
1
0
≤0.45 V
0
1
not allowed
undefined
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
MED647
+2
R: −15%;
C: −5%
VoAF
(dB)
+1
0
−1
R: +15%;
C: +5%
−2
10
Fig.4
10 2
10 3
10 4
10 5
foAF (Hz)
Tolerance scheme of AF frequency response; de-emphasis with CD1, CD2 = 10 nF (±5%);
Rinternal = 5 kΩ (±15%).
V C4
(V)
5
HIGH
2.8
3-state
2.1
1.5
0.8
LOW 0
VC1/C2/C3
(V)
5
t h1
t h2
t su1
t su2
t h1
t h2
t su1
t (s)
t su2
HIGH
2
0.8
LOW 0
t (s)
MED811
Fig.5 Waveforms showing the hold and set-up times of the C1 to C3 control line in the 3-state mode.
1995 May 23
16
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
V C1
(V)
5
HIGH
2
0.8
LOW 0
t (s)
V C2
(V)
5
HIGH
2
0.8
LOW 0
t (s)
V C3
(V) 5
HIGH
2
0.8
LOW 0
t (s)
V C4
(V) 5
HIGH
2.8
3-state
2.1
1.5
0.8
t (s)
LOW 0
valid main
storage main
valid SCART
storage SCART
valid main
AF outputs
main
dual: AA
SCART
dual: AA
dual: AA
external: CC
dual: BB
sound mute
MED810
Fig.6
Programming the main and SCART register of the TDA9847 with a microcontroller via the control lines
C1 to C4; the dual identification frequency is detected.
1995 May 23
17
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
INTERNAL CIRCUITRY
VP
VP
3 µA
C1
3 µA
2 kΩ
1
2 kΩ 24
5 kΩ
VP
–
+5 V
2 kΩ
13 kΩ
TDA9847
VP
CAGC
3
21
C
D2
–
+
20
4
GND
60 µA
25 kΩ
VP
19
VP
LEDST
5
40 µA
25 kΩ
VP
VP
18
60 µA
Z\xV
P
CDCL
5 kΩ
3 µA
2 kΩ
VP
CLP
VP
–
VP
3 µA
C4
22
3 pF
+
2
XTAL
+
3 µA
C2
C3
23
LEDDU
6
VP
25 kΩ
40 µA
5 kΩ
5 kΩ
+
5 kΩ
7
17
C
D1
–
Vi pil
–
C ref
+
8
22.5 kΩ
5 kΩ
5 kΩ
Vi1
9
VP
16
IB
15 kΩ
35 kΩ
Vi2
VP
IB
200 µA
VP
15
IB
Z\xV
10
P
IB
200 µA
AF inputs
14
Z\xV
Vi3
P
11
50 kΩ
200 µA
IB
P
12
50 kΩ
IB
200 µA
Z\xV
P
MED807
VP
ESD protection diode
for pins 4 to 17, 21 and 23
zener diode protection
for pins 1, 2, 3, 18, 19, 20 and 24
Fig.7 Internal circuits.
1995 May 23
18
Vo1
VP
13
Z\xV
Vi4
Vo4
VP
AF outputs
50 kΩ
Vo3
Vo2
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
TEST AND APPLICATION INFORMATION
control input
ports
100 µF/16V
Cref
1/2 VP
C1
1
24
C2
2
23
C4
3
22
4
5%
21
CD2 10 nF
5
20
XTAL
C3 control input port
10 MHz
CAGC
10 µF
CLP
10 nF
CDCL
100 nF
6
CVP
VP
10 µF
stereo transmission
19
1 kΩ
TDA9847
3.3 nF 2.5 mH
7
18
5%
8
17
9
16
Vo3
10
15
Vo4
external sound V
i3
source C
11
14
Vo1
external sound V
i4
source D
12
13
Vo2
2.2 kΩ
AF from 5.5 MHz V
or from AM demodulator (L) i1
VP
dual transmission
47 pF
30 kΩ
50 µs
de-emphasis
CD1 10 nF
50 µs
de-emphasis
SCART
AF from 5.742 MHz Vi2
2.2 kΩ
main
SCART
4 x 2.2 µF
MED806
Fig.8 Test circuit of the stereo decoder TDA9847.
1995 May 23
19
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
20
VP
16
22
15
TDA9847
HP3585
14
10 kΩ
100 µF
5 V modulated
with 200 mV (p-p)
13
8
9
10
11
12
100 µF/16V
70 Hz
100 µF
MED808
Fig.9 Test circuit for measurement of ripple rejection.
VP = 5 V ±10%
VP = 4.5 to 8.8 V
RC4A
11 kΩ
C4
22
3
RC4B
6.2 kΩ
STEREO
DECODER
MICROCONTROLLER
C1
C2
1
TDA9847
2
C3
24
20
MED809
All resistors: ±2%.
Fig.10 Application circuit for the stereo decoder TDA9847 in conjunction with a microcontroller
[LOW/HIGH output ports with internal pull-ups or push-pull stages (C1 to C3) and
LOW/high-ohmic/HIGH output Port (C4)].
1995 May 23
20
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
VP = 5 V ±10%
VP = 4.5 to 8.8 V
RC42A
10 kΩ
C41
RC41A
10 kΩ R
C41B
100 kΩ
RC42B
C42
100 kΩ
MICROCONTROLLER
RC1
10 kΩ
RC2
10 kΩ
RC4A
11 kΩ
22
C4
3
RC4B
6.2 kΩ
STEREO
DECODER
TDA9847
RC3
10 kΩ
C1
1
C2
2
C3
24
20
MED812
Resistors RC4A and RC4B ±2%; all other resistors ±10%; transistors BC types or equivalent.
Fig.11 Application circuit for the stereo decoder TDA9847 in conjunction with a microcontroller
(LOW/HIGH with open-drain output ports).
1995 May 23
21
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
PACKAGE OUTLINES
SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
SOT234-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
(e 1)
w M
MH
b
13
24
pin 1 index
E
1
12
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.7
0.51
3.8
1.3
0.8
0.53
0.40
0.32
0.23
22.3
21.4
9.1
8.7
1.778
10.16
3.2
2.8
10.7
10.2
12.2
10.5
0.18
1.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT234-1
1995 May 23
EUROPEAN
PROJECTION
22
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
inches
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.61
0.60
0.30
0.29
0.050
0.419
0.043
0.055
0.394
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
Z
(1)
θ
8o
0o
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT137-1
075E05
MS-013AD
1995 May 23
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
23
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
SOLDERING
BY SOLDER PASTE REFLOW
Plastic dual in-line packages
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.
Plastic small outline packages
BY WAVE
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
1995 May 23
24
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9847
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1995 May 23
25
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
NOTES
1995 May 23
26
TDA9847
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
NOTES
1995 May 23
27
TDA9847
Philips Semiconductors – a worldwide company
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Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. (0 212)279 27 70, Fax. (0212)282 67 07
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Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
SCD40
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
533061/1500/02/pp28
Document order number:
Date of release: 1995 May 23
9397 750 00154