Si9936BDY Vishay Siliconix Dual N-Channel 30-V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) RDS(on) (Ω) 30 ID (A) 0.035 at VGS = 10 V 6.0 0.052 at VGS = 4.5 V 4.9 • Halogen-free According to IEC 61249-2-21 Definition • Compliant to RoHS Directive 2002/95/EC D1 D2 SO-8 S1 1 8 D1 G1 2 7 D1 S2 3 6 D2 G2 4 5 D2 G1 G2 Top View Ordering Information: Si9936BDY-T1-E3 (Lead (Pb)-free) Si9936BDY-T1-GE3 (Lead (Pb)-free and Halogen-free) S1 S2 N-Channel MOSFET N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol 10 s Steady State Drain-Source Voltage VDS 30 Gate-Source Voltage VGS ± 20 Continuous Drain Current (TJ = 150 °C)a TA = 25 °C TA = 70 °C Continuous Source Current (Diode Conduction)a IS TA = 25 °C TA = 70 °C PD 4.5 4.8 3.6 40 1.7 0.9 2.0 1.1 1.3 0.7 TJ, Tstg Operating Junction and Storage Temperature Range V 6.0 IDM Pulsed Drain Current Maximum Power Dissipationa ID Unit - 55 to 150 A W °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambienta Maximum Junction-to-Foot (Drain) Symbol t ≤ 10 s Steady State Steady State RthJA RthJF Typical Maximum 53 62.5 92 110 30 40 Unit °C/W Notes: a. Surface Mounted on 1" x 1" FR4 board. Document Number: 72521 S09-0704-Rev. C, 27-Apr-09 www.vishay.com 1 Si9936BDY Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. 1.0 Typ. Max. Unit Static VGS(th) VDS = VGS, ID = 250 µA Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V Zero Gate Voltage Drain Current IDSS On-State Drain Currenta ID(on) Gate Threshold Voltage Drain-Source On-State Resistancea Diode Forward Voltage a V nA VDS = 30 V, VGS = 0 V 1 VDS = 30 V, VGS = 0 V, TJ = 55 °C 5 VDS ≥ 5 V, VGS = 10 V RDS(on) Forward Transconductancea 3.0 ± 100 µA 40 A VGS = 10 V, ID = 6 A 0.028 0.035 VGS = 4.5 V, ID = 4.9 A 0.041 0.052 gfs VDS = 15 V, ID = 6 A 12 VSD IS = 1.7 A, VGS = 0 V 0.8 1.2 8.6 13 Ω S V Dynamicb Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg VDS = 15 V, VGS = 10 V, ID = 6 A f = 1 MHz VDD = 15 V, RL = 15 Ω ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω tr td(off) Turn-Off Delay Time Fall Time tf Source-Drain Reverse Recovery Time trr Ω 2.8 td(on) Turn-On Delay Time Rise Time nC 1.8 1.5 IF = 1.7 A, dI/dt = 100 A/µs 10 15 15 25 25 40 10 15 20 40 ns Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 40 40 VGS = 10 V thru 6 V 35 25 °C 30 I D - Drain Current (A) 30 I D - Drain Current (A) TC = - 55 °C 35 5V 25 20 4V 15 125 °C 25 20 15 10 10 5 5 3V 0 0 0 www.vishay.com 2 1 2 3 4 5 0 1 2 3 4 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 5 6 Document Number: 72521 S09-0704-Rev. C, 27-Apr-09 Si9936BDY Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.10 800 600 C - Capacitance (pF) R DS(on) - On-Resistance (Ω) 700 0.08 0.06 VGS = 4.5 V 0.04 VGS = 10 V Ciss 500 400 300 200 Coss 0.02 100 Crss 0.00 0 0 5 10 15 20 25 30 35 40 0 10 15 20 25 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current Capacitance 30 1.6 10 VGS = 10 V ID = 6 A VDS = 15 V ID = 6 A 1.4 6 4 (Normalized) 8 R DS(on) - On-Resistance VGS - Gate-to-Source Voltage (V) 5 1.2 1.0 0.8 2 0.6 - 50 0 0 2 4 6 8 10 - 25 0 25 50 75 100 125 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature 150 0.10 40 RDS(on) - On-Resistance (Ω) I S - Source Current (A) ID = 6 A TJ = 150 °C 10 TJ = 25 °C 0.08 0.06 0.04 0.02 1 0.0 0.00 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VSD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage Document Number: 72521 S09-0704-Rev. C, 27-Apr-09 1.6 0 2 4 6 8 10 VGS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage www.vishay.com 3 Si9936BDY Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.4 50 40 ID = 250 µA 0.0 Power (W) VGS(th) Variance (V) 0.2 - 0.2 30 20 - 0.4 10 - 0.6 - 0.8 - 50 - 25 0 25 50 75 100 125 0 10 -3 150 10 -2 10 -1 1 10 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power 100 600 100 IDM Limited Limited by RDS(on)* P(t) = 0.0001 I D - Drain Current (A) 10 P(t) = 0.001 1 ID(on) Limited P(t) = 0.01 P(t) = 0.1 0.1 TA = 25 °C Single Pulse BVDSS Limited 0.01 0.1 1 P(t) = 1 P(t) = 10 DC 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 PDM 0.05 t1 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = R thJA = 92 °C/W 0.02 3. T JM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10 - 4 10 - 3 10 - 2 10 - 1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient www.vishay.com 4 Document Number: 72521 S09-0704-Rev. C, 27-Apr-09 Si9936BDY Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 - 4 10 - 3 10 - 2 10 - 1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72521. Document Number: 72521 S09-0704-Rev. C, 27-Apr-09 www.vishay.com 5 Package Information Vishay Siliconix SOIC (NARROW): 8-LEAD JEDEC Part Number: MS-012 8 6 7 5 E 1 3 2 H 4 S h x 45 D C 0.25 mm (Gage Plane) A e B All Leads q A1 L 0.004" MILLIMETERS INCHES DIM Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.20 0.004 0.008 B 0.35 0.51 0.014 0.020 C 0.19 0.25 0.0075 0.010 D 4.80 5.00 0.189 0.196 E 3.80 4.00 0.150 e 0.101 mm 1.27 BSC 0.157 0.050 BSC H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.50 0.93 0.020 0.037 q 0° 8° 0° 8° S 0.44 0.64 0.018 0.026 ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498 Document Number: 71192 11-Sep-06 www.vishay.com 1 VISHAY SILICONIX TrenchFET® Power MOSFETs Application Note 808 Mounting LITTLE FOOT®, SO-8 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/ppg?72286), for the basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. 0.288 7.3 0.050 1.27 0.196 5.0 0.027 0.69 0.078 1.98 0.2 5.07 Figure 1. Single MOSFET SO-8 Pad Pattern With Copper Spreading Document Number: 70740 Revision: 18-Jun-07 0.050 1.27 0.088 2.25 0.088 2.25 0.027 0.69 0.078 1.98 0.2 5.07 Figure 2. Dual MOSFET SO-8 Pad Pattern With Copper Spreading The minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose. Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. www.vishay.com 1 APPLICATION NOTE In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. 0.288 7.3 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SO-8 0.172 (4.369) 0.028 0.022 0.050 (0.559) (1.270) 0.152 (3.861) 0.047 (1.194) 0.246 (6.248) (0.711) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 22 Document Number: 72606 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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Material Category Policy Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000