ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS843246I is a Crystal-to-3.3V LVPECL Clock ICS Synthesizer/Fanout Buffer designed for Fibre HiPerClockS™ Channel and Gigabit Ethernet applications and is a member of the HiperClockS™ family of High Performance Clock Solutions from IDT. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 26.5625MHz crystal for a Fibre Channel. The low phase noise characteristics of the ICS843246I make it an ideal clock for these demanding applications. • Six LVPECL outputs • Crystal oscillator interface • VCO range: 490MHz to 680MHz • Crystal input frequency range: 25MHz to 33.333MHz • RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz to 20MHz): 0.41ps (typical) • Full 3.3V or 3.3V core, 2.5V output supply mode Core/Output 3.3V/3.3V 3.3V/2.5V • -40°C to 85°C ambient operating temperature SELECT FUNCTION TABLE Inputs FB_SEL • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Function N_SEL1 N_SEL0 M Divide N Divide M/N 0 0 0 20 2 10 0 0 1 20 4 5 0 1 0 20 5 4 0 1 1 20 8 2.5 1 0 0 24 3 8 1 0 1 24 4 6 1 1 0 24 6 4 1 1 1 24 12 2 BLOCK DIAGRAM Q0 nQ0 PLL_BYPASS Pullup Q1 1 XTAL_IN OSC PLL 0 nQ1 Output Divider XTAL_OUT nQ2 Q3 Feedback Divider N_SEL0 VCCO VCCO nQ2 Q2 nQ1 Q1 nQ0 Q0 PLL_BYPASS VCCA VCC FB_SEL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 nQ3 Q4 nQ4 Q5 nQ5 N_SEL1 VEE VEE N_SEL0 XTAL_OUT XTAL_IN nQ3 ICS843246I FB_SEL Pulldown N_SEL1 Q2 PIN ASSIGNMENT Q4 Pullup nQ4 Pullup Q5 24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.9mm body package G Package Top View nQ5 IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 1 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 VCCO 3, 4 5, 6 Type Description Power Output supply pins. nQ2, Q2 Output Differential output pair. LVPECL interface levels. nQ1, Q1 Output Differential output pair. LVPECL interface levels. 7, 8 nQ0, Q0 Output 9 PLL_BYPASS Input 10 VCCA Power Differential output pair. LVPECL interface levels. Selects between the PLL and crystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT. LVCMOS / LVTTL interface levels. Analog supply pin. 11 VCC Power Core supply pin. 12 13, 14 15, 18 16, 17 FB_SEL XTAL_IN, XTAL_OUT N_SEL0 N_SEL1 VEE Input 19, 20 nQ5, Q5 Output 21, 22 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVPECL interface levels. Input Input Pullup Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pullup Output frequency select pins. LVCMOS/LVTTL interface levels. Negative supply pins. Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER Test Conditions 2 Minimum Typical Maximum Units ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER TABLE 3. TYPICAL APPLICATION FREQUENCY FUNCTION TABLE Inputs XTAL (MHz) FB_SEL Function N_SEL1 N_SEL0 M VCO (MHz) N Output (MHz) 25 0 0 0 20 500 2 250 25 0 0 1 20 500 4 125 25 0 1 0 20 500 5 10 0 25 0 1 1 20 500 8 62.5 25 1 0 0 24 600 3 200 25 1 0 1 24 600 4 150 25 1 1 0 24 600 6 100 25 1 1 1 24 600 12 50 26.5625 0 1 0 20 531.25 5 106.25 26.5625 1 0 0 24 637.5 3 212.5 26.5625 1 0 1 24 637.5 4 159.375 26.5625 1 1 0 24 637.5 6 106.25 26.5625 1 1 1 24 637.5 12 53.125 30 0 0 0 20 600 2 300 30 0 0 1 20 600 4 150 30 0 1 0 20 600 5 12 0 30 0 1 1 20 600 8 75 31.25 0 0 0 20 625 2 312.5 31.25 0 0 1 20 62 5 4 156.25 31.25 0 1 0 20 62 5 5 12 5 31.25 0 1 1 20 625 8 78.125 33.3333 0 0 0 20 666.6667 2 333.3333 33.3333 0 0 1 20 666.6667 4 166.6667 33.3333 0 1 0 20 666.6667 5 133.3333 33.3333 0 1 1 20 666.6667 8 83.3333 IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 3 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 37°C/W (0 mps) -65°C to 150°C Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3. 3 3.465 V VCCA Analog Supply Voltage VCC – 0.10 3. 3 VCC V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 180 mA ICCA Analog Supply Current 10 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3. 3 3.465 V VCCA Analog Supply Voltage VCC – 0.10 3.3 VCC V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 180 mA ICCA Analog Supply Current 10 mA TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum 2 -0.3 FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER Typical Maximum Units VCC + 0.3 V 0.8 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA VCC = 3.465V, VIN = 0V -5 µA VCC = 3.465V, VIN = 0V -150 µA 4 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 33.333 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Maximum Units 340 MHz NOTE: Characterized using an 18pF parallel resonant crystal. TABLE 6A. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter FOUT t jit(Ø) Test Conditions Output Frequency RMS Phase Jitter (Random) t sk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time Minimum Typical 40.833 125MHz, Integration Range: 1.875MHz - 20MHz 312.5MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% 0.41 ps 0.47 ps 200 odc Output Duty Cycle 45 See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. 40 ps 700 ps 55 % Maximum Units 340 MH z TABLE 6B. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO = 2.5V±5%, VEE = 0V, TA = -40°C TO 85°C Symbol Parameter FOUT t jit(Ø) Test Conditions Output Frequency RMS Phase Jitter (Random) t sk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time Minimum Typical 40.833 125MHz, Integration Range: 1.875MHz - 20MHz 312.5MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% 0.44 ps 0.46 ps 200 odc Output Duty Cycle 45 See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 5 40 ps 700 ps 55 % ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER ➤ TYPICAL PHASE NOISE AT 125MHZ @ 3.3V Gb Ethernet Filter Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.41ps (typical) Phase Noise Result by adding Gb Ethernet Filter to raw data OFFSET FREQUENCY (HZ) ➤ TYPICAL PHASE NOISE AT 312.5MHZ @ 3.3V Gb Ethernet Filter Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz 312.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.47ps (typical) Phase Noise Result by adding Gb Ethernet Filter to raw data OFFSET FREQUENCY (HZ) IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 6 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2.8V±0.04V 2V 2V 2.8V±0.04V 2V VCC VCC, VCCO Qx SCOPE Qx VCCO SCOPE VCCA VCCA LVPECL LVPECL nQx VEE nQx VEE -0.5V ± 0.125V -1.3V ± 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power nQx Qx nQy Phase Noise Mask Qy tsk(o) f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot OUTPUT SKEW RMS PHASE JITTER nQ0:nQ5 80% 80% Q0:Q5 VSW I N G Clock Outputs t PW 20% 20% tR t tF odc = PERIOD t PW x 100% t PERIOD OUTPUT RISE/FALL TIME IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 7 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843246I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC , V CCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CRYSTAL INPUT INTERFACE below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS843246I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p FIGURE 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 8 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure X. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 125Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION 9 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These ter minations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL DRIVER TERMINATION EXAMPLE IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 10 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER LAYOUT GUIDELINE Figure 5 shows an example of ICS843246I application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 22pF and C2 = 22pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. Two examples of LVPECL termination are shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. 3.3V PLL_BY PASS VCC VCCA R2 10 R3 133 R5 133 Zo = 50 Ohm C3 10uF C4 0.01u + Zo = 50 Ohm Logic Control Input Examples To Logic Input pins To Logic Input pins RD1 Not Install R6 82.5 12 11 10 9 8 7 6 5 4 3 2 1 RU2 Not Install R4 82.5 RD2 1K U1 843246I XTAL_IN FB_SEL XTAL_OUT VCC N_SEL0 VCCA VEE PLL_BYPASS VEE Q0 N_SEL1 nQ0 nQ5 Q1 Q5 nQ1 nQ4 Q2 Q4 nQ2 nQ3 VCCO Q3 VCCO RU1 1K FB_SEL Set Logic Input to '0' VDD - VCCO VCC=3.3V VCCO=3.3V 13 14 15 16 17 18 19 20 21 22 23 24 Set Logic Input to '1' VDD VCC Zo = 50 Ohm VCC (U1-11) + X1 C2 22pF C5 0.1uF 25MHz 18pF Zo = 50 Ohm C1 22pF (U1-1) VCCO C6 0.1uF N_SEL0 R7 50 R8 50 N_SEL1 (U1-2) Optional Y-Termination C7 0.1uF R9 50 FIGURE 5. SCHEMATIC OF RECOMMENDED LAYOUT THERMAL RELEASE PATH The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is contacted through solder as shown in Figure 4. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor’s Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology. EXPOSED PAD SOLDER M ASK SOLDER SIGNAL TRACE SIGNAL TRACE GROUND PLANE Expose Metal Pad THERM AL VIA FIGURE 6. P.C. BOARD IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER FOR (GROUND PAD) EXPOSED PAD THERMAL RELEASE PATH EXAMPLE 11 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843246I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843246I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. · · Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 180mA = 623.7mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 6* 30mW = 180mW Total Power_MAX (3.465V, with all outputs switching) = 623.7mW + 180mW = 803.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.804W * 37°C/W = 114.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, E-PAD FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 0 1 2.5 37°C/W 31°C/W 30°C/W 12 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V – 2V. CCO • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/R ] * (VCCO_MAX – VOH_MAX) = L L [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/R ] * (VCCO_MAX – VOL_MAX) = L L [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 13 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP, E-PAD TABLE 9. PACKAGE DIMENSIONS FOR 24 LEAD TSSOP, E-PAD SYMBOL Millimeters Minimum N Nominal Maximum 24 A -- 1.10 A1 0.05 0.15 A2 0.85 b 0.19 b1 0.19 c 0.09 c1 0.09 D 7. 7 0 E E1 0.90 0.95 0.30 0.22 0.25 0.20 0.127 0.16 7.80 7.90 6.40 BASIC 4.30 e 4.40 4.50 0.65 BASIC L 0.50 0.60 P 5.0 5.5 P1 3.0 3.2 α 0° 8° aaa 0.076 bbb 0.10 0.70 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 14 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP, E-PAD θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37°C/W 31°C/W 30°C/W TRANSISTOR COUNT The transistor count for ICS843246I is: 3863 IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 15 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843246BGI ICS843246BGI 24 Lead TSSOP, E-Pad tube -40°C to 85°C ICS843246BGIT ICS843246BGI 24 Lead TSSOP, E-Pad 2500 tape & reel -40°C to 85°C ICS843246BGILF ICS843246BGIL 24 Lead "Lead-Free" TSSOP, E-Pad tube -40°C to 85°C ICS843246BGILFT ICS843246BGIL 24 Lead "Lead-Free" TSSOP, E-Pad 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 16 ICS843246BGI REV. A AUGUST 2, 2007 ICS843246I FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA