Integrated Circuit Systems, Inc. ICS9148-36 Frequency Generator & Integrated Buffers for PENTIUM/ProTM General Description Features The ICS9148-36 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Generates the following system clocks: - 3 CPU(2.5V/3.3V) upto 100MHz. - 6 PCI(3.3V) @ 33.3MHz - 3AGP(3.3V) @ 2 x PCI - 13 SDRAMs(3.3V) up to 100MHz - 1 REF (3.3V) @ 14.318MHz Skew characteristics: - CPU CPU<250ps - CPU(early) PCI : 1-4ns, Center 2-6ns - AGP - PCI: 250ps Supports Spread Spectrum modulation & I2C programming for Power Management, Frequency Select Efficient Power management scheme through PCI and CPU STOP CLOCKS. Uses external 14.318MHz crystal 48 pin 300mil SSOP. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9148-36 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SDRAM12 output may be used as a feed back into an off chip PLL. Block Diagram Pin Configuration Power Groups VDD1 = REF (0:1), X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:12), supply for PLL core VDD4 = AGP (1:2) VDD5 = Fixed PLL, 48MHz , AGP0 VDDL = CPUCLK (0:2) 9148-36 Rev I 11/11/99 48-Pin SSOP * Internal Pull-up Resistor of 240K to 3.3V on indicated inputs Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9148-36 Pin Descriptions PIN NUMBER 1 2 3,9,16,22,27, 33,39,45 4 P I N NA M E VDD1 REF0 TYPE PWR OUT C P U 3 . 3 # _ 2 . 5 1,2 IN GND PWR SDRAM 11 OUT PCI_STOP#1 IN SDRAM 10 OUT SDRAM (0:9) OUT SDRAM clock outputs. AGP_STOP# IN IN 5 X2 OUT VDD2 PWR PCICLK_F OUT 7 FS11, 2 10, 11, 12, 13 14 15 17 18 28, 29, 31, 32, 34, 35,37,38 20 PCICLK0 FS21, 2 PCICLK(1:4) VDD5 BUFFERIN CPU_STOP#1 SDRAM9 21 PD# IN OUT IN OUT PWR IN IN OUT IN SDRAM8 OUT 19,30,36 VDD3 PWR 23 24 SDATA SCLK IN IN AGP0 OUT 25 MODE1, 2 48MHz 26 41, 43, 44 40 42 46, 47 48 Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Supply for fixed PLL, 48MHz, AGP0 Input pin for SDRAM buffers. Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output X1 6 8 DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 Mhz reference clock. Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V C P U 1. L a t c h e d i n p u t 2 1, 2 FS0 CPUCLK(0:3) SDRAM12 VDDL AGP (1:2) VDD4 IN OUT IN OUT OUT PWR OUT PWR This asynchronous input halts AGP(1:2) clocks at logic "0" level when input low (in Mobile Mode, MODE=0) Does not affect AGP0 SDRAM clock output This asyncheronous Power Down input Stops the VCO, crystal & internal clocks when active, Low. (In Mobile Mode, MODE=0) SDRAM clock output Supply for SDRAM (0:11), CPU Core, 48MHz clocks, nominal 3.3V. Data input for I2C serial input. Clock input of I2C input Advanced Graphic Port output, powered by VDD4. Not affected by AGP_STOP# Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock for USB timing. Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Feedback SDRAM clock output. Supply for CPU (0:3), either 2.5V or 3.3V nominal Advanced Graphic Port outputs, powered by VDD4. Supply for AGP (0:2) Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9148-36 Mode Pin - Power Management Input Control MODE, Pin 25 (Latched Input) 0 1 Pin 17 Pin 18 Pin 20 Pin 21 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) PCI_STOP# (INPUT) SDRAM 10 (OUTPUT) AGP_STOP# (INPUT) SDRAM 9 (OUTPUT) PD# (INPUT) SDRAM 8 (OUTPUT) Power Management Functionality AGP_STOP# CPU_STOP# PCI_STOP# AGP, CPUCLK Outputs PCICLK (0:5) PCICLK_F, REF, 48MHz and SDRAM Crystal OSC VCO AGP(1:2) 1 0 1 Stopped Low Running Running Running Running Running 1 1 1 Running Running Running Running Running Running 1 1 0 Running Stopped Low Running Running Running Running 0 1 1 Running Running Running Running Running Stopped Low CPU 3.3#_2.5V Buffer selector for CPUCLK drivers. CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD Functionality VDD1, 2, 3, 4 = 3.3V±5%, VDDL = 2.5V ±5% or 3.3 ±5%, TA= 0 to 70°C Crystal (X1, X2) = 14.31818MHz FS2 FS1 FS0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CPU, SDRAM (MHz) 100 95.25 83.3 75 75 68.5 66.8 60 PCI (MHz) 33.3 31.75 33.3 30 37.5 34.25 33.4 30 AG P (MHz) 66.6 63.5 66.6 60 75 68.5 66.8 60 3 R E F, I OA P I C (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 ICS9148-36 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. ICS (Slave/Receiver) The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 4 ICS9148-36 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit Bit 7 Bit 6:4 Bit 3 Bit 2 Bit 1 Bit 0 Description Must be 0 for normal operation 0 - ±0.25% Spread Spectrum Modulation 1 - ±0.6% Spread Spectrum Modulation Bit6 Bit5 Bit4 CPU Clock PCI AGP 111 100 33.3 66.6 110 95.25 31.75 63.5 101 83.3 33.3 66.6 100 75 30 60 011 75 37.5 75 010 68.5 34.25 68.5 001 66.8 33.4 66.8 000 60 30 60 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 6:4 (above) Must be 0 for normal operation 0 - Spread Spectrum center spread type. 1 - Spread Spectrum down spread type. 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs PWD 0 Note1 0 Note: PWD = Power-Up Default 0 I2C is a trademark of Philips Corporation 0 0 Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 41 43 44 PWD 1 X X 1 1 1 1 1 Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description (Reserved) FS2# FS1# SDRAM12 (Act/Inact) (Reserved) CPUCLK2 (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Pin # 7 13 12 11 10 8 PWD X 1 X 1 1 1 1 1 Description CPU3.3#_2.5 PCICLK_F (Act/Inact) FS0# PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0(Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 5 ICS9148-36 Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 34 35 37 38 PWD 1 1 1 1 1 1 1 1 Description SDRAM7 (Act/Inact) SDRAM6 (Act/Inact) SDRAM5 (Act/Inact) SDRAM4 (Act/Inact) SDRAM3 (Act/Inact) SDRAM2 (Act/Inact) SDRAM1 (Act/Inact) SDRAM0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Pin # 47 46 2 PWD 1 1 1 1 1 X 1 1 Pin # 25 - PWD 1 1 1 1 Bit 3 17 1 Bit 2 18 1 Bit 1 Bit 0 20 21 1 1 Description AGP0 (Active/Inactive) (Reserved) (Reserved) (Reserved) SDRAM11 (Act/Inact) (Desktop Mode Only) SDRAM10 (Act/Inact) (Desktop Mode Only) SDRAM9 (Act/Inact) SDRAM8 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. Byte 6: Optional Register for Possible Furture Requirements Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description (Reserved) (Reserved) (Reserved) AGP1 (Act/Inact) (Reserved) MODE AGP2 (Act/Inact) REF0 (Act/Inact) Pin # - PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for futue applications. Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 6 ICS9148-36 CPU_STOP# Timing Diagram CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9148-36. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9148-36. 3. All other clocks continue to run undisturbed. (including SDRAM outputs). 7 ICS9148-36 PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9148-36. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9148-36 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9148. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state. 8 ICS9148-36 Shared Pin Operation Input/Output Pins These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). Pins 2, 7, 8, 25 & 26 on the ICS9148-36 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. Fig. 1 9 ICS9148-36 Fig. 2a Fig. 2b 10 ICS9148-36 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND 0.5 V to VDD +0.5 V 0°C to +70°C 115°C 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; 66.8 MHz Operating IDD3.3OP Supply Current Input frequency Fi VDD = 3.3 V; Input Capacitance1 CIN Logic Inputs CINX X1 & X2 pins Transition Time1 Ttrans To 1st crossing of target Freq. 1 Settling Time Ts From 1st crossing to 1% target Freq. 1 Clk Stabilization TSTAB From VDD = 3.3 V to 1% target Freq. TCPU-PCI1 VT = 1.5 V; f = 66/100 MHz; CPU leads Skew1 TCPU-PCI1 VT = 1.5 V; f = 83/75 MHz; CPU leads TAGP-PCI1 VT = 1.5 V; AGP Leads MIN 2 VSS-0.3 -5 -200 TYP 0.1 2.0 -100 100 MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 160 mA 14.318 27 36 1 1 2.4 3.8 220 5 45 2 2 4 4 500 MHz pF pF ms ms ms ns ns ps 1 Guaranteed by design, not 100% tested in production. Ele ctrical Characte ristics - Input/Supply /Com m on Output Param e te rs T A = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAM ETER Operating Supply Current Skew 1 SYM BOL IDD2 .5 OP CONDITIONS C L = 0 pF; 66.8 M Hz M IN TYP 10 M AX 20 UNITS mA T CPU-PCI1 VT = 1.5 V; f = 66/100 M Hz; CPU leads 1 2.4 4 ns T CPU-PCI1 T AGP-PCI1 VT = 1.5 V; f = 83/75 M Hz; CPU leads VT = 1.5 V; AGP Leads 1 3.8 220 4 500 ns ps 11 ICS9148-36 Electrical Characteristics - CPU TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; C L = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH2A VOL2A IOH2A IOL2A Rise Time tr2A1 Fall Time tf2A1 d t2A1 tsk2A1 tj1s2A1 tjabs2A1 Duty Cycle Skew Jitter, One Sigma Jitter, Absolute 1 CONDITIONS IOH = -28 mA IOL = 27 mA VOH = 2.0 V VOL = 0.8 V MIN 2.5 TYP 2.6 0.35 -29 37 MAX VOL = 0.4 V, VOH = 2.4 V 1.75 2 ns VOH = 2.4 V, VOL = 0.4 V 1.1 2 ns 50 55 % VT = 1.5 V 50 250 ps VT = 1.5 V VT = 1.5 V 65 150 ps 165 250 ps 33 VT = 1.5 V 45 -250 0.4 -23 UNITS V V mA mA Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPU TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH2B IOH = -8 mA Output Low Voltage VOL2B IOL = 12 mA Output High Current IOH2B VOH = 1.7 V Output Low Current IOL2B VOL = 0.7 V tr2B1 VOL = 0.4 V, VOH = 2.0 V Rise Time 2 19 TYP 2.2 0.3 -20 26 MAX 1.5 1.8 1.6 1.8 ns 50 55 % 0.4 -16 UNITS V V mA mA ns Fall Time tf2B Duty Cycle dt2B 1 VT = 1.25 V Skew Jitter, Single Edge Displacement2 Jitter, One Sigma tsk2B1 VT = 1.25 V 60 250 ps tjsed2B1 VT = 1.25 V tj1s2B 1 VT = 1.25 V tjabs2B1 VT = 1.25 V 200 250 ps 65 150 ps 160 250 ps Jitter, Absolute 1 1 MIN 2 VOH = 2.0 V, VOL = 0.4 V 40 -250 Guaranteed by design, not 100% tested in production. Edge displacement of a period relative to a 10-clock-cycle rolling average period. 12 ICS9148-36 Electrical Characteristics - PCI TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; C L = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 41 TYP 3 0.2 -60 50 MAX 0.4 -40 UNITS V V mA mA tr1 1 VOL = 0.4 V, VOH = 2.4 V 1.8 2 ns tf1 1 VOH = 2.4 V, VOL = 0.4 V 1.6 2 ns Duty Cycle d t1 1 VT = 1.5 V 50 55 % Skew tsk1 1 VT = 1.5 V 130 250 ps tj1s1a tj1s1b VT = 1.5 V, synchronous VT = 1.5 V, asynchronous 40 200 150 250 ps ps tab s1a tjabs1b VT = 1.5 V, synchronous VT = 1.5 V, asynchronous 135 500 250 650 ps ps Rise Time Fall Time Jitter, One Sigma Jitter, Absolute 1 SYMBOL VOH1 VOL1 IOH1 IOL1 1 1 45 -250 -650 Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Propagation Delay 1 Skew 1 SYMBOL VOH1 VOL1 IOH1 IOL1 CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 41 TYP 3 0.2 -60 50 MAX UNITS V 0.4 V -40 mA mA Tr1 VOL = 0.4 V, VOH = 2.4 V 1.75 2 ns Tf1 VOH = 2.4 V, VOL = 0.4 V 1.5 2 ns 50 4.2 55 6 % ns 200 500 ps Dt1 Tprop VT = 1.5 V VT = 1.5 V Tsk1 VT = 1.5 V 45 Guaranteed by design, not 100% tested in production. 13 ICS9148-36 Electrical Characteristics - AGP TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V tr1 1 VOL = 0.4 V, VOH = 2.4 V Fall Time tf1 1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle d t1 1 VT = 1.4 V 1 tj1s1 Rise Time 1 SYMBOL VOH1 VOL1 IOH1 IOL1 Skew Jitter, One Sigma1 tsk1 Jitter, Absolute1 tabs1a tjabs1b MIN 2.4 41 TYP 3 0.2 -60 50 MAX 1.1 2 ns 0.4 -40 UNITS V V mA mA 1 2 ns 50 55 % VT = 1.5 V 130 250 ps VT = 1.5 V 2 3 % 2.5 4.5 5 6 % % TYP 2.6 0.3 -32 25 MAX UNITS V V mA mA 45 VT = 1.5 V, synchronous VT = 1.5 V, asynchronous -5 -6 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 48MHz, REF TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; C L = 10 -20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH5 VOL5 IOH5 IOL5 Rise Time tr5 1 VOL = 0.4 V, VOH = 2.4 V 2 4 ns Fall Time 1 VOH = 2.4 V, VOL = 0.4 V 1.9 4 ns 50 57 % Duty Cycle Jitter, One Sigma Jitter, Absolute 1 tf5 d t5 1 1 tj1s5 tjabs5 1 CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 16 VT = 1.5 V 45 VT = 1.5 V VT = 1.5 V -5 Guaranteed by design, not 100% tested in production. 14 0.4 -22 1 3 % - 5 % ICS9148-36 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended. Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01µF ceramic 15 ICS9148-36 Pin 1 Index Area .093 DIA. PIN (Optional) D/2 E/2 PARTING LINE H L DETAIL “A” TOP VIEW BOTTOM VIEW -eA2 C SEE DETAIL “A” -C- A -E- A A1 A2 B C D E e H h L N ∝ SEATING PLANE -DEND VIEW SYMBOL B COMMON DIMENSIONS MIN. NOM. MAX. .095 .102 .110 .008 .012 .016 .087 .090 .094 .008 .0135 .005 .0085 See Variations .291 .295 .299 0.025 BSC .395 .420 .010 .013 .016 .020 .040 See Variations 0° 8° SIDE VIEW VARIATIONS AC MIN. .620 A1 D NOM. .625 N MAX. .630 48 “For current dimensional specifications, see JEDEC 95.” 48 Pin 300 mil SSOP Package Ordering Information ICS9148yF-36 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 16 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.