PRELIMINARY CY28SRC04 PCI-Express Clock Generator Features • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Four 100-MHz differential SRC clocks • 3.3V power supply • Low-voltage frequency select input • I2C support with readback capabilities • 24-pin TSSOP package Pin Configuration Block Diagram XIN XOUT XTAL OSC PLL PLL Ref Freq Divider Network VDD_SRC SRCT[2:1],SRCC[2:1] IREF SDATA SCLK I2C Logic Cypress Semiconductor Corporation Document #: 001-00043 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 20, 2005 PRELIMINARY CY28SRC04 Pin Description Pin No. Name 12 IREF 20 21 Type Description I A precision resistor attached to this pin is connected to the internal current reference. SCLK I, PU SMBus compatible SCLOCK. This pin has an internal pull-up. SDATA I/O, PU SMBus compatible SDATA. This pin has an internal pull-up. 1, 2, 5, 6, 7, 8, SRCT/C[4:1] 23, 24 O, DIF 100-MHz Differential Serial reference clock. 18 I XIN 14.318-MHz Crystal Input 19 XOUT O 14.318-MHz Crystal Output 4, 10, 22 VDD_SRC PWR 3.3V power supply for SRC outputs 3, 9, 11 VSS_SRC GND Ground for SRC outputs 14 VDDA PWR 3.3V Analog Power for PLLs 13 VSSA GND Analog Ground 17 VDD_REF PWR 3.3V power supply for Xtal 16 VSS_REF GND Ground for Xtal 15 NC NC No Connect Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:5) Chip select address, set to ‘00’ to access device (4:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000' Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write 10 18:11 19 27:20 28 36:29 Block Read Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write Acknowledge from slave 10 Acknowledge from slave Command Code – 8 bits 18:11 Command Code – 8 bits Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits 20 Repeat start Acknowledge from slave Data byte 1 – 8 bits Document #: 001-00043 Rev. *A 27:21 28 Slave address – 7 bits Read = 1 Page 2 of 10 PRELIMINARY CY28SRC04 Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 37 45:38 Block Read Protocol Description Bit Acknowledge from slave 29 Data byte 2 – 8 bits 37:30 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N – 8 bits 38 46:39 47 .... Acknowledge from slave .... Stop 55:48 Description Acknowledge from slave Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Byte Read Protocol Description Bit Start 1 Slave address – 7 bits 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Data byte – 8 bits 20 28 Acknowledge from slave 29 Stop 27:21 Repeated start Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0: Control Register 0 Bit @Pup 7 0 Reserved Name Reserved 6 1 SRC[T/C]4 SRC[T/C]4 Output Enable- only for CY28SRC04 0 = Disable (Hi-Z), 1 = Enable 5 1 SRC[T/C]3 SRC[T/C]3 Output Enable- only for CY28SRC04 0 = Disable (Hi-Z), 1 = Enable 4 1 SRC[T/C]2 SRC[T/C]2 Output Enable- only for CY28SRC02 and CY28SRC04 0 = Disable (Hi-Z) 1 = Enable 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable- only for CY28SRC02 and CY28SRC04 0 = Disable (Hi-Z), 1 = Enable 2 1 SRC [T/C]0 SRC[T/C]0 Output Enable- only for CY28SRC01 0 = Disable (Hi-Z), 1 = Enable 1 0 Reserved Reserved Document #: 001-00043 Rev. *A Description Page 3 of 10 PRELIMINARY CY28SRC04 Byte 0: Control Register 0 (continued) Bit @Pup 0 0 Name Reserved Description Reserved Byte 1: Control Register 1 Bit @Pup 7 0 Reserved Name Reserved Description 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Byte 2: Control Register 2 Bit @Pup Name Description 7 1 SRCT/C Spread Spectrum Selection ‘0’ = –0.35% ‘1’ = –0.50% 6 1 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 0 SRC SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on 1 1 Reserved Reserved 0 1 Reserved Reserved Byte 3: Control Register 3 Bit @Pup 7 1 Reserved Name Reserved Description 6 0 Reserved Reserved 5 1 Reserved Reserved 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Byte 4: Control Register 4 Bit @Pup 7 0 Reserved Name Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved Document #: 001-00043 Rev. *A Description Page 4 of 10 PRELIMINARY CY28SRC04 Byte 4: Control Register 4 (continued) Bit @Pup 0 1 Name Reserved Description Reserved Byte 5: Control Register 5 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Byte 6: Control Register 6 Bit @Pup Name Description 7 0 TEST_SEL REF/N or Tri-state Select 1 = REF/N Clock, 0 = Tri-state 6 0 TEST_MODE Test Clock Mode Entry Control 1 = REF/N or Tri-state mode, 0 = Normal operation 5 0 Reserved Reserved 4 1 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 Reserved Reserved 0 1 Reserved Reserved Byte 7: Control Register 7 Bit @Pup 7 0 Name Revision Code Bit 3 Description 6 0 Revision Code Bit 2 5 1 Revision Code Bit 1 4 1 Revision Code Bit 0 3 1 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 12 pF–16 pF 1 mW 7 pF ±50 ppm ±50 ppm 5 ppm Document #: 001-00043 Rev. *A Page 5 of 10 PRELIMINARY Crystal Recommendations The CY28SRC04 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28SRC04 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. CY28SRC04 series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Clock Chip Ci2 C i1 Pin 3 to 6p Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. X2 X1 Cs1 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 27pF Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Figure 1. Crystal Capacitive Clarification Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) Document #: 001-00043 Rev. *A Page 6 of 10 PRELIMINARY CY28SRC04 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDDA Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 – 20 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/W UL-94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level V–0 1 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description VDD_SRC, 3.3V Operating Voltage VDDA Condition 3.3V ± 5% Min. Max. Unit 3.135 3.465 V VILSMBUS Input Low Voltage SDATA, SCLK – 1.0 V VIHSMBUS Input High Voltage SDATA, SCLK 2.2 – V VDD VIL Input Low Voltage VIH Input High Voltage IIL Input Leakage Current Except Pull-ups or Pull downs 0<VIN<VDD VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = 1 mA IOZ High-Impedance Output Current VSS – 0.3 0.8 V 2.0 VDD + 0.3 V –5 5 mA – 0.4 V 2.4 - V –10 10 µA CIN Input Pin Capacitance 3 5 pF COUT Output Pin Capacitance 3 5 pF LIN Pin Inductance VXIH Xin High Voltage VXIL Xin Low Voltage IDD Dynamic Supply Current At max load and frequency IPDD Power Down Supply Current PD asserted, Outputs driven – 70 mA IPDT Power Down Supply Current PD asserted, Outputs Hi-Z - 2 mA Condition Min. Max. Unit – 7 nH 0.7*VDD VDD V 0 0.3*VDD V – 400 mA AC Electrical Specifications Parameter Description Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification 47.5 52.5 % TPERIOD XIN Period When XIN is driven from an external clock source 69.841 71.0 ns TR / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD – 10.0 ns Document #: 001-00043 Rev. *A Page 7 of 10 PRELIMINARY CY28SRC04 AC Electrical Specifications (continued) Parameter Description Condition Min. Max. 45 55 Unit SRC TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX 9.997001 10.00300 % TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns TPERIODAbs 100-MHz SRCT and SRCC Absolute Period Measured at crossing point VOX 10.12800 9.872001 ns TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX 9.872001 10.17827 ns ns TSKEW Any SRCT/C to SRCT/C Clock Skew TSKEW Any SRCS clock to Any SRCS clock Skew Measured at crossing point VOX - 250 ps TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps LACC SRCT/C Long Term Accuracy Measured at crossing point VOX TR / TF SRCT and SRCC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) ∆TR Rise TimeVariation ∆TF Fall Time Variation VHIGH Voltage High Math averages Figure 3 VLOW Voltage Low Math averages Figure 3 –150 – mv VOX Crossing Point Voltage at 0.7V Swing 250 550 mV VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V Measured at crossing point VOX – 250 ps – 300 ppm 175 700 ps – 20 % – 125 ps – 125 ps 660 850 mv VUDS Minimum Undershoot Voltage –0.3 – V VRB Ring Back Voltage See Figure 3. Measure SE – 0.2 V TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps TLTJ Long Term Jitter Measurement at 1.5V@1us - TBD ps Test and Measurement Set-up For Differential SRC Output Signals The following diagram shows the test load configuration for the differential CPU and SRC outputs. 33Ω SRCT 4 9 .9 Ω 33Ω SRCC IR E F 100 Ω M e a s u re m e n t P o in t 2pF 100 Ω 4 9 .9 Ω M e a s u re m e n t P o in t 2pF 475Ω Figure 3. 0.7V Load Configuration Document #: 001-00043 Rev. *A Page 8 of 10 PRELIMINARY CY28SRC04 Ordering Information Part Number Package Type Product Flow Standard CY28SRCZC-04 24-pin TSSOP Commercial, 0° to 70°C CY28SRCZC-04T 24-pin TSSOP—Tape and Reel Commercial, 0° to 70°C Package Diagrams 24-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24 PIN 1 ID 1 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 24 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.25[0.010] BSC 1.10[0.043] MAX. GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 7.70[0.303] 7.90[0.311] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85119-*A Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-00043 Rev. *A Page 9 of 10 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY28SRC04 Document History Page Document Title: CY28SRC04 PCI-Express Clock Generator Document Number: 001-00043 Issue Date Orig. of Change REV. ECN NO. ** 371761 See ECN RGL New Data Sheet *A 384078 See ECN RGL 1) Swap Pin 1 and 2 in Pin Configuration 2) Swap Pin 5 and 6 in Pin Configuration Document #: 001-00043 Rev. *A Description of Change Page 10 of 10