PL IA NT Features S CO M ■ *R oH ■ ■ ■ ■ Applications Lead free device (RoHS compliant*) Protects up to 4 I/O ports Unidirectional configuration ESD protection Low capacitance 3 pF ■ ■ ■ ■ ■ Ethernet – 10/100/1000 Base T Personal digital assistant Handheld electronics Cellular phones Video cards CDNBS08-SLVU2.8-4 – Low Capacitance TVS Array General Information The markets of portable communications, computing and video equipment are challenging the semiconductor industry to develop increasingly smaller electronic components. 8 7 6 5 1 2 3 4 Bourns offers Transient Voltage Suppressor Array combination diodes for surge and ESD protection applications in an 8 Lead Narrow Body SOIC package size format. Bourns Chip Diodes conform to JEDEC standards, are easy to handle on standard pick and place equipment and their flat configuration minimizes roll away. The Bourns device® will meet IEC 61000-4-2 (ESD), IEC 61000-4-4 (EFT) and IEC 61000-4-5 (Surge) requirements. Electrical Characteristics (@ TA = 25 °C Unless Otherwise Noted) Parameter Symbol Min. Nom. Max. Unit Peak Pulse Current (tp = 8/20 µs) I PP 30 A Peak Pulse Power (tp = 8/20 µs)1 PPP 600 W Working Voltage VWM Breakdown Voltage @ 1 mA VBR Leakage Current @ VWM ID Capacitance @ 0 V, 1 MHz C Snapback Voltage 2.8 3.0 V V 1.0 6 µA pF 2.8 V @ IPP = 2 A VC 5.5 V @ IPP = 5 A VC 8.5 V @ IPP = 24 A VC 15 V @ IPP = 30 A VC 21 V Clamping Voltage Note: 1. See Peak Pulse Power vs. Pulse Time. Thermal Characteristics (@ TA = 25 °C Unless Otherwise Noted) Parameter Operating Temperature Storage Temperature Symbol Min. Nom. Max. Unit TJ -55 +25 +150 °C TSTG -55 +25 +150 °C *RoHS Directive 2002/95/EC Jan 27 2003 including Annex. Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. CDNBS08-SLVU2.8-4 – Low Capacitance TVS Array Mechanical Characteristics This is a molded JEDEC Narrow Body SO-8 package with lead free 100 % Sn plating on the lead frame. It weighs approximately 15 mg and has a flammability rating of UL 94V-0. Product Dimensions Recommended Footprint A A B F B H C D G C E DIMENSIONS = MILLIMETERS (INCHES) D Dimensions E Dimensions A 1.143 - 1.397 (0.045 - 0.055) B 0.635 - 0.889 (0.025 - 0.035) A 4.80 - 5.00 (0.189 - 0.196) C B 3.80 - 4.00 (0.150 - 0.157) D 3.937 - 4.191 (0.155 - 0.165) C 5.80 - 6.20 (0.229 - 0.244) E 1.016 - 1.27 (0.040 - 0.050) D 1.35 - 1.75 (0.054 - 0.068) E 0.10 - 0.25 (0.004 - 0.008) F 0.25 - 0.50 (0.010 - 0.019) G 0.40 - 1.250 (0.016 - 0.049) H 0.18 - 0.25 (0.007 - 0.009) How To Order CD NBS08 - SLVU 2.8 - 4 Common Code CD = Chip Diode Package NBS08 = Narrow Body SOIC8 Package Model SLVU = Low Capacitance TVS Array Working Peak Reverse Voltage 2.8 = 2.8 VRWM (Volts) Number of Diodes Typical Part Marking CDNBS08-SLVU2.8-4 .......................................................... 6.223 Min. (0.245) SL4 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. CDNBS08-SLVU2.8-4 – Low Capacitance TVS Array Packaging The surface mount product is packaged in a 8 mm x 4 mm Tape and Reel format per EIA-481 standard. TOP SIDE VIEW (INTO COMPONENT POCKET) 4.0 ± 0.1 (.16 ± .004) 0.3 ± 0.05 (.01 ± .002) 1.5 ± 0.1/-0 (.06 ± .004/-0) DIA. 2.0 ± 0.05 (.08 ± .002) R 1.75 ± 0.1 (.07 ± .004) 0.3 MAX. (0.01) 12.0 ± 0.3 (.47 ± .01) 2.1 ± 0.1 (.083 ± .004) 5.5 ± 0.3 (.22 ± .01) 6.4 ± 0.1 (.252 ± .004) 9.0 ± 0.1 (.354 ± .004) 8.0 ± 0.3 (.31 ± .01) ORIENTATION OF COMPONENT IN POCKET R 0.25 TYP. (0.010) BACKSIDE FACING UP Block Diagram 8 1 Device Pinout 7 2 6 3 5 4 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. Pin 1 2 3 4 5 6 7 8 Unidirectional Common Mode Line 1 GND Line 3 GND Line 4 GND Line 2 GND Bidirectional Common Mode Line 1 GND GND Line 2 Line 2 GND GND Line 1 Bidirectional Differential Mode Line Pair 1 Line Pair 1 Line Pair 2 Line Pair 2 Line Pair 2 Line Pair 2 Line Pair 1 Line Pair 1 CDNBS08-SLVU2.8-4 – Low Capacitance TVS Array Performance Graphs Peak Pulse Power vs Pulse Time Pulse Wave Form 120 IPP – Peak Pulse Current (% of IPP) PPP – Peak Pulse Current (W) 10,000 600 W, 8/20 µs Waveform 1,000 100 Test Waveform Parameters tt = 8 µs td = 20 µs tt 100 80 et 60 40 td = t|IPP/2 20 0 10 0.01 1 10 100 1,000 10,000 0 5 10 15 20 25 t – Time (µs) td – Pulse Duration (µs) Power Derating Curve % of Rated Power 100 Peak Pulse Power 8/20 µs 80 60 40 20 Average Power 0 0 25 50 75 100 125 150 TL – Lead Temperature (°C) Reliable Electronic Solutions Asia-Pacific: Tel: +886-2 2562-4117 • Fax: +886-2 2562-4116 Europe: Tel: +41-41 768 5555 • Fax: +41-41 768 5510 The Americas: Tel: +1-951 781-5500 • Fax: +1-951 781-5700 www.bourns.com REV. 05/06 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. 30