Si9169 Vishay Siliconix High Frequency 1-A Synchronous Buck/Boost Converter FEATURES D D D D Voltage Mode Control Fully Integrated MOSFET Switches 2.7-V to 6-V Input Voltage Range Programmable PWM/PSM Control − Up to 1-A Output Current @ 3.6 V in PWM − Up to 2-MHz Adjustable Switching Frequency in PWM − Less than 200-mA Quiescent Current in PSM D D D D Integrated UVLO and POR Integrated Soft-Start Synchronization Shutdown Current <1 mA DESCRIPTION The Si9169 provides fully integrated synchronous buck or boost converter solution for the latest one cell Lithium Ion cellular phones. Capable of delivering up to 1 A of output current at +3.6 V, the Si9169 provides ample power for various baseband circuits as well as for some PAs. It combines the 2-MHz switching controller with fully integrated high-frequency MOSFETs to deliver the smallest and most efficient converter available today. The 2-MHz switching frequency reduces the inductor height to new level of 2 mm and minimizes the output capacitance requirement to less than 10 mF with peak-to-peak output ripple as low as 10 mV. Combined with low-gate charge high-frequency MOSFETs, the Si9169 delivers efficiency up to 95%. The programmable pulse skipping mode maintains this high efficiency even during the standby and idle modes to increase overall battery life and talktime. In order to extract the last ounce of power from the battery, the Si9169 is designed with 100% duty cycle control for buck mode. With 100% duty cycle, the Si9169 operates like a saturated linear regulator to deliver the highest potential output voltage for longer talktime. Si9169 can be a drop-in replacement of Si9165 provided Pin 1 is not connected. For full 1A load condition, Pin 1 is required to be connected to low power controller ground. The Si9169 is available in both standard and lead (Pb)-free TSSOP-20 pin package. In order to satisfy the stringent ambient temperature requirements, the Si9169 is rated to handle the industrial temperature range of −25_C to 85_C and −40_C to 85_C. FUNCTIONAL BLOCK DIAGRAM INPUT 2.7 X 6 V OUTPUT 0X1A INPUT 2.7 X 6 V VDD COIL VO MODE VS VIN/OUT FB VS VIN/OUT COIL SYNC PGND ROSC REF GND Boost Configuration Document Number: 70945 S-40695—Rev. D, 19-Apr-04 OUTPUT 0X1A PGND VDD MODE FB COMP SHUTDOWN COMP PWM/PSM VO SHUTDOWN ROSC PWM/PSM REF SYNC PGND GND Buck Configuration www.vishay.com 1 Si9169 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Voltages Referenced to GND Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Power Dissipation (Package)a MODE, PWM/PSM, SYNC, SD, VREF, ROSC COMP, FB . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD +0.3 V VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VS +0.3 V PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "0.3 V Voltages Referenced to PGND VS, VIN/OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V COIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.4 V to VIN/OUT +0.4 V Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A for 1 ms Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150_C 20-Pin TSSOP (Q Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W Thermal Impedance (ΘJA) 20-Pin TSSOPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90_C/W Operating Temperature Range Si9169BQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 to 85_C Si9169DQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to 85_C Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 11 mW/_C above 60_C. c. With Pin 1 connected to GND plane. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Voltages Referenced to GND VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V Fosc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 kHz to 2 MHz MODE, PWM/PSM, SYNC, SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VDD Rosc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kW to 300 kW Voltages Referenced to PGND VREF Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF VS, VIN/OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V SPECIFICATIONS Test Conditions Unless Otherwise Specified Parameter Symbol Limitse 2.7 V < VDD < 6V, VIN/OUT = 3.3 V, VS = 3.3 V Mina Typb Maxa IREF = 0 1.265 1.3 1.330 TA = 25°C, IREF = 0 1.280 1.3 1.320 Unit Reference Output Voltage Load Regulation Power Supply Rejection VREF DVREF VDD = 3.3 V, −500 µA < IREF <0 PSRR V 3 mV 60 dB UVLO Under Voltage Lockout (turn-on) Hysteresis VUVLOLH VHYS 2.3 VUVLOLH − VUVLOHL 2.4 2.5 0.1 V Soft-Start Time SS time tss 6 ms MODE Logic High VIH Logic Low VIL Input Current 0.7 VDD 0.3 VDD IL −1.0 Logic High VIH 2.4 Logic Low VIL 1.0 V mA SD, SYNC, PWM/PSM Input Current www.vishay.com 2 IL 0.8 −1.0 1.0 V mA Document Number: 70945 S-40695—Rev. D, 19-Apr-04 Si9169 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Otherwise Specified Symbol Parameter Limitse 2.7 V < VDD < 6V, VIN/OUT = 3.3 V, VS = 3.3 V Mina Nominal 1.60 MHz, ROSC = 30 kW −20 Typb Maxa Unit Oscillator Maximum Frequency FMAX Accuracy 2 Max Duty Cycle (Buck, (Buck Non LDO Mode) DMAX Fsw = 2 MHz Max Duty Cycle (Boost) Si9169BQ 75 85 Si9169DQ 73 85 Si9169BQ 52 65 50 65 Si9169DQ SYNC Range MHz 20 FSYNC/FOSC 1.2 SYNC Low Pulse Width 50 SYNC High Pulse Width 50 % 1.5 ns SYNC tr, tf 50 Error Amplifier Input Bias Current IBIAS Open Loop Voltage Gain AVOL FB Threshold VFB Unity Gain BW BW Output Current IEA VFB = 1.5 V TA = 25_C −1 1 mA 50 60 dB 1.270 1.30 1.330 1.255 1.30 1.340 2 Source (VFB = 1.05 V), VCOMP = 0.75 V −3 Sink (VFB = 1.55 V), VCOMP = 0.75 V 1 Boost Modec VOUT v 4.2 V 1000 Buck Moded 1.8 V v VOUT v 5.0 V 1000 VIN = 3.3 V, VOUT = 3.6 V 150 VIN = 3.6 V, VOUT = 2.7 V 150 V MHz −1 mA 3 Output Current Output Current (PWM) Output Current (PSM) Boost Modec IOUT Buck Moded rDS(on) N-Channel rDS(on) P-Channel rDS(on) DS( ) VS w 3.3 33V mA 130 300 160 330 mW Over Temperature Protection Trip Point Rising Temperature Hysteresis 165 °C 25 Supply Current Normal Mode PSM Mode Shutdown Mode IDD VDD = 3.3 V, FOSC = 2 MHz 500 750 VDD = 3.3 V 180 250 VDD = 3.3 V, SD = 0 V mA 1 Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. VIN = VDD, VOUT = VIN/OUT = VS = VO, L = 1.5 mH, VIN v VOUT d. VIN = VDD = VS = VIN/OUT, VOUT = VO, L = 1.5 mH, VIN w VOUT e. Limits are for both Si9169BQ (−25_C to 85_C) and Si9169DQ (−40_C to 85_C) unless otherwise noted. Document Number: 70945 S-40695—Rev. D, 19-Apr-04 www.vishay.com 3 Si9169 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) VREF vs. VDD 1.310 1.31 V REF (V) 1.305 V REF (V) VREF vs. Temperature 1.32 1.300 1.295 1.30 1.29 1.290 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.28 −50 6.0 0 50 VDD − (V) 150 Temperature (_C) Frequency vs. Temperature 2.00 100 Frequency vs. ROSC 10000 1.95 1.90 Frequency (kHz) Frequency (MHz) ROSC = 25 kW 1.85 1.80 1000 1.75 1.70 −100 100 −50 0 50 100 10 150 100 Temperature (_C) Boost Mode Efficiency, VO = 3.6 V 95 95 PSM−3.6 V 85 PSM−4.2 V PWM−3.6 V 75 PWM−4.2 V 70 PWM−2.7 V PSM−2.7 V 80 75 70 65 65 60 60 1 10 100 Load Current (mA) www.vishay.com 4 PSM−3.3 V 85 PWM−3 V 80 PWM−3.3 V 90 PSM−3 V 90 Efficiency (%) Efficiency (%) ROSC (kW) Buck Mode Efficiency, VO = 2.7 V 100 1000 1000 1 10 100 1000 Load Current (mA) Document Number: 70945 S-40695—Rev. D, 19-Apr-04 Si9169 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) PWM Supply Current PSM Supply Current 800 250 700 200 I DD ( mA) I DD ( mA) 600 500 150 400 100 300 200 50 2 3 4 5 6 2 7 3 4 VDD − (V) 5 6 7 VDD − (V) PIN CONFIGURATION AND ORDERING INFORMATION TSSOP-20 GND SD PWM/PSM VIN/OUT VIN/OUT VIN/OUT SYNC GND VREF FB 1 2 3 4 5 6 7 8 9 10 Si9169 20 19 18 17 16 15 14 13 12 11 COIL COIL MODE PGND PGND VS VO VDD ROSC COMP ORDERING INFORMATION Part Number Temperature Range Si9169BQ-T1 Si9169BQ-T1—E3 Si9169DQ-T1 Si9169DQ-T1—E3 Package −25 25 to 85_C Tape and Reel −40 40 to 85_C Top View PIN DESCRIPTION Pin Symbol 1 GND 2 SD Description Low power controller ground. Can be left unconnected for load currents below 600 mA. Shuts down the IC completely and decreases current consumed by the IC to <1 mA. 3 PWM/PSM 4, 5, 6 VIN/OUT Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification is disabled. 7 SYNC Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not used, the pin must be connected to VDD , or logic high. 8 GND Low power controller ground 9 VREF 1.3-V reference. Decoupled with 0.1-mF capacitor. 10 FB 11 COMP 12 Rosc External resistor to determine the switching frequency. 13 VDD Input supply voltage for the analog circuitry. Input voltage range is 2.7 V to 6 V. 14 VO Direct output voltage sensing to control peak inductor current in PSM mode. Supply voltage for the internal MOSFET drive circuit. Input node for buck mode and output node for boost mode. Output voltage feedback connected to the inverting input of an error amplifier. Error amplifier output for external compensation network. 15 VS 16, 17 PGND Power ground. 18 MODE Determines the converter topology. Connect to AGND for buck or VDD for boost. 19, 20 COIL Document Number: 70945 S-40695—Rev. D, 19-Apr-04 Inductor connection node www.vishay.com 5 Si9169 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM VDD SD VS VIN/OUT Positive Supply Reference Threshold Generator Soft-Start Timer UVLO POR Bias Generator OTP VREF FB COMP PWM Modulator 1.0 V Ramp SYNC 0.5 V PWM/PSM Select Oscillator ROSC PSMEN COSC P PWMIN PWMEN COIL Drivers N PSMIN PSM Modulator VO PWM/PSM MODE Negative Return and Substrate GND PGND DETAIL OPERATIONAL DESCRIPTION Start-Up The UVLO circuit prevents the internal MOSFET switches and oscillator circuit from turning on, if the voltage on VDD pin is less than 2.5 V. With typical UVLO hysteresis of 0.1 V, controller is continuously powered on until the VDD voltage drops below 2.4 V. This hysteresis prevents the converter from oscillating during the start-up phase and unintentionally locking up the system. Once the VDD voltage exceeds the UVLO threshold, and with no other shutdown condition detected, an internal Power-On-Reset timer is activated while most circuitry, except the output driver, are turned on. After the POR timeout of about 1 ms, the internal soft-start capacitor is allowed to charge. When the soft-start capacitor voltage reaches 0.5 V, the PWM circuit is enabled. Thereafter, the constant current charging the soft-start capacitor will force the output voltage to rise gradually without overshooting. To prevent negative undershoot, the synchronous switch is tri-stated until the duty www.vishay.com 6 cycle reaches about 10%. In tri-state, the high-side p-channel MOSFET is turned off by pulling up the gate voltage to VS potential. The low-side n-channel MOSFET is turned off by pulling down the gate voltage to PGND potential. Note that the Si9169 will always soft starts in the PWM mode regardless of the voltage level on the PWM/PSM pin. Shutdown The Si9169 is designed to conserve as much battery life as possible by decreasing current consumption of IC during normal operation as well as the shutdown mode. With logic low level on the SD pin, current consumption of the Si9169 is decreased to less than 1 mA by shutting off most of the circuits. The logic high enables the controller and starts up as described in “Start-Up” section above. Document Number: 70945 S-40695—Rev. D, 19-Apr-04 Si9169 Vishay Siliconix Over Temperature Protection The Si9169 is designed with over temperature protection circuit to prevent MOSFET switches from running away. If the temperature reaches 165_C, internal soft-start capacitor is discharged, shutting down the output stage. Converter remains in the disabled mode until the temperature in the IC decreases below 140_C. The maximum duty cycle under boost mode is internally limited to 75% to prevent inductor saturation. If the converter is turned on for 100% duty cycle, inductor never gets a chance to discharge its energy and eventually saturates. In boost mode, synchronous rectifier is always turned on for minimum or greater duration as long as the switch has been turned on. The controller will deliver 0% duty cycle, if the input voltage is greater than the programmed output voltage. Because of signal propagation time and MOSFET delay/rise/fall time, controller will not transition smoothly from minimum controllable duty cycle to 0% duty cycle. For example, controller may decrease its duty cycle from 5% to 0% abruptly, instead of gradual decrease you see from 75% to 5%. PWM Mode With PWM/PSM mode pin in logic high condition, the Si9169 operates in constant frequency (PWM) mode. As the load and line varies, switching frequency remain constant. The switching frequency is programmed by the Rosc value as shown by the Oscillator curve. In the PWM mode, the synchronous drive is always enabled, even when the output current reaches 0 A to assure the converter is operating in continuous current mode. In continuous current mode, transfer function of the converter remain constant, providing fast transient response. If the converter operates in discontinuous current mode, overall loop gain decreases and transient response time can be ten times longer than if the converter remain in continuous current mode. This transient response time advantage can significantly decrease the hold-up capacitors needed on the output of dc-dc converter to meet the transient voltage regulation. Therefore, the PWM/PSM pin is available to dynamically program the controller. The maximum duty cycle of the Si9169 can reach 100% in buck mode. This allows the system designers to extract out the maximum stored energy from the battery. Once the controller delivers 100% duty cycle, converter operates like a saturated linear regulator. At 100% duty cycle, synchronous rectification is completely turned off. Up to a maximum duty cycle of 80% at 2-MHz switching frequency, controller maintains perfect output voltage regulation. If the input voltage drops below the level where the converter requires greater than 80% duty cycle, controller will deliver 100% duty cycle. This instantaneous jump in duty cycle is due to fixed BBM time, MOSFET delay/rise/fall time, and the internal propagational delays. In order to maintain regulation, controller might fluctuate its duty cycle back and forth from 100% to something less than maximum duty cycle while the converter is operating in this input voltage range. If the input voltage drops further, controller will remain on 100%. If the input voltage increases to a point where it requires less than 80% duty cycle, synchronous rectification is once again activated. Document Number: 70945 S-40695—Rev. D, 19-Apr-04 Pulse Skipping Mode The gate charge losses produced from the Miller capacitance of MOSFETs are the dominant power dissipation parameter during light load (i.e. < 10 mA). Therefore, less gate switching will improve overall converter efficiency. This is exactly why the Si9169 is designed with pulse skipping mode. If the PWM/PSM pin is connected to logic low level, converter operates in pulse skipping modulation (PSM) mode. During the pulse skipping mode, quiescent current of the controller is decreased to approximately 200 mA, instead of 500 mA during the PWM mode. This is accomplished by turning off most of internal control circuitry and utilizing a simple constant on-time control with feedback comparator. The controller is designed to have a constant on-time and a minimum off-time acting as the feedback comparator blanking time. If the output voltage drops below the desired level, the main switch is first turned on and then off. If the applied on-time is insufficient to provide the desired voltage, the controller will force another on and off sequence, until the desired voltage is accomplished. If the applied on-time forces the output to exceed the desired level, as typically found in the light load condition, the converter stays off. The excess energy is delivered to the output slowly, forcing the converter to skip pulses as needed to maintain regulation. The on-time and off-time are set internally based on inductor used (1.5-mH Typical), Mode pin selection and maximum load current. Wide duty cycle range can be achieved in both buck and boost configurations. In pulse skipping mode, synchronous rectifier drive is also disabled to further decrease the gate charge loss, which in turn improves overall converter efficiency. Reference The reference voltage of the Si9169 is set at 1.3 V. The reference voltage is internally connected to the non-inverting inputs of the error amplifier. The reference is decoupled with 0.1-mF capacitor. www.vishay.com 7 Si9169 Vishay Siliconix Error Amplifier The error amplifier gain-bandwidth product and slew rate is critical parameters which determines the transient response of converter. The transient response is function of both small and large signal response. The small signal is the converter closed loop bandwidth and phase margin while the large signal is determined by the error amplifier dv/dt and the inductor di/dt slew rate. Besides the inductance value, error amplifier determines the converter response time. In order to minimize the response time, the Si9169 is designed with 2-MHz error amplifier gain-bandwidth product to generate the widest converter bandwidth and 3.5 V/msec slew rate for ultra-fast large signal response. Oscillator The oscillator is designed to operate up to 2-MHz minimal. The 2-MHz operating frequency allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. Even with 2-MHz switching frequency, quiescent current is only 500 mA with unique power saving circuit design. The switching frequency is easily programmed by attaching a resistor to ROSC pin. See oscillator frequency versus ROSC curve to select the proper values for desired operating frequency. The tolerance on the operating frequency is "20% with 1% tolerance resistor. Synchronization The synchronization to external clock is easily accomplished by connecting the external clock into the SYNC pin. A logic www.vishay.com 8 high to low transition synchronizes the clock. The external clock frequency must be within 1.2 to 1.5 times the internal clock frequency. Break-Before-Make Timing A proper BBM time is essential in order to prevent shoot-through current and maintain high efficiency. The break-before-make time is set internally at 20 ns @ VS = 3.6 V. The high and low-side MOSFET drain voltages are monitored and when the drain voltage reaches the 1.75 V below or above its initial starting voltage, 20 ns BBM time is set before the other switch turns on. The maximum controllable duty cycle is limited by the BBM time. Since the BBM time is fixed, maximum controllable duty cycle will vary depending on the switching frequency. Output MOSFET Stage The high- and low-side switches are integrated to provide optimum performance and to minimize the overall converter size. Both, high and low-side switches are designed to handle up to 1 A of continuous current. The MOSFET switches were designed to minimize the gate charge loss as well as the conduction loss. For the high frequency operation, switching losses can exceed conduction loss, if the switches are designed incorrectly. Under full load, efficiency of 90% is accomplished with 3.6-V battery voltage in both buck and boost modes (+2.7-V output voltage for buck mode and +5-V output voltage for boost mode). Document Number: 70945 S-40695—Rev. D, 19-Apr-04