www.fairchildsemi.com TMC22071A Genlocking Video Digitizer Features Description • • • • • • The TMC22071A Genlocking Video Digitizer converts standard baseband composite NTSC or PAL video into 8-bit digital composite video data. It extracts horizontal and vertical sync signals and generates a pixel clock for the on-board 8-bit A/D converter and a 2x clock for the transfer of data to subsequent video processing decoding or encoding with the TMC22x5y Video Decoder or TMC22x9x Digital Video Encoder family. It also measures the color subcarrier phase and frequency and provides this data to the Encoder (for genlocked color NTSC or PAL encoding), or a frame buffer (for frame capture) over the digital composite video port. • • • • • Fully integrated acquisition 3-channel video input multiplexer Two-stage video clamp Automatic gain adjustment Sync detection and separation Pixel and subpixel adjustment of HSYNC-to-Video timing Genlock to NTSC or PAL inputs Clock generation 8-bit video A/D converter Microprocessor interface Line-locked pixel rates - 12.27 MHz NTSC - 13.5 MHz NTSC or PAL Direct interface to TMC22x9x encoders Built-in circuitry for crystal oscillator No tuning or external voltage reference required 68 Lead PLCC or 100 Lead MQFP package Applications The TMC22071A includes a three-channel video input multiplexer, analog clamp, variable gain amplifier, and digital back porch clamp. The on-board oscillator circuitry generates the clock from a 20 MHz crystal or the clock source may be an external oscillator. It is programmable over a microprocessor interface for NTSC or PAL operation. No external component changes and no production tuning or service adjustments are ever required. • Frame grabber • Digital VCR/VTR • Desktop video The TMC22071A is fabricated in an advanced CMOS process, and is packaged in a 68 Lead PLCC or 100 Lead MQFP. Its performance is guaranteed from 0°C to 70°C. • • • • Block Diagram BACK PORCH CLAMP DATA SELECTOR CVBS7-0 ANALOG CLAMP GAIN SUBCARRIER PHASE-LOCKED LOOP A/D VIN3 LOWPASS FILTER D/A SYNC SEPARATOR GVSYNC GHSYNC D/A EXT PXCK DDS/PIXEL CLOCK INTERFACE CBYP DDS OUT CLK IN RT RB ANALOG INTERFACE HORIZONTAL PHASE-LOCKED LOOP PXCK SEL MICROPROCESSOR INTERFACE COMP VREF A0 CS R/W INT RESET D0 +1.2V CLK OUT DIRECT DIGITAL SYNTHESIZER CONTROL PFD IN VIN2 MUX VIN1 PXCK LDV VALID 65-22071-01 Rev. 1.0.5 TMC22071A Functional Description The TMC22071A is a fully-integrated genlocking video A/D converter which digitizes NTSC or PAL baseband composite video under program control. It accepts video on three selectable input channels, adjusts gain, clamps to the back porch, and digitizes the video at a multiple of the horizontal line frequency. It extracts horizontal and vertical sync, measures the subcarrier frequency and phase (relative to the sampling clock), and provides the data along with digital composite video data over an 8-bit digital video port. Two sync outputs (GHSYNC and GVSYNC) are also provided. It generates 1x (LDV) and 2x (PXCK) pixel clocks for data transfer. PXCK also serves as a master clock for the companion TMC22x9x Encoders and TMC22x5y decoders. Operating parameters are set up via a serial microprocessor port. Internal or external voltage reference operation is available Timing The TMC22071A operates from an internally-synthesized clock, PXCK, which runs at twice the pixel data rate. The nominal pixel rates may be set to 12.27 Mpps for NTSC and 13.5 Mpps for NTSC and PAL. Customers requiring 14.75 or 15 Mpps PAL operation should consult factory. Video Input Three high-impedance video inputs are selected by an internal multiplexer under host processor control. The device accepts industry-standard video levels of 1.23 Volts (sync tip to peak color = 1 volt sync tip to reference white). Good channel-to-channel isolation allows active video on all three inputs simultaneously. Antialiasing filtering (if used) and line termination resistors must be provided externally. The input selection is controlled by two bits in the Control Register. Analog Clamp The front-end analog clamp ensures that the input video falls within the active range of the A/D converter. The digitized composite video output can be clamped to the back porch by a secondary digital clamp. Automatic Gain Adjustment Since video signals may vary substantially from nominal levels, the TMC22071A performs an automatic level setting routine to establish correct signal amplitudes for digitizing. The TMC22071A relies upon the presence of the sync tip-to-back porch voltage to determine the gain required for the input video signal. Sync tip compression or clipping is often affected by APL (Average Picture Level) variation. Rather than tracking minor variations in sync tip amplitude and constantly adjusting video gain, the TMC22071A establishes proper signal 2 PRODUCT SPECIFICATION amplitudes during initial genlock acquisition, and then (optionally) holds the gain constant. This results in a stable picture under variable signal conditions. Improperly terminated or weak video signals are handled in the TMC22071A by a selectable gain of +1.0 or +1.5. The higher gain can amplify a doubly-terminated signal which is reduced in amplitude by 2/3. If the input signal levels are well controlled, the automatic gain adjustment can be disabled and the gain held at its nominal value (unity or 1.5X). Analog-to-Digital Converter The TMC22071A contains a high-performance 8-bit A/D converter. Its gain and offset are automatically set as a part of the automatic gain adjustment process during initial signal acquisition, and require no user attention. The reference voltages to the A/D converter are set up by internal D/A converters under automatic control during genlock acquisition. These voltages determine the gain and offset of the A/D converter with respect to the video level presented at its input. Low-Pass Filter The digitized composite video stream is digitally low-pass filtered to remove chrominance components from the sync separator. Filtering provides robust operation by optimizing the signal-to-noise ratio of the synchronizing/blanking portion of the video, improving the accuracy of the back porch blanking level detector. A digital sync separator provides the output sync signals, GHSYNC and GVSYNC, and times internal operations. Horizontal Phase-Locked Loop A phase-locked loop generates PXCK, at twice the pixel rate. The reference signal for the horizontal phase-locked loop is generated by the Direct Digital Synthesizer (DDS). The DDS output is constructed with an internal D/A converter and is output from the TMC22071A via the DDS OUT pin. This signal is passed through an external LC filter and input to the horizontal phase-comparator. The frequency of the DDS output is one ninth of that of PXCK. A 20 MHz clock is required to drive the DDS. Preferably, this may be input to the TMC22071A via CMOS levels on the CLK IN pin. Alternately, a 20 MHz crystal may be directly connected between CLK IN and CLK OUT with tuning capacitors to activate the internal crystal oscillator circuitry. If incoming video is lost or disconnected after the TMC22071A has acquired and locked, PXCK, GHSYNC, PRODUCT SPECIFICATION TMC22071A GVSYNC and GRS data will continue. The GRS data will be the initial subcarrier frequency and phase values selected by the Format select bits of the Control Register. The TMC22071A will acquire and lock to incoming video within two frames after video is restored. Subcarrier Phase-Locked Loop A fully-digital phase-locked loop is used to extract the phase and frequency of the incoming color burst. These frequency and phase values are output over the CVBS bus during the horizontal sync period. Fairchild’s video decoder and genlockable encoder chips will accept these data directly. Back Porch Digital Clamp A digital back-porch clamp is employed to ensure a constant blanking level. It digitally offsets the data from the A/D converter to set the back porch level to precisely 3Ch for NTSC and 40h for PAL. When the digital clamp is enabled, the CVBS video output data is determined from the A/D conversion result minus the back porch level + 3Ch (40h for PAL). Digitized Video Output Subcarrier frequency, subcarrier phase, and Field ID data (GRS) are transmitted in 4-bit nibbles over CVBS3-0 during the horizontal sync tip period at the PXCK rate. Microprocessor Interface Since microprocessor buses are notoriously noisy from a wide-band analog point of view, the microprocessor interface bus is only one bit wide, rather than the more customary eight. The operation of this bus is similar to other buscontrolled devices except that the TMC22071A internal Control Register is accessed one bit at a time. A sequence of 47 bits is written to or read from the LSB of a standard microprocessor port. Writing to or reading from the secondary address results in the transfer of data to or from the internal shift register. The RESET input, when LOW, sets all internal state machines to their initialized conditions. Returning the RESET pin HIGH starts the signal acquisition sequence which lasts until locking with the gain-adjusted and clamped video signal is achieved. The digitized 8-bit video output is provided over an 8-bit wide CVBS data port, synchronous with PXCK and LDV. Pin Assignments 1 68 65-22071-02 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Name VDD CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 VDD DGND CVBS5 CVBS6 CVBS7 GHSYNC GVSYNC VALID DGND DGND LDV Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name VDD PXCK DGND DGND VDD VDDA AGND VDDA VDDA AGND RB VIN3 VDDA VIN2 AGND VDDA VIN1 Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Name AGND RT AGND VREF AGND VDDA AGND CBYP PFD IN AGND DDS OUT PXCK SEL VDDA COMP AGND DGND CLK IN Pin 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Name VDD CLK OUT EXT PXCK DGND DGND DGND VDD VDD A0 R/W CS VDD RESET DGND D0 INT DGND 3 TMC22071A PRODUCT SPECIFICATION Pin Assignments (continued) 80 51 81 50 100 31 1 30 Notes: 1. NC = Do Not Connect. * These pins are not connected in the TMC22071A. However, you should connect these pins as shown for compatibility with future genlock ICs. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16* 17 18 19 20 21 22 23 24 25 Name A0 NC NC R/W CS VDD RESET DGND D0 NC NC NC NC NC NC DGND INT VDD NC NC CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41* 42* 43 44 45 46 47 48 49 50 Name VDD DGND CVBS5 CVBS6 CVBS7 NC GHSYNC GVSYNC VALID NC NC NC DGND DGND LDV DGND VDD NC VDD PXCK DGND DGND VDD VDDA AGND Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name VDDA VDDA NC NC AGND NC RB VIN3 NC VDDA VIN2 NC AGND VDDA VIN1 NC AGND RT AGND VREF NC AGND VDDA AGND CBYP Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name NC PFD IN NC NC NC AGND DDS OUT NC NC NC PXCK SEL VDDA COMP AGND DGND CLK IN VDD CLK OUT EXT PXCK DGND DGND DGND VDD NC VDD 65-22071-02B Pin Definitions Pin Number 68 pin PLCC 100 pin MQFP 34, 31, 29 CLK IN Pin Name Pin Type Function 65, 61, 58 1.23Vp-p Composite Video Input. Video inputs,1.25 Volts peak-to-peak, sync tip to peak color 51 91 CMOS 20 MHz DDS clock input. 20 MHz CMOS clock input to DDS. This pin may also be used along with CLK OUT for directly connecting crystals. CLK OUT 53 93 CMOS Inverted clock output. Inverted DDS clock output. This pin may also be used along with CLK IN for directly connecting a crystal. PXCK 19 45 CMOS 2x Pixel clock output. 2x oversampled line-locked clock output. LDV 17 40 CMOS Pixel clock output. Delayed pixel clock output. LDV runs at 1/2 the rate of PXCK and its rising edge is useful for transferring CVBS digital video from the TMC22071A to the TMC22x9x Digital Video Encoders. EXT PXCK 54 94 CMOS External PXCK input. Input for external PXCK clock source. PXCK SEL 46 86 CMOS PXCK source select. Select input for internal or external PXCK. When HIGH, the internally generated line-locked PXCK is selected. When LOW, the external PXCK source is enabled. Video Input VIN1-3 Clocks 4 TMC22071A PRODUCT SPECIFICATION Pin Definitions (continued) Pin Number Pin Name 68 pin PLCC 100 pin MQFP Pin Type Function Digital Video GHSYNC 12 32 CMOS Horizontal sync output. When the TMC22071A is locked to incoming video, the GHSYNC pin provides a negative-going pulse after the falling edge of the horizontal sync pulse. There is a fixed number of PXCK clock cycles between adjacent falling edges of GHSYNC, except following a VCR headswitch. GVSYNC 13 33 CMOS Vertical sync output. When the TMC22071A is locked to incoming video, the GVSYNC pin provides a negative-going edge after the start of the first vertical sync pulse of a vertical blanking interval. CVBS7-0 11-9, 62 30-28, 25-21 CMOS Composite output bus. 8-bit composite video data is output on this bus at 1/2 the PXCK rate. During horizontal sync, field ID, subcarrier frequency, and subcarrier phase are available on this bus. D0 66 9 TTL Data l/O port. Microprocessor data port. All control parameters are loaded into and read back from the Control Register over this 1-bit bus. A0 60 1 TTL mP port control. Microprocessor address bus. A LOW on this input loads the l/O Port Shift Register with data from D0 and CS. A HIGH transfers the l/O Port Shift Register contents into the Control Register on the last falling edge of CS. CS 62 5 TTL Chip select. When CS is HIGH, D0 is in a high-impedance state and ignored. When CS is LOW, the microprocessor can read or write D0 data into the Control Register. RESET 64 7 TTL Master reset input. Bringing RESET LOW forces the internal state machines to their starting states, loads the Control Register with default values, and disables outputs. Bringing RESET HIGH restarts the TMC22071A in its default mode. R/W 61 4 TTL Bus read/write control. When R/W and A0 are LOW, the microprocessor can write to the Control Register over D0. When R/W is HIGH and A0 is LOW, the contents of the Status Register are read over D0. INT 67 17 TTL Interrupt output. This output is LOW if the internal horizontal phase lock loop is unlocked with respect to incoming video for 128 or more lines per field. After lock is established, INT goes HIGH. VALID 14 34 TTL HSYNC locked flag. This output, when HIGH indicates that incoming horizontal sync has been detected within the ±16 pixel window in time established by previous sync pulses. When LOW, it indicates that incoming horizontal sync has not been found within the expected time frame. VALID will toggle if the time stability of incoming video is such that sync positioning varies more than ±16 pixels or if occasional horizontal sync pulses are missing. mP l/O 5 PRODUCT SPECIFICATION TMC22071A Pin Definitions (continued) Pin Number Pin Name 68 pin PLCC 100 pin MQFP Pin Type Function Analog Interface VREF 38 70 +1.23 V VREF input/output. +1.23 Volt reference. When the internal voltage reference is used, this pin should be decoupled to AGND with a 0.1 mF capacitor. An external +1.2 Volt reference may be connected here, overriding the internal reference source. COMP 48 88 0.1 mF Compensation capacitor. Compensation for DDS D/A converter circuitry. This pin should be decoupled to VDDA with a 0.1 mF capacitor. RT,RB 36, 28 68 0.1 mF A/D VREF decoupling. Decoupling points for A/D converter voltage references. These pins should be decoupled to AGND with a 0.1 mF capacitor. DDS OUT 45 82 Internal DDS output. Analog output from the internal Direct Digital Synthesizer D/A converter, at 1/9 the PXCK frequency. PFD IN 43 77 Horizontal PLL input. Analog input to the Phase/Frequency Detector of the horizontal phase-locked loop. CBYP 42 75 1 mF Comparator bypass. Decoupling point for the internal comparator reference of the Phase/Frequency Detector. This pin should be decoupled to AGND with a 0.1 mF capacitor. 23, 25, 26, 30, 33, 40, 47 49, 51, 52, 60, 64, 73, 87 +5 V Analog power supply. Positive power supply to analog section. 1, 7,18, 6, 18, 22, 52, 26, 42, 58,59,63 44, 48, 92, 98, 100 +5 V Digital power supply. Positive power supply to digital section. PLL Filter Power Supply VDDA VDD Ground AGND 24, 27, 32, 35, 37, 39, 41, 44, 49, 50, 55, 63, 67, 69, 72, 74, 81, 89 0.0 V Analog ground. Ground for analog section. DGND 8, 15, 16, 20, 21, 50, 55-57, 65, 68 8, 16, 27, 38, 39, 41, 46, 47, 90, 9597 0.0 V Digital ground. Ground for digital section. 6 PRODUCT SPECIFICATION TMC22071A Control and Status Registers Table 1. Microprocessor Port Control The TMC22071A is controlled by a single 47-bit long Control Register. Access to the Control Register is via the I/O Port Shift Register arranged as shown in Figure 1. The Control Register can be written, with the desired programming. The 12-bit Status Register is read-only and accessed through the same l/O Port Shift Register. Reading the Status Register yields information about blanking level, subcarrier presence, and whether or not PXCK is locked or unlocked with respect to the line rate. I/O Port Shift Register D0 0 46 Control Register 47 58 Status Register A0 R/W Action 0 0 Write data from D0 into l/O Port Shift Register 0 1 Read D0 data from last stage of l/O Port Shift Register 1 0 Transfer l/O Port Shift Register contents to Control Register 1 1 Enables continuous update of status bits in l/O Port Shift Register The full sequence of 47 bits of Control Register data must be written each time a change in that data is desired. All or a few of the Control and Status Register bits may be read, but the sequence always begins with bit 58 of the Status Register. CS 65-22071-03 Figure 1. Control and Shift Register Structure The host processor writes data into the TMC22071A using only one bit of the microprocessor’s data and address bus. As shown in Figure 2, the user should bring A0 high for the CS falling edge preceding the introduction of bit 0 to the D0 port. The next rising edge of CS completes the preloading of the control data, which transfer into the control register on the next rising edge of the pixel clock. The I/O Port Shift Register, Control Register and Status Register are governed by CS, R/W, and A0. R/W and A0 are latched by the TMC22071A on the falling edge of CS and data input D0 is latched on the rising edge of CS. Data read from D0 is enabled by the falling edge of CS and disabled by the rising edge of CS. When the Control Register is read more than once consecutively, an extra CS pulse and accompanying A0 is needed to align the circulated shift register data. R/W D0 46 45 1 0 tH A0 tS 65-22071-04 Figure 2. Data Write Sequence CS R/W D0 58 57 1 0 A0 65-22071A-05 Figure 3. Data Read Sequence 7 TMC22071A PRODUCT SPECIFICATION 7 8 15 16 39 40 46 TEST TEST GRSONLY 0 0 STVAL TEST BPFOUT DCLAMP 0 0 0 0 0 VCR/TV CVBSEN TEST AGC FREERUN LEADLAG (LSB) TEST VGAIN 31 32 0 0 0 1 TEST 24 LEADLAG 23 0 0 SOURCE TEST FORMAT SRESET 0 0 0 SUBPIX 0 STATUS REGISTER TEST TEST 58 LOCK BLKAMP COLOR (LSB) (MSB) 54 55 47 65-22071-06 Figure 4. Control Register Map Control Register Bit Functions Bit Name Function 0 SRESET Software reset. When LOW, resets and holds internal state machines, resets Control Register with previously written values, and disables output drivers. When HIGH, SRESET starts and runs state machines, PXCK, and enables outputs. 1-3 FORMAT Input signal format select. Bit 3 is the MSB. 000 NTSC at 12.27 Mpps. 001 NTSC at 13.5 Mpps. 010 Reserved. 011 Reserved. 100 PAL at 13.5 Mpps. 101 Reserved. 11x Reserved. 4-6 TEST Factory test control bits. These should be set LOW. 7,8 SOURCE Video source select. Bit 8 is the MSB. 00 VIN1 01 VIN2 1x VIN3 8 9 VGAIN Video gain. When LOW, gain is set to unity. When HIGH, gain is set to 1.5X. 10-11 TEST Factory test control bits. These should be set LOW. 12-16 SUBPIX These control bits allows the HSYNC, VSYNC, and sample clock to be time-shifted by -16/32 to +15/32 pixels. Bit 16 is the two’s complement MSB. When SUBPIX is 00h, HSYNC and incoming video are subject to LEADLAG. A value of 18h delays HSYNC 1/4 pixel. A value of 08h advances HSYNC 1/4 pixel. 17-24 LEADLAG This control word allows the HSYNC and VSYNC to be time-shifted -122 to +132 LDV cycles. When LEADLAG is 7Bh, HSYNC and incoming video are in alignment. A value of 83h delays HSYNC eight LDV cycles. A value of 73h advances HSYNC eight LDV cycles. Bit 24 is the MSB. PRODUCT SPECIFICATION TMC22071A Control Register Bit Functions (continued) Bit Name Function 25 AGC AGC operation control. After H and V sync acquisition, the A/D converter references are adjusted to encompass the full video range. The system can initiate an A/D adjustment sequence at any time by bringing this bit HIGH. The control bit will reset to 0 following AGC adjustment. 26 FRERUN When HIGH, a free-running PXCK is generated, independent of incoming video. When LOW, PXCK is locked to incoming video. 27-29 TEST Factory test control bits. These should be set LOW. 30 VCR/TV Block sync enable. When HIGH the TMC22071A accepts both normal and block sync. (In block sync, the incoming signal is at the sync tip level for 2.5 (PAL) or 3 (NTSC) consecutive lines. Equalization pulses may be absent.) When LOW, only normal sync may be input. For most applications, whether using a VCR or a studio video input source, best performance will be found when this bit is HIGH. 31 CVBSEN CVBS bus enable. When LOW, the CVBS7-0, GHSYNC, and GVSYNC outputs are in a high-impedance state. When HIGH, they are enabled. 32 TEST Factory test control bit. This should be set LOW. 33 BPFOUT Burst phase / frequency output control. When HIGH, GRS is disabled. When LOW, burst phase and frequency information is output on CVBS3-0. 34 DCLAMP Digital clamp enable. The digital clamp is enabled when DCLAMP is HIGH and disabled when LOW. 35-39 TEST Factory test control bits. These should be set LOW. 40-43 STVAL Sync tip value. When DCLAMP is HIGH and STVAL is set to its default value 3h the output sync level is 3h for NTSC and 7h for PAL. Bit 43 is the MSB. 44 VCR VCR lock control. Setting this bit LOW improves the TMC22071A’s locking to VCR signals. When only clean video input signals are used, the user may set this bit HIGH for compatibility with existing TMC22071 firmware. 45 TEST Factory test control bit. This should be set LOW. 46 GRSONLY When the horizontal phase lock loop becomes unlocked (i.e. after video input is disconnected) and this Control Bit is HIGH, all CVBS data is forced LOW except subcarrier frequency and phase data (GRS). GHSYNC, GVSYNC, and PXCK continue with default GRS data until video is required. The presence of GRS also depends upon bit 33. If the GRSONLY bit is LOW, GHSYNC, GVSYNC, and PXCK continue with default GRS data continue but video pixel data is random. Status Bits (Read Only) 47 COLOR Burst present status bit. This bit is HIGH when burst is present on the input video. It is LOW, when burst is not present. 48-55 BLKAMP Blanking amplitude status bit. These eight bits report the actual blanking level. 56 LOCK H-lock loop status bit. When HIGH, the TMC22071A is not locked to an input signal. When LOW, lock has been achieved. 57-58 TEST These are read-only bits for testing puposes only. 9 TMC22071A PRODUCT SPECIFICATION Horizontal Timing 2.35 µsec PAL 2.3 µsec NTSC Equalizing Pulse Horizontal line rate is selectable, and is determined by the FORMAT control bits (12.27 Mpps for NTSC, 13.5 Mpps for NTSC and PAL). Figure 5 illustrates the horizontal blanking interval. Figure 6 completes the definition of timing parameters with vertical blanking interval detail. H 0.5H 4.7 µsec Serration Video In GVSYNC tVD GHSYNC (Odd Field) tDH GHSYNC (Even Field) Video In 65-22071-08 Figure 6. Vertical Sync timing Burst Programming the TMC22071A Upon power-up after bringing RESET LOW, the TMC22071A Control Register is set to default values as shown in the top entry of Table 3. These default values do not necessarily render the TMC22071A operational in any specific application. Before the TMC22071A is expected to acquire input video, its Control Register must be loaded with data that is specific to its use. tDH GHSYNC 65-22071-07 Figure 5. Horizontal Sync Timing Table 2.TMC22071A Timing Options Field Rate (Hz) Line Rate (kHz) Pixel Rate (Mpps) PXCK Frequency (MHz) Plxels Per Line NTSC 59.94 15.734264 12.2727+ 24.54+ 780 NTSC-601 59.94 15.734264 13.50 27.0 858 PAL-601 50.00 15.625 13.50 27.0 864 Standard Table 3. Control Register Example Data Control Register Data (Bit 56 …… Bit 0) Standard 46 42 38 34 30 26 22 18 14 10 6 2 DEFAULT 0000 0110 0000 1001 0000 0010 0000 0000 0000 0000 0000 001 NTSC 0010 0110 0000 1001 1000 0010 0000 0000 0000 00xx 0000 000 NTSC-601 0010 0110 0000 1001 1000 0010 0000 0000 0000 00xx 0000 010 PAL-601 0010 1110 0000 1001 1000 0010 0000 0000 0000 00xx 0001 xx0 10 PRODUCT SPECIFICATION TMC22071A CVBS Bus Data Formats The CVBS bus outputs a Genlock Reference Signal (GRS) along with the 8-bit digital composite video data. The range of output data versus video input voltage is illustrated in Figure 7 where sync tip and blanking levels are controlled by the digital backporch clamp of the TMC22071A. During horizontal sync, the TMC22071A outputs field identification, subcarrier frequency, and subcarrier phase information on the CVBS bus. Field identification is output on CVBS2-0. The LSB, CVBS0, will be LOW during odd fields and HIGH for even fields. When NTSC operation is selected, CVBS1-0 count 00,01,10,11 for fields 1 through 4 respectively. When PAL operation is selected, CVBS2-0 count 000, 001, 010, etc. to 111 for fields 1 through 8, respectively. CVBS3 indicates V-component inversion in PAL. It is HIGH for NTSC lines (burst 135°) and LOW for PAL lines (burst 225°) NTSC PAL Peak Chrominance Peak Luminance FEh FFh D2h CFh 3Ch 40h 03h 03h Subcarrier frequency is sent out in a 24-bit binary representation in six 4-bit nibbles on CVBS3-0. Subcarrier frequency data, f23-0, is identical to the pre-programmed BSEED value used in the TMC22071A to lock the subcarrier phase-locked loop to the incoming subcarrier frequency. Back Porch Blanking Burst Sync Tip Subcarrier phase, F23-0, is also sent out in a 24-bit binary representation in six 4-bit nibbles on CVBS3-0. Bit F23 is the MSB. 65-22071-09 Figure 7. Output Data vs. Input Video Level PXCK 0 1 2 3 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 GHSYNC CVBS7:0 PIXEL PIXEL PIXEL f23:20 f19:16 f15:12 f11:8 f7:4 f3:0 f23:20 f19:16 f15:12 f11:8 FREQUENCY f7:4 f3:0 PIXEL PHASE PIXEL 65-22071-10 FIELD IDENTIFICATION Figure 8. Genlock Reference Signal (GRS) Format tPWHPX tPWHPX 1/fPXCK PXCK tDO GHSYNC tXL tXV LDV tHO CVBS7:0 PIXEL 0 PIXEL 1 65-22071-11 Figure 9. CVBS Bus Video Data Format 11 TMC22071A PRODUCT SPECIFICATION tPWLCS tPWHCS CS tSA tHA R/W A0 tSD tHD D0 65-22071-12 Figure 10. Microprocessor Port – Write Timing tPWLCS tPWHCS CS tSA tHA R/W A0 tDOM tHOM D0 tDOZ Figure 11. Microprocessor Port – Read Timing 12 65-22071-13 PRODUCT SPECIFICATION TMC22071A Equivalent Circuits and Transition Levels VDD VDD n Substrate VDD 2k½ n p VDD PFD IN p CBYP p DDS OUT +2.4 V + – 150½ 65-22071-15 65-22071-14 Figure 12. Equivalent PFD IN Circuit Figure 13. Equivalent DDS OUT Circuit VDD VDD p p n Substrate Input Output n n 65-22071-17 65-22071-16 Figure 14. Equivalent Digital Input Circuit Figure 15. Equivalent Digital Output Circuit tDOM CS tHOM tDOZ 0.5 V Hi-Z D0 2.0 V 0.8 V 0.5 V 65-22071-18 Figure 16. Transition Levels for Three-State Measurements 13 TMC22071A PRODUCT SPECIFICATION Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Min. Max. Unit. Power Supply Voltage -0.5 7.0 V Input Voltage -0.5 VDD + 0.5 V -0.5 VDD + 0.5 V -6.0 6.0 mA 1 sec 130 °C Operating, Junction 150 °C Lead Soldering (10 seconds) 300 °C Digital Outputs Applied Voltage2 3,4 Forced Current Short Circuit Duration (single output in HIGH state to GND) Temperature Operating, Case -60 Vapor Phase Soldering (1 minute) Storage -65 220 °C 150 °C Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device. Operating Conditions (for standard temperature range) Parameter VDD Power Supply Voltage VIH Input Voltage, Logic HIGH TTL Inputs CMOS Inputs VIL Min. Nom. Max. Units 4.75 5.0 5.25 V 2.0 VDD V 2/3VDD VDD V Input Voltage, Logic LOW TTL Inputs DGND 0.8 V CMOS Inputs DGND 1/3 VDD V IOH Output Current, Logic HIGH -2.0 mA lOL Output Current, Logic LOW 4.0 mA VIN Video Input Signal Level, Sync Tip to Peak White VREF External Reference Voltage TA Ambient Temperature, Still Air 1.0 V 1.235 0 V 70 °C Microprocessor Interface tPWHCS CS Pulse Width, LOW 50 ns tPWHCS CS Pulse Width, HIGH 50 ns tSA Address Setup Time 0 ns tHA Address Hold Time 16 ns tSD Data Setup Time 20 ns tHD Data Hold Time 0 ns Note: 1. Timing reference points are at the 50% level. 14 PRODUCT SPECIFICATION TMC22071A Electrical Characteristics (for standard temperature range) Parameter Conditions 1 Min Typ Max Units 190 230 mA IDD Power Supply Current Total Current VDD = Max, fPXCK = 30MHz IREF Reference Inputcurrent VREF = +1.235V 100 mA IIH Input Current, Logic HIGH VDD = Max, VIN = 4.0V ±10 mA IIL Input Current, Logic LOW VDD = Max, VIN = 0.4V ±10 mA VOH Output Voltage, Logic HIGH IOH = -2.0 mA VOL Output Voltage, Logic LOW IOL = 4.0 mA 0.4 V IOZH Hi-Z Output Leakage current, HIGH VDD = Max, VIN = VDD ±10 mA IOZL Hi-Z Output Leakage current, LOW VDD = Max, VIN =GND ±10 mA Cl Digital Input Capacitance TA = 25°C, f = 1 Mhz 4 15 pF CO Digital Output Capacitance TA - 25°C, f = 1 Mhz 10 CV Input Capacitance, VIN1-3 TA = 25°C, f = 3.58 Mhz RV Input Resistance, VIN1-3 2.4 V pF 15 50 pF kW Note: 1. Typical IDD with VDD = +5.0 Volts and TA = 25°C, Maximum IDD with VDD = +5.25 Volts and TA = 0°C. Switching Characteristics (for standard temperature range) Parameter Conditlons Max Units 2 15 ns Output Hold Time 3 8 ns fPCK Pixel Rate 12 15.3 MHz fPXCK Master Clock Rate 24 30.6 MHz tPWHPX PXCK Pulse Width, LOW 12 ns tPWHPX PXCK Pulse Width, HIGH 12 ns tDH Horizontal Sync to GHSYNC 14 pixels tVD Vertical Sync to GVSYNC 14 pixels tXL PXCK LOW to LDV HIGH tXV PXCK LOW to LDV LOW tDOM D0 enable time tHOM D0 disable time tDOZ CS LOW to D0 output driven tDO Output Delay Time tHO CLOAD = 35 pF Min 10 Typ 8 ns 8 ns 20 ns 15 ns 5 ns 15 TMC22071A PRODUCT SPECIFICATION System Performance Characterlstics Parameter Min Type Max 1 Units ESCH Sync time-base variation ±3 ns ESCP Subcarrier Phase Error1 ±2 degrees tAL Line-lock Acquisition Time 2 frames VXT Channel-to-Channel Crosstalk @3.58 Mhz -35 dB Note: 1. NTSC/PAL compliant black burst at nominal input level ±10%, frequencies nominal ±10 ppm. +5V Ferrite Bead 6.8 pF Analog Supply Plane* Digital Supply Plane 10µF 10µF 0.1µF 0.1µF 10µH 150 pF 390 pF 0.01 µF +5V DGND LPF 75½ LPF Video C DDS OUT PFD IN COMP 3.3 µF VREF VIN2 LM385-1.2 TMC22071A Genlocking Video Digitizer 3.3 µF VIN3 0.1µF RB RESET D0 A0 CS R/W INT VALID CBYP CVBS7:0 GHSYNC GVSYNC PXCK LDV 0.1µF 8 0.1µF and MICROPROCESSOR INTERFACE must be connected DIGITAL VIDEO INTERFACE EXT PXCK CLK IN CLK OUT PXCK SEL 0.1µF RT 75½ 20 MHz, TTL 0.1µF 3.3K½ VIN1 75½ Video B AGND 3.3 µF LPF Video A VDD VDDA 65-22071A-19 *section of supply plane beneath analog interface circuitry via low-impedance path Figure 17. Typical Interface Circuit Application Notes The TMC22071A is a complex mixed-signal VLSI circuit. It produces CMOS digital signals at clock rates of up to 15 MHz while processing analog video inputs with a resolution of less than a few millivolts. To maximize performance it is important to provide an electrically quiet operating environment. The circuit shown in Figure 17 provides an optional external 1.2V reference to the VREF input of the TMC22071A. The internal VREF source is adequate for most applications. Flltering Inexpensive low-pass anti-aliasing filters are shown in Figures 18 and 20. These filters would normally be inserted in the video signal path just before the 75W terminating resistor and AC-coupling capacitor for each of the three video inputs, VIN1-3. The filter of Figure 18 exhibits a 5th-order 16 Chebyshev response with-3dB bandwidth of 6.7MHz and a group delay of 140 nanoseconds at 5MHz. The filter of Figure 19 has been equalized for group delay in the video signal band. Its -3dB passband is 5.5MHz while the group delay is constant at 220 nanoseconds through the DC to 5MHz frequency band. 2.2µH 470 pF 2.2µH 1000 pF 470 pF 65-22071-20 Figure 18. Simple Anti-aliasing Filter PRODUCT SPECIFICATION 3.3 µH 430 pF TMC22071A 3.3 µH 750 pF 4.7 µH 4.7 µH 470 pF 430 pF Grounding The TMC22071A has separate analog and digital circuits. To minimize digital crosstalk into the analog signals, the power supplies and ground connections are provided over separate pins (VDD and VDDA are digital and analog power supply pins; DGND and AGND are digital and analog ground pins). In general, the best results are obtained by tying all grounds to a solid, low-impedance ground plane. Power supply pins should be individually decoupled at the pin. Power supply noise isolation should be provided between analog and digital supplies via a ferrite bead inductor on the analog lead. Ultimately all +5 Volt power to the TMC22071A should come from the same power source. 470 pF 910 µH 2.2 µH 65-22071-21 Figure 19. Group Delay Equalizer Filter Using a 20 MHz Crystal In systems where a 20 MHz clock is not available, a crystal may be used to generate the clock to the TMC22071A. The crystal must be a 20 MHz “fundamental” type, not overtone. Specific crystal characteristics are listed in Table 4 and the connections are shown in Figure 20. Another approach calls for separating analog and digital ground. While some systems may benefit from this strategy, analog and digital grounds must be kept within 0.1V of each other at all times. Table 4. Crystal Parameters Parameter Value Fundamental frequency Interface to the TMC22x9x Encoder 20 MHz Tolerance ±30 ppm @ 25°C Stability ±50 ppm, 0°C to 70°C Load Capacitance 20 pF Shunt Capacitance 7 pF Max. ESR 50 W, Max. The TMC22x9x Digital Video Encoders have been designed to directly interface to the TMC22071A Digital Video Genlock. The TMC22071A is the source for TMC22x9x input signals CVBS7-0, GHSYNC, GVSYNC, LDV, and PXCK as shown in Figure 21. These signals directly connect to the TMC22x9x. The microprocessor interface for TMC22x9x and TMC22071A are identical. All R/W, RESET, data and address bus signals from the host microprocessor are shared by the TMC22x9x and TMC22071A. Only CS, VALID, and INT signals are separate from the microprocessor bus. TMC22071A 33 pF CLK IN 1M½ 20 MHz Crystal 300½ CLK OUT 33 pF 65-22071A-22 Figure 20. Direct Crystal Connections CS R/W TMC22x9x DIGITAL VIDEO ENCODER A1:0 CVBS7:0 GHSYNC GVSYNC PXCK LDV RESET D7:0 8 CS R/W A0 RESET D0 CVBS7:0 GHSYNC GVSYNC PXCK TMC22071A LDV GENLOCKING VIDEO DIGITIZER 2 8 MICROPROCESSOR INTERFACE 65-22071A-23 Figure 21. TMC22x9x Interface Circuit 17 TMC22071A Printed Circuit Board Layout PRODUCT SPECIFICATION 4. Decoupling capacitors should be applied liberally to VDD pins. Remember that not all power supply pins are created equal. They typically supply adjacent circuits on the device, which generate varying amounts of noise. For best results, use 0.1mF capacitors in parallel with 10mF capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. 5. If the digital power supply has a dedicated power plane layer, it should not overlap the TMC22071A, the voltage reference or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the TMC22071A and its related analog circuitry can degrade performance. 6. CLK should be handled carefully. Jitter and noise on this clock or its ground reference may degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing. Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Wire-wrap is not an option. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor picture quality. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (COMP,VREF, RT, RB, DDS OUT, PFD IN, CBYP, and VIN1-3) as short as possible and as far as possible from all digital signals. The TMC22071A should be located near the board edge, close to the analog output connectors. 2. The digital power plane for the TMC22071A should be that which supplies the rest of the digital circuitry. A single power plane should be used for all of the VDD pins. If the analog power supply for the TMC22071A is the same as that of the system’s digital circuitry, power to the TMC22071A VDDA pins should be decoupled with ferrite beads and 0.1 mF capacitors to reduce noise. 3. 18 The ground plane should be solid, nor cross-hatched. Connections to the ground plane should have very short leads. Related Products • • • • • TMC22x9x Digital Video Encoders TMC2242/TMC2243/TMC2246 Video Filters TMC2081 Digital Video Mixer TMC22x5y Digital Decoders TMC2302 Image Manipulation Sequencer PRODUCT SPECIFICATION TMC22071A Notes: 19 TMC22071A Notes: 20 PRODUCT SPECIFICATION PRODUCT SPECIFICATION TMC22071A Notes: 21 TMC22071A PRODUCT SPECIFICATION Mechanical Dimensions 68 Lead PLCC Package Inches Symbol Min. A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Max. Min. 4.19 5.08 2.29 3.30 .51 — .33 .53 .66 .81 25.02 25.27 24.13 24.33 20.32 BSC 1.27 BSC .042 1.07 17 68 — Notes Max. .165 .200 .090 .130 .020 — .013 .021 .026 .032 .985 .995 .950 .958 .800 BSC .050 BSC .056 Notes: Millimeters 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45¡ 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm) 3 1.42 2 17 68 .004 — 0.10 E E1 J D D1 D3/E3 B1 e A A1 A2 22 J B -CLEAD COPLANARITY ccc C PRODUCT SPECIFICATION TMC22071A Mechanical Dimensions (continued) 100 Lead MQFP Package – 3.2mm Footprint Inches Symbol Notes: Millimeters Notes Min. Max. Min. Max. A A1 A2 B C D — .010 .100 .008 .005 .904 .134 — .120 .015 .009 .923 — .25 2.55 .22 .13 22.95 3.40 — 3.05 .38 .23 23.45 D1 E E1 e L N ND NE .783 .791 .667 .687 .547 .555 .0256 BSC .028 .040 100 30 20 a ccc 0¡ — 7¡ .004 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 3, 5 5 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness. 19.90 20.10 16.95 17.45 13.90 14.10 .65 BSC .73 1.03 100 30 20 0¡ — 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 4 7¡ .12 D .20 (.008) Min. 0¡ Min. .13 (.30) R .005 (.012) D1 Datum Plane B C E1 a .13 (.005) R Min. Pin 1 Indentifier E L e 0.076" (1.95mm) Ref Lead Detail See Lead Detail Base Plane A A2 B A1 Seating Plane -CLead Coplanarity ccc C 23 TMC22071A PRODUCT SPECIFICATION Ordering Information Product Number Temperature Range Screening Package Package Marking TMC22071AR1C TA = 0°C to 70°C Commercial 68-Lead PLCC 22071AR1C TMC22071AKHC1 TA = 0°C to 70°C Commercial 100-Lead MQFP 22071AKHC Note: 1. 100 Lead MQFP is strongly recommended for all new board designs. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 7/24/98 0.0m 002 Stock#DS7022071A Ó 1998 Fairchild Semiconductor Corporation