Preliminary Revised August 2001 74LCX32652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs (Preliminary) General Description Features The LCX32652 contains thirty-two non-inverting bidirectional bus transceivers with 3-STATE outputs providing multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Each byte has separate control inputs which can be shorted together for full 32-bit operation. Output Enable pins (OEABn, OEBAn) are provided to control the transceiver function (see Functional Description). ■ 5V tolerant inputs and outputs The LCX32652 is designed for low-voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. ■ ESD performance: The LCX32652 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) ■ 2.3V–3.6V VCC specifications provided ■ 5.7 ns tPD max (VCC = 3.3V), 20 µA ICC max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ ±24 mA output drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74LCX32652GX (Note 2) Package Number BGA114A (Preliminary) Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] Note 2: BGA package available in Tape and Reel only. © 2001 Fairchild Semiconductor Corporation DS500634 www.fairchildsemi.com 74LCX32652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs (Preliminary) August 2001 74LCX32652 Preliminary Connection Diagram Pin Descriptions Pin Assignment for FBGA Pin Names 1A0 - 1A15 Description Data Register A Inputs/3-STATE Outputs 2A0 - 2A15 1B0 - 1B15 Data Register B Inputs/3-STATE Outputs 2B0 - 2B15 CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs OEABn, OEBAn Output Enable Inputs NC No Connect FBGA Pin Assignments (Top Thru View) www.fairchildsemi.com 2 1 2 A 1A0 SAB1 CPAB1 CPBA1 3 4 5 6 SBA1 1B0 B 1A2 1A1 OEAB1 OEBA1 C 1A4 1A3 GND GND 1B1 1B2 1B3 D 1A6 1A5 VCC VCC 1B5 1B4 1B6 E 1A8 1A7 GND GND 1B7 1B8 F 1A10 1A9 GND GND 1B9 1B10 G 1A12 1A11 VCC VCC 1B11 1B12 H 1A13 1A14 GND GND 1B14 1B13 J 1A15 SAB2 SBA2 1B15 K NC L 2A0 SAB3 M 2A2 2A1 GND N 2A4 2A3 VCC P 2A6 2A5 R 2A8 T 2A10 CPAB2 CPBA2 CPAB3 OEAB2 OEBA2 CPBA3 OEAB3 OEBA3 NC SBA3 2B0 GND 2B1 2B2 VCC 2B3 2B4 GND GND 2B5 2B6 2A7 GND GND 2B7 2B8 2A9 VCC VCC 2B9 2B10 GND GND U 2A12 2A11 2B11 2B12 V 2A13 2A14 CPAB4 CPBA4 2B14 2B13 W 2A15 SAB4 OEAB4 OEBA4 SBA4 2B15 Preliminary (Note 3) Inputs Inputs/Outputs (Note 4) OEAB1 OEBA1 CPAB1 CPBA1 L H L H X H H H L X L L L L L L H H H H or L H or L H or L H or L SAB1 SBA1 1A0 thru 1A7 1B0 thru 1B7 Input Input X X X X Isolation X X Input Not Specified X X Input Output X X Not Specified Input Hold A, Store B Store B in Both Registers Store A and B Data X X Output Input X X L Output Input X H or L X H H X X L X H H or L X H X L H or L H or L H H X Operating Mode Store A, Hold B Store A in Both Registers Real-Time B Data to A Bus Store B Data to A Bus Input Output Real-Time A Data to B Bus Stored A Data to B Bus Output Output Stored A Data to B Bus and Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Note 3: Data I/O paths (1A and 1B: 0 - 7) is shown. This also applies to data I/O (1A and 1B: 8 - 15) and #2 control pins, to data (2A and 2B: 0 - 7) and #3 control pins, to data (2A and 2B: 8 - 15) and #4 control pins. Note 4: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 3 www.fairchildsemi.com 74LCX32652 Truth Table 74LCX32652 Preliminary Functional Description Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPABn, CPBAn) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEABn and OEBAn. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental bus-management functions that can be performed with the 74LCX32652 for data register I/O 1A and 1B: 0 - 7. Real-Time Transfer Bus B to Bus A OEAB1 OEBA1 CPAB1 CPBA1 L L X X Real-Time Transfer Bus A to Bus B SAB1 SBA1 X L OEAB1 OEBA1 CPAB1 CPBA1 H H Transfer Storage Data to A or B OEAB1 OEBA1 CPAB1 CPBA1 H L www.fairchildsemi.com H or L H or L X X SAB1 SBA1 L X SAB1 SBA1 Storage SAB1 SBA1 H H OEAB1 OEBA1 CPAB1 CPBA1 4 X H L X L H X X X X X X X X Preliminary 74LCX32652 Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 5 www.fairchildsemi.com 74LCX32652 Preliminary Logic Diagrams (Continued) Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 6 Preliminary Symbol Parameter Value VCC Supply Voltage −0.5 to +7.0 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Conditions Units V V Output in 3-STATE −0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 6) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC V mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions (Note 7) Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH/IOL Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 Units V V V mA −40 85 °C 0 10 ns/V Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 6: IO Absolute Maximum Rating must be observed. Note 7: Unused (inputs or I/O's) must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC TA = −40°C to +85°C (V) Min 2.3 − 2.7 1.7 2.7 − 3.6 2.0 Max V 2.3 − 2.7 0.7 2.7 − 3.6 0.8 2.3 − 3.6 VCC − 0.2 IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.3 − 3.6 Units V V 0.2 IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 V IOL = 24 mA 3.0 0.55 II Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA IOZ 3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0 µA 0 10 µA VI = V IH or VIL IOFF Power-Off Leakage Current VI or VO = 5.5V 7 www.fairchildsemi.com 74LCX32652 Absolute Maximum Ratings(Note 5) 74LCX32652 Preliminary DC Electrical Characteristics Symbol (Continued) Parameter VCC Conditions TA = −40°C to +85°C (V) ICC ∆ICC Quiescent Supply Current Increase in ICC per Input Min Units Max VI = VCC or GND 2.3 − 3.6 20 3.6V ≤ VI, VO ≤ 5.5V (Note 8) 2.3 − 3.6 ±20 VIH = VCC −0.6V 2.3 − 3.6 500 µA µA Note 8: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min Max Min Max Min Max 1.5 5.7 1.5 6.2 1.5 6.8 Bus to Bus 1.5 5.7 1.5 6.2 1.5 6.8 fMAX Maximum Clock Frequency 170 tPHL Propagation Delay tPLH MHz tPHL Propagation Delay 1.5 6.2 1.5 7.0 1.5 7.4 tPLH Clock to Bus 1.5 6.2 1.5 7.0 1.5 7.4 7.8 tPHL Propagation Delay 1.5 6.5 1.5 7.0 1.5 tPLH Select to Bus 1.5 6.5 1.5 7.0 1.5 7.8 tPZL Output Enable Time 1.5 7.0 1.5 8.0 1.5 9.1 1.5 7.0 1.5 8.0 1.5 9.1 1.5 6.5 1.5 7.0 1.5 7.8 1.5 6.5 1.5 7.0 1.5 7.8 tPZH tPLZ Output Disable Time tPHZ Units ns ns ns ns ns tS Setup Time 2.5 2.5 3.0 tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.0 3.0 3.5 ns ns Dynamic Switching Characteristics Symbol VCC TA = 25°C (V) Typical CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 CL = 30 pF, VIH = 2.5V, VIL =0V 2.5 0.6 CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 CL = 30 pF, VIH = 2.5V, VIL =0V 2.5 −0.6 Parameter VOLP Quiet Output Dynamic Peak VOL VOLV Quiet Output Dynamic Valley VOL Conditions Units V V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF www.fairchildsemi.com Conditions 8 Preliminary 74LCX32652 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V, and 2.7V VCC x 2 at VCC = 2.5 ± 0.2V tPZH, tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1 MHz, tr = tf = 3 ns) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 9 www.fairchildsemi.com 74LCX32652 Preliminary Schematic Diagram Generic for LCX Family www.fairchildsemi.com 10 Preliminary 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A Preliminary Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com 74LCX32652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs (Preliminary) Physical Dimensions inches (millimeters) unless otherwise noted