CY24488 Quad PLL Clock Generator with Serial Interface (I2C) Features Benefits •Three output frequencies plus reference out •Programmable output frequencies via I2C serial interface •Output frequencies from 4.9152 to 148.5 MHz •Uses an external 27 MHz crystal or 27 MHz input clock •Optional analog VCXO •Programmable output drive strength to minimize EMI •The non-I2C equivalent is the CY22388 / 89 / 91 •16-pin TSSOP package •3.3V operation with 2.5V output buffer option •Meets most Digital Set Top Box, DVD Recorder, and DTV application requirements •Multiple high-performance PLLs allow synthesis of unrelated frequencies •Integration eliminates the need for external loop filter components •Complete VCXO solution with ±120 ppm (typical pull range) Pin Configuration Block Diagram CLKC PLL1 XIN/CLKIN 1 16 XOUT CLKD VCXO XOUT XIN/CLKIN PLL2 Dividers & Multiplexers VIN PLL3 CLKF SDAT 2 15 AVDD 3 14 DNC VIN 4 13 VDD2 VDD1 5 12 VSS VSS CLKE PLL4 SCLK SCLK SDAT Serial Interface & Select Logic CLKG 6 11 CLKG CLKC 7 10 CLKF CLKD 8 9 CLKE Table 1. Applications and Frequencies Output Clock CLKC CLKD Application Frequencies (MHz) Audio 6.144, 8.192, 11.2896, 12.288, 16.384, 16.9344, 18.432, 22.5792, 24.576, 33.8688, 36.864 iLink 24.576 HDMI 25.175, 28.322 Video 27, 27.027, 54, 54.054, 81 USB 12, 24, 48 Video-Pixel Freq. Modem CLKE 74.25/1.001, 74.25, 148.5/1.001, 148.5 4.9152, 11.0592 iLink 24.576 Video 13.5, 27, 54, 81, 108 Ethernet 25 PCI 33.3333, 66.6666 Processor 20, 30, 40, 50, 60, 80, 100 CLKF see CLKC/D/E REFOUT or Copy of CLKC, CLKD or CLKE CLKG see CLKC/D/E REFOUT or Copy of CLKC, CLKD or CLKE Cypress Semiconductor Corporation Document #: 001-09608 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 31, 2006 [+] Feedback CY24488 Pin Description Pin Name Pin Number Pin Description XIN/CLKIN 1 Crystal Input (27 MHz) or External Input Clock (27 MHz) XOUT 16 Crystal Output CLKC 7 Clock Output CLKD 8 Clock Output CLKE 9 Clock Output CLKF 10 Clock Output CLKG 11 Clock Output SCLK 2 Serial Interface (I2C) Clock Input SDAT 3 Serial Interface (I2C) Data VIN 4 Analog Control Input for VCXO DNC 14 Do Not Connect. This pin should be left floating. AVDD 15 Core and input Voltage Supply VDD1 5 Voltage Supply for Outputs CLKC VDD2 13 Voltage Supply for Outputs CLKD, CLKE, CLKF, CLKG VSS 6,12 Ground General Description The CY24488 generates up to three independent clock frequencies, plus a buffered copy of the reference crystal frequency, from a single crystal or reference input. Five clock output pins are available, which allows some frequencies to be driven on two or more output pins. Outputs can also be individually enabled or disabled. When a CLK output is individually disabled, it drives low. The analog voltage controlled crystal oscillator (VCXO) allows t heusert o“ pul l ”t her ef er enc ec r ys t alt oaf r equenc yt hati s slightly higher or lower than nominal. Doing so will cause all output clocks to shift by an equivalent parts-per-million (PPM). The VCXO is controlled by the analog control voltage applied to the VIN pin. For applications that do not require the VCXO functionality, it can be disabled. A serial programming interface (SPI) permits in-system configuration of the device by writing to internal registers. It is used to set the output frequencies, enable and disable outputs, enable and disable the VCXO feature, etc. The SPI provides volatile programming. When powered down, the device reverts to its pre-SPI state. When the system is powered back up, the SPI registers will need to be configured again. Specific configuration details are given later in this data sheet. Customers may contact their Cypress FAE or salesperson for any frequency that is not listed in this data sheet. The data sheet can be updated with a new hex code for the requested frequency. Default Start-up Configuration The default state of the device refers to its state at power on. All output clocks are off except CLKG, which outputs a copy of the 27 MHz reference clock. The serial programming interface must be used to configure the device for the desired output Document #: 001-09608 Rev. *A frequencies. Because the serial programming memory is volatile, the device will revert to its default configuration when power is cycled. Reference Input There are three programmable reference operating modes for the CY24488 family of devices. Table 2 shows the data values that must be programmed into the device for each of the reference operating modes. The correct values are required to ensure frequency accuracy and VCXO pullability. The first mode utilizes an external 27 MHz pullable crystal and incorporates the internal analog VCXO. The crystal is connected between the XIN/CLKIN and XOUT pins. See “ Cr y s t al Requi r ement s”f orf ur t herdet ai l s . The second mode disables the VCXO input control and utilizes a standard 27 MHz crystal. Crystal requirements are relaxed relative to the VCXO mode. The crystal is connected between t heXI N/ CLKI NandXOUTpi ns .See“ Cr y st alRequi r ement s. ” In this mode, tie the VIN pin to AVDD. The third mode accepts an external 27 MHz reference clock, applied to the XIN/CLKIN pin. In this configuration, the XOUT pin must be unconnected. The VCXO feature is not available; tie the VIN pin to AVDD. Analog VCXO The VCXO feature allows the user to fine tune the output frequency via a control voltage applied to the VIN pin. A special pullable crystal must be used in order to have adequate VCXO pull range. This data sheet lists specific crystals that have been qualified for used with the CY24488. Specific serial programming values are also given for each crystal. Page 2 of 15 [+] Feedback CY24488 The special crystal requirements are eliminated if the VCXO feature is not needed. To disable the VCXO, the VIN pin must be tied high, and the appropriate register values given in the programming table must be programmed into the device. clock frequencies, as shown in the tables below. To do this, find the desired frequency from the appropriate table, then use the serial programming interface to write the specified hexadecimal data into the specified memory addresses. The VCXO is completely analog, so there is infinite resolution on the VCXO pull curve. The analog-to-digital converter steps that are normally associated with a digital VCXO input are not present in this device. In some cases the data at a particular memory address controls multiple functions, so only some of the bit values are specified. Since a byte is the smallest unit of data that can be written, it is necessary to construct the full data byte prior to writing it. To do this, look in the other tables to find the correct values for the other bits in that byte. VCXO Profile Figure 1 shows an example of what a VCXO profile looks like. The analog voltage input is on the X-axis and the PPM range is on the Y-axis. An increase in the VCXO input voltage results in a corresponding increase in the output frequency. This has the effect of moving the PPM from a negative to positive offset Enabling and Disabling Output Clocks Figure 1. VCXO Profile All output clocks can be individually enabled or disabled. Only CLKG is on at power on. All other clocks are off (driven low), and their respective PLLs are off. When using the serial programming interface to set an output to a desired frequency, the PLL Lock Time (AC Parameters Table) applies. 200 150 Tuning [ppm] 100 50 0 -50 0 0.5 1 Any of the remaining output clocks (CLKF and CLKG) can be configured to generate duplicate copies of any the three primary clocks. Any of them can also drive a buffered version of the reference crystal frequency. 1.5 2 2.5 3 3.5 -100 -150 -200 VCXO input [V] Crystal Requirements The crystal requirements for the CY24488 differ for the VCXO and non-VCXO modes. In all cases, the device must be programmed correctly for the specific crystal used, as indicated in Table 2. Crystals for Non-VCXO Mode When not using the VCXO, the VIN pin should be tied high. The CY24488 uses a standard AT-cut parallel resonant crystal, which is available in a variety of packages. The key crystal parameter is load capacitance (CL). The CY24488 has programmable load capacitance, to match a range of crystal CL values. The specific configurations are shown in Table 2. Crystals with CL values outside this range are not recommended. When turning off an output, the output buffer and associated PLL are turned off by different register addresses. Therefore it is possible to turn off an output by programming just one byte, but the PLL will continue to run and consume some power. Therefore the PLL Lock Time does not apply when turning the output back on. The clock configuration tables also show a second off state that also turns off the PLL, saving additional power. This requires programming one or two additional bytes, and the PLL Lock Time applies. Output Drive Strength Output drive strength is configurable, with 2 bits available to s et t hedr i vest r engt hf oreachout put .Thedef aul tv al uei s‘ 10’ , which is medium-high. This is the recommended setting for outputs operating at 3.3V. The recommended setting for 2.5V out put si s‘ 11’ ,whi c h mus tbe pr ogr ammed by t he us er . Table 10 shows which bits must be changed, and how to integrate these bits with other control bits to create valid bytes for shifting in. The user may program any output to a lower drive strength if EMIi sapr obl em.‘ 00’ i st hel owes tdr i v est r engt h,whi l e‘ 11’ i s the highest. Note that the lowest setting is very weak and is not suitable for most applications. Pullable Crystals for VCXO Mode Output Supply Voltage When the VCXO mode is used, the crystal requirements increase considerably in order to ensure the pullable range and glitch-free pulling. Table 2 lists the crystals that Cypress has qualified for use with the CY24488, as well as the corresponding programming configurations. Customers wishing to use non-qualified crystals should first contact Cypress technical support. The clock outputs may be operated at either 3.3V or 2.5V. CLKC has its own power pin (VDD1), while all other clocks are powered by VDD2. VDD1 and VDD2 may be operated at different voltages if desired. AVDD must always be 3.3V. Output Configurations The CY24488 also has internal register settings that should be configured for the actual output supply voltage. The default settings are optimized for VDD1 = VDD2 = 3.3V. Table 10 and Table 3 show the values that need to be programmed for 2.5V supply voltage. CLKC, CLKD, and CLKE are the three primary synthesized output clocks. For each one, the user can select from several Document #: 001-09608 Rev. *A Page 3 of 15 [+] Feedback CY24488 Programming Flow The device registers may be programmed in any sequence, but for convenience, a suggested programming flow is shown in Figure 2. Any step in this programming sequence may be skipped if the default value is the desired value. Example: configure CLKC for 33.8688 MHz and 2.5V output. For address 48H, start with the value in Table 4: 89H (binary 10001001). Table 9 shows that bits 7 & 6 control the drive s t r engt h,whi chs houl dbe‘ 11’ ( f r om Table 10). Therefore, the final value is 11001001, which is C9H. This value is written once. Figure 2. Programming Flow When programming an output frequency, the new frequency will be valid on that output after all of the specified data values have been written to all of the specified addresses. When changing an output frequency, the output may transition through one or more indeterminate frequencies between the writing of the first byte and the last byte. Note that some of the programming steps are not as independent as they appear in the flow diagram. In particular, addresses 48H, 53H, and 57H control both output frequencies and drive strength. Because a byte is the smallest unit that may be programmed through the serial interface, the user must consider both the frequency setting and the output drive strength when constructing the byte value to be written into these particular address. It is not necessary to write more than once to any given address, but that one write must have all of the bits set correctly. Default CLKC, D & E Frequency settings (Tables 4 - 6) Reference CLK & Crystal settings (Table 2) CLKF & G Frequency settings (Tables 7 - 8) Output Supply Voltage settings if 2.5V (Table 3) Drive Strength settings for 2.5V or EMI (Tables 9, 4, 6, 8) Table 2. Register Settings for VCXO and Reference Crystal Reference Clock and VCXO Manufacturer Part No. Address Package Specified CL 16H 17H – – – 89 3A Crystal, VCXO off any any 10.7 pF 88 4F Crystal, VCXO off any any 12 pF 88 5F Crystal, VCXO off (default) any any 12.6 pF 88 67 CLKIN (external reference), VCXO off Crystal, VCXO off any any 14 pF 88 77 Crystal, VCXO on KDS DSX530GA 5x3.2 mm 12.6 pF 88 3A Crystal, VCXO on KDS DSX530GA 5x3.2 mm 10.7 pF 88 2A Crystal, VCXO on RIVER FCX-03 5x3.2 mm 12 pF 88 41 Crystal, VCXO on KDK 5x3.2 mm 12 pF 88 3A Crystal, VCXO on KDS SMD-49 12 pF 88 39 Crystal, VCXO on Ecliptek ECX-6277 SMD-49 12 pF 88 41 Table 3. Register Settings for Output Supply Voltages Output CLKC CLKD, CLKE, CLKF, CLKG Document #: 001-09608 Rev. *A Output Supply Voltages Address 41H 43H VDD1 = 3.3V BF (default) – VDD1 = 2.5V 7F – VDD2 = 3.3V – A0 (default) VDD2 = 2.5V – 90 Page 4 of 15 [+] Feedback CY24488 Table 4. CLKC Output Frequencies (Audio, iLink, or HDMI) Frequency (MHz) Register Address Application Frequency Error 0AH 0BH 0CH 0DH 0EH 0FH 48H[1] – – – – 88 – – 44 8D CLKC off and PLL off (default) – – – – – – – – 8D 25.175 HDMI 0 ppm 01 07 D2 26 18 72 AD 28.322 HDMI 0 ppm 10 39 E2 94 39 6A 91 6.144 (48K x 128) Audio 0 ppm 17 3E D0 1C 06 64 A5 12.288 (32K x 384) Audio 0 ppm 17 3E D0 1C 06 64 A9 16.384 (32K x 512) Audio 0 ppm 17 3E D0 19 0E 64 81 18.432 (48K x 384) Audio 0 ppm 17 3E D0 1C 06 64 89 24.576 (48K x 512) Audio, iLink 0 ppm 17 3E D0 1C 06 64 B5 36.864 (48K x 768) Audio 0 ppm 17 3E D0 1C 06 64 95 11.2896 (44.1K x 256) Audio 0 ppm 17 3E D0 30 16 66 A5 16.9344 (44.1K x 384) Audio 0 ppm 17 3E D0 30 16 66 85 22.5792 (44.1K x 512) Audio 0 ppm 17 3E D0 30 16 66 A9 33.8688 (44.1K x 768) Audio 0 ppm 17 3E D0 30 16 66 89 CLKC off Table 5. CLKD Output Frequencies (Video, Pixel rate, USB, modem or iLink) Frequency (MHz) CLKD off and PLL off (default) Register Address Application Frequency Error 10H 11H 12H 50H – – – – 00 8E – – – – – 8E 12 USB 0 ppm 01 08 30 A2 24 USB 0 ppm 07 1E 30 86 48 USB 0 ppm 07 1E 30 8A 4.9152 Modem +38 ppm 18 21 26 A2 11.0592 Modem +11 ppm 39 8F 28 A6 24.576 iLink 6 ppm 56 8E 33 82 27 (reference) Video 0 ppm – – 02 9A 27.027 Video 0 ppm 7B F2 33 86 54 (ref * 2) Video 0 ppm 02 0E 30 8A CLKD off 54.054 Video 0 ppm 7B F2 33 8A 74.25/1.001 Video pixel rate 0 ppm 59 F8 2C 96 74.25 Video pixel rate 0 ppm 00 03 22 96 81 (ref * 3) Video 0 ppm 00 07 30 B6 148.5/1.001 Video pixel rate 0 ppm 59 F8 2C B2 148.5 Video pixel rate 0 ppm 00 03 22 B2 Note 1. Bi t s[ 7: 6]cont r olCLKCdr i vest r engt h.Thev al uesgi v eni nt hi st abl ecor r es pondt oadr i vest r engt hs et t i ngof‘ 10’ .SeeTable 9 and Table 10. Document #: 001-09608 Rev. *A Page 5 of 15 [+] Feedback CY24488 Table 6. CLKE Output Frequencies (Ethernet, Video, PCI, Processor) Frequency (MHz) CLKE off and PLL off (default) Register Address Application Frequency Error 13H 14H 15H 53H[2] – – – – 00 3E – – – – – 3E 13.5 Video 0 ppm 00 05 26 8E 27 (reference) Video 0 ppm – – 02 6E 54 Video 0 ppm 00 06 24 2E 81 Video 0 ppm 00 07 24 DE 108 Video 0 ppm 00 06 24 5E 20 Processor 0 ppm 07 26 24 9E 25 Ethernet 0 ppm 07 17 30 AE 30 Processor 0 ppm 01 08 28 AE PCI 0 ppm 19 62 30 AE 40 Processor 0 ppm 07 26 30 AE 50 Processor 0 ppm 19 62 30 2E 60 Processor 0 ppm 01 08 28 DE PCI 0 ppm 19 62 30 DE 80 Processor 0 ppm 07 26 30 DE 100 Processor 0 ppm 19 62 30 5E CLKE off 33.333333 66.666666 Table 7. CLKF Output Clock Address 55H Frequency (MHz) Data value (hex) CLKF off (default) 0C 27 MHz reference 18 Copy of CLKC copy of data from Table 4 address 48H Copy of CLKD copy of data from Table 5 address 50H Copy of CLKE copy of data from Table 6 address 53H, divided by 4[3] \ Table 8. CLKG Output Clock (Default = Reference out) Frequency (MHz) CLKG off Address 57H bits [7:6] bits [5:0] 10 001100 27 MHz reference (default) dr i vest r engt h( def aul t =10)–s eeTable 10 011000 Copy of CLKC dr i vest r engt h( def aul t =10)–s eeTable 10 bi t s[ 5: 0]ofaddr ess48H–s eeTable 4 Copy of CLKD dr i vest r engt h( def aul t =10)–s eeTable 10 bi t s[ 5: 0]ofaddr ess50H–s eeTable 5 Copy of CLKE dr i vest r engt h( def aul t =10)–s eeTable 10 bi t s[ 7: 2]ofaddr ess53H–s eeTable 6 Notes 2. Bi t s[ 1: 0]cont r ol CLKDdr i v es t r engt h.Thev al uesgi veni nt hi st abl ec or r espondt oadr i vest r engt hs et t i ngof‘ 10’ .SeeTable 9 and Table 10. 3. Bi t s[ 7: 6]ofaddr es s55Har edon’ tc ar e.Di v i di ngby4i sequi v al entt or i ghtshi f t i ngby2bi t s. Document #: 001-09608 Rev. *A Page 6 of 15 [+] Feedback CY24488 Table 9. Register Settings for Output Drive Strength[4] Output Clock Drive strength bits CLKC bits[7:6] of 48H CLKD bits[1:0] of 53H CLKE bits[7:6] of 54H CLKF bits[5:4] of 56H CLKG bits[7:6] of 57H bit 7 bit 6 bit 5 bit 4 DS bit 3 bit 2 bit 1 see address 53H in Table 6 DS 1 bit 0 see address 48H in Table 4 0 1 0 DS DS DS 0 0 0 0 0 0 0 0 see address 57H in Table 8 [] Table 10. Drive Strength (DS) Values[4] DS Value Drive Strength 3.3V Output 2.5V Output 00 Very low EMI Adjustment EMI Adjustment 01 Medium low EMI Adjustment EMI Adjustment 10 (default) Medium high Standard EMI Adjustment 11 High Extra Drive Standard Notes 4. Thedef aul t dr i vest r engt h( DS)s et t i ngf oral l c l ocksi s‘ 10’ . Al l out put speci f i cat i onsf or3. 3Vout put sar egi venf ort hi svalue. Output specifications for 2.5V outputs ar egi v enf oraset t i ngof‘ 11’ .Tochanget heDSset t i ngs ,t heser i al pr ogr ammi ngi nt er f ac emustbeusedt opr ogr am i nt hedesi red values. Users may program i nany2bi tval ue,butc er t ai nout putspeci f i cat i onswi l l notbeval i df ors et t i ngsot hert han‘ 10’ ( 3. 3V)or‘ 11’ ( 2. 5V) .Seethe DC Parameters and AC Parameters tables for further details. Document #: 001-09608 Rev. *A Page 7 of 15 [+] Feedback CY24488 Serial Programming Interface Protocol and Timing The CY24488 utilizes pins SDAT and SCLK for a 2-wire serial interface that operates up to 400 kbit/s in Read or Write mode. The basic Write protocol is as follows: Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in MA+2; ACK; etc. until STOP Bit. The basic serial format is illustrated in Figure 4. Writing Multiple Bytes In order to write more than one byte at a time, the master does not end the write sequence with a STOP condition. Instead, the master can send multiple contiguous bytes of data to be stored. After each byte, the slave responds with an acknowledge bit, the same as after the first byte, and will accept data until the acknowledge bit is responded to by the STOP condition. When receiving multiple bytes, the CY24488 internally increments the register address. Read Operations The device address is a 7-bit value. The default serial interface address is 47H. Read operations are initiated the same way as Write operat i onsex ceptt hatt heR/ W bi toft hesl av eaddr essi ssett o‘ 1’ (HIGH). There are three basic read operations: current address read, random read, and sequential read. Data Valid Current Address Read Data is valid when the clock is HIGH, and may only be transitioned when the clock is LOW, as illustrated in Figure 5. The CY24488 has an onboard address counter that retains 1 more than the address of the last word access. If the last word wr i t t enorr ead waswor d‘ n’ ,t hen acur r entaddr es sr ead oper at i onwoul dr et ur nt heval uest or edi nl oc at i on‘ n+1’ . When the CY24488 receives the slave address with the R/W bit set t oa‘ 1’ ,t heCY24488i s suesanac k nowl edgeandt r ans mi t s the 8-bit word. The master device does not acknowledge the transfer, but does generate a STOP condition, which causes the CY24488 to stop transmission. Device Address Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 6. START Sequence - Start Frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a start signal is given, the next 8-bit data must be the device address (seven bits) and a R/W bit, followed by register address (eight bits) and register data (eight bits). STOP Sequence - Stop Frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop Frame frees the bus to write to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write Mode the CY24488 will respond with an Acknowledge (ACK) pulse after every eight bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle, as illustrated in Figure 7 (N = the number of bytes transmitted). During Read Mode the acknowledge pulse after the data packet is sent is generated by the master. Write Operations Writing Individual Bytes A valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (SDAT = 0/LOW). The next eight bits must contain the data word intended for storage. After the data word is received, the slave responds with another acknowledge bit (SDAT = 0/LOW), and the master must end the write sequence with a STOP condition. Document #: 001-09608 Rev. *A Random Read Through random read operations, the master may access any memory location. To perform this type of read operation, first set the word address. Send the address to the CY24488 as part of a write operation. After the word address is sent, the master generates a START condition following the acknowledge. This terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. Next the master reissues the control byt ewi t ht heR/ W byt es ett o‘ 1’ .TheCY24488t heni s s uesan acknowledge and transmits the 8-bit word. The master device does not acknowledge the transfer, but does generate a STOP condition, which causes the CY24488 to stop transmission. Sequential Read Sequential read operations follow the same process as random reads except that the master issues an acknowledge instead of a STOP condition after transmission of the first 8-bit data word. This action results in an incrementing of the internal address pointer, and subsequently output of the next 8-bit data word. By continuing to issue acknowledges instead of STOP conditions, the master may serially read the entire contents of the slave device memory. Note that register addresses outside of 0AH to 17H and 40H to 57H can be read from but are not real registers and do not contain configuration information. When the internal address pointer points to the FFH register, after the next increment, the pointer will point to the 00H register. Page 8 of 15 [+] Feedback CY24488 Figure 3. Data Transfer Sequence on the Serial Bus SCL SDAT Address or Acknowledge Valid START Condition STOP Condition Data may be changed Figure 4. Data Frame Architecture SDAT Write Multiple Contiguous Registers 1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address 1 Bit Slave ACK 8-bit Register Address (XXH) 1 Bit Slave ACK 8-bit Register Data (XXH) 1 Bit Slave ACK 8-bit Register Data (XXH+1) 1 Bit Slave ACK 8-bit Register Data (XXH+2) 1 Bit Slave ACK 8-bit Register Data (FFH) 1 Bit Slave ACK 8-bit Register Data (00H) Stop Signal Start Signal SDAT Read Current Address Read Start Signal SDAT Read Multiple Contiguous Registers 1 Bit Slave ACK 1 Bit 1 Bit Slave R/W = 1 ACK 7-bit Device Address 1 Bit Slave ACK 1 Bit Master ACK 8-bit Register Data Stop Signal 1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address 1 Bit Slave ACK 8-bit Register Address (XXH) 1 Bit Master ACK 7-bit Device Address +R/W=1 1 Bit Master ACK 8-bit Register Data (XXH) 1 Bit Master ACK 8-bit Register Data (XXH+1) 8-bit Register Data (FFH) 1 Bit Master ACK 1 Bit Master ACK 1 Bit Master ACK 8-bit Register Data (00H) Stop Signal Start Signal Repeated Start bit Figure 5. Data Valid and Data Transition Periods Data Valid Transition to next Bit SDAT tDH tSU CLKHIGH VIH SCLK Document #: 001-09608 Rev. *A VIL CLKLOW Page 9 of 15 [+] Feedback CY24488 Serial Programming Interface Timing Figure 6. Start and Stop Frame SDAT SCLK Transition to next Bit START STOP Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data) SDAT + START DA6 DA5 DA0 + R/W ACK RA7 RA6 RA1 + RA0 D7 ACK + + D6 D1 D0 ACK STOP + SCLK Serial Programming Interface Timing Specifications Parameter Description Min. Max. Unit – 400 kHz Start Mode Time from SDA LOW to SCL LOW 0.6 – s CLKLOW SCLK LOW Period 1.3 – s CLKHIGH SCLK HIGH Period 0.6 – s tSU Data Transition to SCLK HIGH 100 – ns tDH Data Hold (SCLK LOW to data transition) 0 – ns Rise Time of SCLK and SDAT – 300 ns Fall Time of SCLK and SDAT – 300 ns Stop Mode Time from SCLK HIGH to SDAT HIGH 0.6 – s Stop Mode to Start Mode 1.3 – s fSCLK Frequency of SCLK Document #: 001-09608 Rev. *A Page 10 of 15 [+] Feedback CY24488 Absolute Maximum Conditions Parameter Description Condition AVDD/VDD1 Core Supply Voltage /VDD2 Min. Max. Unit –0. 5 4.6 V VIN Input Voltage Relative to VSS –0. 5 TS Temperature, Storage Non-Functional –65 ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 UL-94 Flammability Rating V-0 @1/8 in. MSL Moisture Sensitivity Level 16 TSSOP VDD + 0.5 VDC +125 °C 2000 – Volts – 10 ppm 1 Pullable Crystal Specifications (for VCXO applications)[5] Parameter Description Comments FNOM AT-cut Crystal Parallel resonance, Fundamental mode CLNOM Nominal Load Capacitance Order crystal at one specific CLNOM 0 ppm R1 Equivalent Series Resistance (ESR) DL Crystal Drive Level F3SEPHI[6] F3SEPLO [6] Min. Typ. Max. 27 Unit MHz 11.4 12 12.6 pF Fundamental mode (CL = Series) – – 40 Nominal VDD @ 25°C over ±120 ppm Pull Range – – 300 W Third Overtone Separation from 3*FNOM Mechanical Third (High side of 3*FNOM) 240 – – ppm Third Overtone Separation from 3*FNOM Mechanical Third (Low side of 3*FNOM) – – Min. Typ. –120 ppm Non-pullable Crystal Specifications (for non-VCXO applications)[5] Parameter Description Comments FNOM AT-cut Crystal Parallel resonance, Fundamental mode CLNOM Nominal Load Capacitance Order crystal at one specific CLNOM 0 ppm R1 Equivalent Series Resistance (ESR) DL Crystal Drive Level Max. 27 Unit MHz 10.7 12 14.0 pF Fundamental mode (CL = Series) – – 40 Nominal VDD @ 25°C – – 300 W Min. Typ. Max. Unit Recommended Operating Conditions Parameter Description AVDD Core Operating Voltage 3.0 3.3 3.6 V VDD1/VDD2 Output Operating Voltage 3.0 3.3 3.6 V 2.3 2.5 2.7 V TA Ambient Temperature –10 – 70 °C CLOAD Maximum Load Capacitance – – 15 pF tPU Power up time for all VDDs reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms Notes 5. Device operates to following specs which are guaranteed by design. 6. Increased tolerance available from pull range less than ±120 PPM. Document #: 001-09608 Rev. *A Page 11 of 15 [+] Feedback CY24488 DC Parameters [7] Parameter Description Min. Typ. Max. Unit VOH = VDD –0. 5,VDD = 3.3V 12 – – mA VOL = 0.5, VDD = 3.3V 12 – – mA Input High Current VIH = VDD, excluding Vin, XIN/CLKIN – 5 10 µA Input Low Current VIL = 0V, excluding Vin, XIN/CLKIN – 5 10 µA VIH Input High Voltage XIN/CLKIN input CMOS levels 0.7xAVDD – – V VIL Input Low Voltage XIN/CLKIN input CMOS levels – – 0.3xAVD V IOH[8] IOL[8] Output High Current Output Low Current IIH IIL Conditions D VVCXO VIN Input Range CIN Input Capacitance XIN/CLKIN pin only IVDD Supply Current VDD Current CINXIN Input Capacitance at XIN/CLKIN VCXO Disabled External Reference CINXTAL Input Capacitance at Crystal VCXO Disabled Fixed Freq. Oscillator – AVDD – – TBD pF – 60 – mA – 15 – pF – 12 – pF 0 V AC Parameters[7] Parameter Min. Typ. Output Frequency PLL minmax/Dividermaximum 4.2 – 166 MHz Output Duty Cycle (excluding REFOUT Duty Cycle is defined in Figure 9; t2/t1, 50% of VDD 45 50 55 % Output Duty Cycle (excluding REFOUT Duty Cycle is defined in Figure 9; t2/t1, 50% of VDD 40 50 60 % DCREFOUT[8, 9] Output Duty Cycle Duty Cycle is defined in Figure 9; t2/t1, 50% of VDD (XIN/CLKIN Duty Cycle = 45/55%) 40 50 60 % ER[8] Rising Edge Rate Output Clock Edge Rate. Measured from 20% to 80% of VDD. CLOAD = 15 pF. See Figure 10. 0.75 1.2 – V/ns EF[8] Falling Edge Rate Output Clock Edge Rate. Measured from 80% to 20% of VDD. CLOAD = 15 pF See Figure 10. 0.75 1.2 – V/ns T9 Clock Jitter Period Jitter; VDD1 = VDD2 = 3.3V, drive strength = ‘ 10’ – ±250 – ps T10 PLL Lock Time From end of serial programming sequence to correct output frequency – 1 5 ms fXO VCXO Crystal Pull Range Using non-SMD-49 crystal specified in Table 2. Nominal Crystal Frequency Input assumed (0 ppm) @ 25°C and 3.3V ±110 ±120 – ppm Using SMD-49 crystal specified in Table 2. Nominal Crystal Frequency Input assumed (0 ppm) @ 25°C and 3.3V ±105 ±120 – ppm 1/t1 DC1 [8, 9] DC2[8, 9] Description Conditions Max. Units External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is 125 MHz) External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is 125 MHz) Notes 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. 8. Dr i v est r engt hs et t i ngs :‘ 10’f or3. 3Vout put s ;‘ 11’f or2. 5Vout put s. 9. Guaranteed when values in Table 3 and Table 9 are programmed to match the output supply voltage. Document #: 001-09608 Rev. *A Page 12 of 15 [+] Feedback CY24488 Test and Measurement Set-up Figure 8. Test and Measurement Diagram V DDs Outputs DUT C LOAD 0.1F GND Voltage and Timing Definitions Figure 9. Duty Cycle Definition t1 t2 V DD 50% of V DD Clock O utput 0V Figure 10. ER = (0.6 VDD)/t3, EF = (0.6 VDD)/t4 t3 t4 V DD 80% of V DD Clock O utput Document #: 001-09608 Rev. *A 20% of V DD 0V Page 13 of 15 [+] Feedback CY24488 Ordering Information Part Number Type Production Flow Lead-free CY24488ZXC 16-pin TSSOP Commercial, 0°C to +70°C CY24488ZXCT 16-pin TSSOP - Tape and Reel Commercial, 0°C to +70°C Package Drawing and Dimensions Figure 11. 16-lead TSSOP 4.40 mm Body Z16.173 51-85091-*A All product and company names mentioned in this document are trademarks of their respective holders. Document #: 001-09608 Rev. *A Page 14 of 15 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY24488 Document History Page Document Title: CY24488 Quad PLL Clock Generator with Serial Interface (I2C) (Final) Document Number: 001-09608 REV. ECN NO. Issue Date Orig. of Change ** 497098 See ECN RGL New data sheet *A 504259 See ECN RGL Minor text additions Change status from Advance Information to Final Document #: 001-09608 Rev. *A Description of Change Page 15 of 15 [+] Feedback