Revised October 2001 74LVT16646 • 74LVTH16646 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs General Description Features The LVT16646 and LVTH16646 contains sixteen noninverting bidirectional registered bus transceivers providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The DIR inputs determine the direction of data flow through the device. The CPAB and CPBA inputs load data into the registers on the LOW-to-HIGH transition (see Functional Description). ■ Input and output interface capability to systems at 5V VCC The LVTH16646 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. ■ Outputs source/sink −32 mA/+64 mA These transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16646 and LVTH16646 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16646) ■ Also available without bushold feature (74LVT16646) ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Latch-up conforms to JEDEC JED78 ■ ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVT16646MEA (Preliminary) MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT16646MTD (Preliminary) MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16646MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16646MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2001 Fairchild Semiconductor Corporation DS012023 www.fairchildsemi.com 74LVT16646 • 74LVTH16646 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs January 2000 74LVT16646 • 74LVTH16646 Connection Diagram Pin Descriptions Pin Names Description A0–A15 Data Register A Inputs/3-STATE Outputs B0–B15 Data Register B Inputs/3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs SABn, SBAn Select Inputs OE1, OE2 Output Enable Inputs DIRn Direction Control Inputs Truth Table (Note 1) Inputs OE1 DIR1 H X H X H X L H Data I/O CPAB1 CPBA1 SAB1 SBA1 H or L H or L X X X X X X X L H L H L H L L L L X L L X L L X H or L X H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level = LOW-to-HIGH Transition. X A0–7 B0–7 Input Input Output Operation Mode Isolation Clock An Data into A Register X X Clock Bn Data Into B Register L X An to Bn—Real Time (Transparent Mode) X L X X H X A Register to Bn (Stored Mode) X H X Clock An Data into A Register and Output to Bn X H or L Input Output Clock An Data to A Register X L X L Bn to An—Real Time (Transparent Mode) X H B Register to An (Stored Mode) X H Clock Bn into B Register and Output to An Output Input Clock Bn Data into B Register Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control pins. www.fairchildsemi.com 2 In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples shown below demonstrate the four fundamental bus-management functions that can be performed. The direction control (DIRn) determines which bus will receive data when OEn is LOW. In the isolation mode (OEn HIGH), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two busses, A or B, may be driven at a time. Real-Time Transfer Bus B to Bus A Real-Time Transfer Bus A to Bus B OE DIR CPAB CPBA SAB SBA L L X X X OE DIR CPAB CPBA SAB SBA L L H Transfer Storage Data to A or B X X L X Storage OE DIR CPAB CPBA SAB SBA OE DIR CPAB CPBA SAB SBA L L X H or L X H L H H or L X H X 3 L H L L H X H X X X X X L X X L X X X X www.fairchildsemi.com 74LVT16646 • 74LVTH16646 Functional Description 74LVT16646 • 74LVTH16646 Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 4 Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 3) V V V IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State V mA mA mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter Min Max 2.7 3.6 V 0 5.5 V VCC Supply Voltage VI Input Voltage IOH HIGH-Level Output Current −32 IOL LOW-Level Output Current 64 TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Units mA −40 85 °C 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. 5 www.fairchildsemi.com 74LVT16646 • 74LVTH16646 Absolute Maximum Ratings(Note 2) 74LVT16646 • 74LVTH16646 DC Electrical Characteristics Symbol T A = −40°C to +85°C VCC Parameter (V) Min Max Units −1.2 Conditions Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 V IOH = −100 µA 2.7 2.4 V IOH = −8 mA 3.0 2.0 V IOH = −32 mA VOL II(HOLD) 2.7 II = −18 mA VIK Output LOW Voltage Bushold Input Minimum Drive II(OD) Bushold Input Over-Drive (Note 4) Current to Change State II Input Current Data Pins Power Off Leakage Current IPU/PD Power Up/Down 3-STATE VO ≤ 0.1V or V 0.8 VO ≥ VCC − 0.1V 2.7 0.2 V IOL = 100 µA 2.7 0.5 V IOL = 24 mA 3.0 0.4 V IOL = 16 mA 3.0 0.5 V IOL = 32 mA 3.0 0.55 V 3.0 Control Pins IOFF 2.0 3.0 (Note 4) V IOL = 64 mA 75 µA −75 µA VI = 2.0V 500 µA (Note 5) −500 VI = 0.8V µA (Note 6) 3.6 10 µA VI = 5.5V 3.6 ±1 µA VI = 0V or VCC −5 µA VI = 0V 1 µA VI = VCC ±100 µA 3.6 0 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V 0–1.5V ±100 µA IOZL (Note 4) 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.0V IOZL Output Current VI = GND or VCC 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.5V IOZH (Note 4) 3-STATE Output Leakage Current 3.6 5 µA VO = 3.6V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.0V IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < VO ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ VO ≤ 5.5V,Outputs Disabled ∆ICC Increase in Power Supply Current 3.6 0.2 mA (Note 7) One Input at VCC − 0.6V Other Inputs at VCC or GND Note 4: Applies to bushold version only (74LVTH16646) Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter VCC (V) (Note 8) TA = 25°C Min Typ Max Units Conditions CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 9) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 9) Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. www.fairchildsemi.com 6 TA = −40°C to +85°C Symbol CL = 50 pF, RL = 500Ω Parameter VCC = 3.3 ± 0.3V Min fMAX Maximum Clock Frequency 150 tPLH Propagation Delay 1.3 Max VCC = 2.7V Min Max 150 5.4 MHz 1.3 5.9 tPHL CPAB or CPBA to A or B 1.3 5.2 1.3 5.8 tPLH Propagation Delay 1.0 4.4 1.0 4.7 tPHL Data to A or B 1.0 4.6 1.0 5.1 tPLH Propagation Delay 1.0 4.6 1.0 5.4 tPHL SBA or SAB to A or B 1.0 4.8 1.0 5.6 tPZH Output Enable Time 1.0 4.7 1.0 5.4 tPZL OE to A or B 1.0 5.1 1.0 6.0 tPHZ Output Disable Time 2.0 5.6 2.0 6.1 tPLZ OE to A or B 2.0 5.4 2.0 6.1 tPZH Output Enable Time 1.0 4.9 1.0 5.4 tPZL DIR to A or B 1.0 5.4 1.0 6.4 tPHZ Output Disable Time 1.5 6.4 1.5 7.1 1.5 5.4 1.5 5.9 tPLZ DIR to A or B tW Pulse Duration tS Setup Time tH tOSHL CPAB or CPBA HIGH or LOW Hold Time 3.3 3.3 A or B before CPAB or CPBA, Data HIGH 1.2 1.5 A or B before CPAB or CPBA, Data LOW 2.0 2.8 A or B after CPAB or CPBA, Data HIGH 0.5 0.0 A or B after CPAB or CPBA, Data LOW 0.5 0.5 Output to Output Skew (Note 10) tOSLH Units ns ns ns ns ns ns ns ns ns ns 1.0 1.0 1.0 1.0 ns Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance Symbol (Note 11) Typical Units CIN Input Capacitance Parameter VCC = Open, VI = 0V or VCC Conditions 4 pF CI/O Input/Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 7 www.fairchildsemi.com 74LVT16646 • 74LVTH16646 AC Electrical Characteristics 74LVT16646 • 74LVTH16646 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A www.fairchildsemi.com 8 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com 74LVT16646 • 74LVTH16646 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)