Revised June 2005
74VCXH162373
Low Voltage 16-Bit Transparent Latch with Bushold
and 26: Series Resistors in Outputs
General Description
Features
The VCXH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state.
The VCXH162373 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The VCXH162373 is also designed with 26: series resistors in the outputs. This design reduces line noise in applications such as memory address driver, clock drivers and
bus transceivers/transmitters.
The 74VCXH162373 is designed for low voltage (1.4V to
3.6V) VCC applications with output compatibility up to 3.6V.
■ 1.4V to 3.6V VCC supply operation
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■ 26: series resistors in outputs
■ tPD (In to On)
3.3 ns max for 3.0V to 3.6V VCC
■ Static Drive (IOH/IOL)
r12 mA @ 3.0V VCC
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model ! 2000V
Machine model ! 200V
The 74VCXH162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
Ordering Code:
Ordering Number
Package
Package Description
Number
74VCXH162373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74VCXH162373MTX
(Note 1)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
Pin Descriptions
Pin Names
OEn
Output Enable Input (Active LOW)
LEn
Latch Enable Input
I0–I15
O0–O15
© 2005 Fairchild Semiconductor Corporation
DS500227
Description
Bushold Inputs
Outputs
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74VCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26: Series Resistors in Outputs
January 2000
74VCXH162373
Connection Diagram
Truth Tables
Inputs
Outputs
LE1
OE1
I0–I7
O0–O7
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
Inputs
H
L
X
Z
O0
Outputs
LE2
OE2
I8–I15
O8–O15
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
HIGH Voltage Level
LOW Voltage Level
Immaterial (HIGH or LOW, control inputs may not float)
High Impedance
Previous O0 before HIGH-to-LOW of Latch Enable
Functional Description
The 74VCXH162373 contains sixteen edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the In enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
its I input changes. When LEn is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LEn. The
3-STATE outputs are controlled by the Output Enable
(OEn) input. When OEn is LOW the standard outputs are in
the 2-state mode. When OEn is HIGH, the standard outputs
are in the high impedance mode but this does not interfere
with entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions (Note 4)
0.5V to 4.6V
0.5V to 4.6V
Supply Voltage (VCC )
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Outputs 3-STATED
Outputs Active (Note 3)
DC Input Diode Current (IIK) VI 0V
0.5V to 4.6V
0.5V to VCC 0.5V
50 mA
Operating
1.4V to 3.6V
Input Voltage
0.3V to VCC
Output Voltage (VO)
Output in Active States
DC Output Diode Current (IOK)
VO 0V
50 mA
50 mA
VO ! VCC
r50 mA
(IOH/IOL)
DC VCC or GND Current per
Storage Temperature Range (TSTG)
0.0V to 3.6V
Output Current in IOH/IOL
DC Output Source/Sink Current
Supply Pin (ICC or GND)
0V to VCC
Output in 3-STATE
r100 mA
65qC to 150qC
VCC
3.0V to 3.6V
VCC
2.3V to 2.7V
VCC
1.65V to 2.3V
VCC
1.4V to 1.6V
Free Air Operating Temperature (TA)
r12 mA
r8 mA
r3 mA
r1 mA
40qC to 85qC
Minimum Input Edge Rate ('t/'V)
VIN
0.8V to 2.0V, VCC
3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
VIH
VIL
Parameter
Conditions
HIGH Level Input Voltage
VCC
(V)
2.7 - 3.6
LOW Level Input Voltage
Min
HIGH Level Output Voltage
1.6
1.65 - 2.3
0.65 x VCC
1.4 - 1.6
0.65 x VCC
2.7 - 3.6
IOH
100 PA
IOH
IOH
V
0.8
2.3 - 2.7
0.7
1.65 - 2.3
0.35 x VCC
V
0.35 x VCC
2.7 - 3.6
VCC - 0.2
6 mA
2.7
2.2
8 mA
3.0
2.4
IOH
12 mA
3.0
2.2
IOH
100 PA
2.7 - 3.6
VCC - 0.2
IOH
4 mA
2.3
2.0
IOH
6 mA
2.3
1.8
IOH
8 mA
IOH
100 PA
IOH
3 mA
IOH
100 PA
IOH
1 mA
3
Units
2.0
2.3 - 2.7
1.4 - 1.6
VOH
Max
2.3
1.7
1.65 - 2.3
VCC - 0.2
1.65
1.25
1.4 - 1.6
VCC - 0.2
1.4
1.05
V
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74VCXH162373
Absolute Maximum Ratings(Note 2)
74VCXH162373
DC Electrical Characteristics
Symbol
(Continued)
Parameter
Conditions
VCC
Min
Max
Units
(V)
VOL
II
II(HOLD)
II(OD)
IOZ
LOW Level Output Voltage
Input Leakage Current
IOL
100 PA
IOL
6 mA
IOL
IOL
2.7 - 3.6
0.2
2.7
0.4
8 mA
3.0
0.55
12 mA
3.0
0.8
IOL
100 PA
2.3 - 2.7
0.2
IOL
6 mA
2.3
0.4
IOL
8 mA
2.3
0.6
IOL
100 PA
IOL
3 mA
IOL
100 PA
IOL
1 mA
Control Pins
0 d VI d 3.6V
Data Pins
VI
VCC or GND
1.65 - 2.3
0.2
1.65
0.3
1.4 - 1.6
0.2
1.4
0.35
1.4 - 3.6
r5.0
PA
1.4 - 3.6
r5.0
PA
Bushold Input Minimum
VIN
0.8V
3.0
75
Drive Hold Current
VIN
2.0V
3.0
75
VIN
0.7V
2.3
45
VIN
1.6V
2.3
45
VIN
0.57V
1.65
25
VIN
1.07V
1.65
25
Bushold Input Over-Drive
(Note 5)
3.6
450
Current to Change State
(Note 6)
3.6
450
(Note 5)
2.7
300
(Note 6)
2.7
300
(Note 5)
1.95
200
(Note 6)
1.95
200
3-STATE Output Leakage
0 d VO d 3.6V
VI
VIH or VIL
IOFF
Power-OFF Leakage Current
0 d (VO) d 3.6V
ICC
Quiescent Supply Current
VI
'ICC
Increase in ICC per Input
VIH
VCC or GND
VCC d (VO) d 3.6V (Note 7)
VCC 0.6V
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: Outputs disabled or 3-STATE only.
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4
V
1.4 - 3.6
PA
PA
r10
PA
PA
0
10
1.4 - 3.6
20
1.4 - 3.6
r20
2.7 - 3.6
750
PA
PA
Symbol
Parameter
tPHL
Propagation Delay
tPLH
In to On
tPHL
Propagation Delay
tPLH
LE to On
tPZL
Output Enable Time
Conditions
CL
30 pF, RL
500:
Output Disable Time
tH
tW
Setup Time
Hold Time
Pulse Width
tOSHL
Output to Output Skew
tOSLH
(Note 9)
Max
3.3 r 0.3
0.8
3.3
2.5 r 0.2
1.0
4.5
1.8 r 0.15
1.5
9.0
2k:
1.5 r 0.1
1.0
18.0
CL
30 pF, RL
500:
3.3 r 0.3
0.8
3.6
2.5 r 0.2
1.0
4.9
1.8 r 0.15
1.5
9.8
CL
30 pF, RL
500:
1.5 r 0.1
1.0
19.6
CL
30 pF, RL
500:
3.3 r 0.3
0.8
3.9
2.5 r 0.2
1.0
5.4
1.8 r 0.15
1.5
9.8
CL
30 pF, RL
2k:
1.5 r 0.1
1.0
19.6
CL
30 pF, RL
500:
3.3 r 0.3
0.8
4.0
2.5 r 0.2
1.0
4.4
1.8 r 0.15
1.5
7.9
15.8
CL
30 pF, RL
2k:
1.5 r 0.1
1.0
CL
30 pF, RL
500:
3.3 r 0.3
1.5
2.5 r 0.2
1.5
1.8 r 0.15
2.5
CL
30 pF, RL
500:
1.5 r 0.1
3.0
CL
30 pF, RL
500:
3.3 r 0.3
1.0
2.5 r 0.2
1.0
1.8 r 0.15
1.0
CL
30 pF, RL
500:
1.5 r 0.1
2.0
CL
30 pF, RL
500:
3.3 r 0.3
1.5
2.5 r 0.2
1.5
1.8 r 0.15
4.0
4.0
CL
30 pF, RL
500:
1.5 r 0.1
CL
30 pF, RL
500:
3.3 r 0.3
CL
Note 8: For CL
40qC to 85qC
Min
30 pF, RL
tPHZ
tS
TA
(V)
CL
tPZH
tPLZ
VCC
30 pF, RL
2k:
Units
ns
Figure
Number
Figures
1, 2
Figures
7, 8
ns
Figures
1, 2
Figures
7, 8
ns
Figures
1, 3, 4
Figures
7, 9, 10
ns
Figures
1, 3, 4
Figures
7, 9, 10
ns
Figure 6
ns
Figure 6
ns
Figure 5
0.5
2.5 r 0.2
0.5
1.8 r 0.15
0.75
1.5 r 0.1
1.5
ns
50PF, add approximately 300 ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
5
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74VCXH162373
AC Electrical Characteristics (Note 8)
74VCXH162373
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
VOHV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
Conditions
CL
CL
CL
30 pF, VIH
30 pF, VIH
30 pF, VIH
VCC, VIL
VCC, VIL
VCC, VIL
0V
0V
0V
VCC
TA 25qC
(V)
Typical
1.8
0.15
2.5
0.25
3.3
0.35
1.8
0.15
2.5
0.25
3.3
0.35
1.8
1.55
2.5
2.05
3.3
2.65
Units
V
V
V
Capacitance
Symbol
Parameter
Conditions
CIN
Input Capacitance
VCC
COUT
Output Capacitance
VI
0V or VCC, VCC
1.8V, 2.5V or 3.3V, VI
CPD
Power Dissipation Capacitance
VI
0V or VCC, f
VCC
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Typical
Units
0V or VCC
6
pF
1.8V, 2.5V or 3.3V
7
pF
20
pF
10 MHz,
1.8V, 2.5V or 3.3V
6
TA 25qC
74VCXH162373
AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC
VCC x 2 at VCC
tPZH, tPHZ
3.V3 r 0.3V;
2.V5 r 0.2V; 1.8V r 0.15V
GND
FIGURE 1. AC Test Circuit
FIGURE 3. 3-STATE Output HIGH Enable and
Disable Times for Low Voltage Logic
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
tREC Waveforms
Symbol
VCC
3.3V r 0.3V
2.5V r 0.2V
1.8V r 0.15V
Vmi
1.5V
VCC/2
VCC/2
Vmo
1.5V
VCC/2
VCC/2
VX
VOL 0.3V
VOL 0.15V
VOL 0.15V
VY
VOH 0.3V
VOH 0.15V
VOH 0.15V
7
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74VCXH162373
AC Loading and Waveforms (VCC 1.5V r 0.1V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VCC x 2 at VCC
tPZH, tPHZ
1.5 r 0.1V
GND
FIGURE 7. AC Test Circuit
FIGURE 8. Waveform for Inverting and Non-Inverting Functions
FIGURE 9. 3-STATE Output HIGH Enable and Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V r 0.1V
VCC/2
Vmi
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Vmo
VCC/2
VX
VOL 0.1V
VY
VOH 0.1V
8
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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74VCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26: Series Resistors in Outputs
Physical Dimensions inches (millimeters) unless otherwise noted