Revised March 2000 DM74AS169A Synchronous 4-Bit Binary Up/Down Counter General Description Features These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74AS169 is a 4-bit binary up/down counter. The carry output is decoded to prevent spikes during normal mode of counting operation. Synchronous operation is provided so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive going) edge of clock input waveform. ■ Switching Specifications at 50 pF These counters are fully programmable; that is, the outputs may each be preset either HIGH or LOW. The load input circuitry allows loading with carry-enable output of cascaded counters. As loading is synchronous, setting up a LOW level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. ■ Switching Specifications guaranteed over full temperature and VCC range ■ Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Functionally and pin-for-pin compatible with Schottky and low power Schottky TTL counterpart ■ Improved AC performance over Schottky and low power Schottky counterparts ■ Synchronously programmable ■ Internal look ahead for fast counting ■ Carry output for n-bit cascading ■ Synchronous counting ■ Load control line ■ ESD inputs The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating. Both count enable inputs (P and T) must be LOW to count. The direction of the count is determined by the level of the up/down input. When the input is HIGH, the counter counts UP; when LOW, it counts DOWN. Input T is fed forward to enable the carry outputs. The carry output thus enabled will produce a LOW level output pulse with a duration approximately equal to the HIGH portion of the QA output when counting UP, and approximately equal to the LOW portion of the QA output when counting DOWN. This LOW level overflow carry pulse can be used to enable successively cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. The control functions for these counters are fully synchronous. Changes at control inputs (enable P, enable T, load, up/down) which modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable setup and hold times. Ordering Code: Order Number Package Number Package Description DM74AS169AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74AS169AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS006292 www.fairchildsemi.com DM74AS169A Synchronous 4-Bit Binary Up/Down Counter April 1984 DM74AS169A Connection Diagram Logic Diagram DM74AS169A www.fairchildsemi.com 2 Supply Voltage 7V Input Voltage 7V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Typical θJA N Package 71.5°C/W M Package 101.0°C/W Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.5 5 5.5 V VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −2 mA IOL LOW Level Output Current fCLK Clock Frequency tSU tsetup, Set-up Time V 0 thold, Hold Time tH 2 20 mA 75 MHz Data; A, B, C, D 8 ns En P, En T 8 ns LOAD 8 ns U/D 11 ns Data; A, B, C, D 0 ns En P, En T 0 ns LOAD 0 ns U/D 0 ns 6.7 ns tWCLK Width of Clock Pulse tA Free Air Operating Temperature 0 °C 70 Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C Symbol Parameter Conditions VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA VOH HIGH Level IOH = −2 mA, Output Voltage VCC = 4.5V to 5.5V LOW Level VCC = 4.5V, Output Voltage IOL = 20 mA VOL II IIH IIL Min Typ Max Units −1.2 V VCC − 2 V 0.35 0.5 Input Current @ Max VCC = 5.5V, LOAD, ENT, U/D 0.2 Input Voltage VIH = 7V Others 0.1 HIGH Level Input Current VCC = 5.5V, LOAD, ENT, U/D 40 VIH = 2.7V Others 20 VCC = 5.5V, CLK, DATA, ENP −0.5 VIL = 0.4V LOAD, ENT, U/D −1 LOW Level Input Current IO (Note 2) Output Drive Current VCC = 5.5V, VO = 2.25V ICC Supply Current VCC = 5.5V −30 46 V mA µA mA −112 mA 63 mA Note 2: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, I OS. 3 www.fairchildsemi.com DM74AS169A Absolute Maximum Ratings(Note 1) DM74AS169A Switching Characteristics over recommended operating free air temperature range Symbol Parameter Conditions fMAX Maximum Clock Frequency VCC = 4.5V to 5.5V tPLH Propagation Delay Time RL = 500Ω LOW-to-HIGH Level Output CL = 50 pF tPHL From Propagation Delay Time Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time Max Propagation Delay Time MHz RIPPLE Carry 3 16.5 ns Clock RIPPLE Carry 2 13 ns Clock Any Q 1 7 ns Clock Any Q 2 13 ns En T RIPPLE Carry 1.5 9 ns En T RIPPLE Carry 1.5 9 ns RIPPLE Carry 2 12 ns RIPPLE Carry 2 13 ns (Note 3) U/D HIGH-to-LOW Level Output Units Clock U/D LOW-to-HIGH Level Output tPHL Min 75 HIGH-to-LOW Level Output tPLH To (Note 3) Note 3: Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is maximum, the ripple carry output will be out of phase. www.fairchildsemi.com 4 DM74AS169A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com DM74AS169A Synchronous 4-Bit Binary Up/Down Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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