Revised February 2005 74VHC132 Quad 2-Input NAND Schmitt Trigger General Description Features The VHC132 is an advanced high speed CMOS 2-input NAND Schmitt Trigger Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the VHC00 but the inputs have hysteresis between the positive-going and negative-going input thresholds, which are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Thus greater noise margin then conventional gates is provided. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. ■ High Speed: tPD 3.9 ns (typ) at VCC 5V ■ Power down protection is provided on all inputs ■ Low power dissipation: ICC ■ Low noise: VOLP 2 PA (max) at TA 25qC 0.8 V (max) ■ Pin and function compatible with 74HC132 Ordering Code: Order Number Package Package Description Number 74VHC132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC132SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC132MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC132MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC132N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. © 2005 Fairchild Semiconductor Corporation DS012124 www.fairchildsemi.com 74VHC132 Quad 2-Input NAND Schmitt Trigger September 1995 74VHC132 Connection Diagram Logic Diagram Truth Table Pin Descriptions Pin Names Description A B Y L L H An, Bn Inputs L H H Yn Outputs H L H H H L www.fairchildsemi.com 2 Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Recommended Operating Conditions (Note 3) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r50 mA 65qC to 150qC 0V to 5.5V Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Lead Temperature (TL) 260qC (Soldering, 10 seconds) 2.0V to 5.5V Supply Voltage (VCC) Input Voltage (VIN) Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VP VN VH VOH VOL Parameter VCC (V) TA Min 25qC Typ TA Max 40qC to 85qC Min 3.0 2.20 2.20 Threshold Voltage 4.5 3.15 3.15 5.5 3.85 3.85 Negative 3.0 0.90 0.90 Threshold Voltage 4.5 1.35 1.35 5.5 1.65 1.65 3.0 0.30 1.20 0.30 1.20 Output Voltage 4.5 0.40 1.40 0.40 1.40 5.5 0.50 1.60 0.50 1.60 HIGH Level 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 LOW Level Output Voltage IIN Input Leakage Current ICC Quiescent Supply Current 2.0 Conditions V V Hysteresis Output Voltage Units Max Positive V VIN V VIH IOH 50 PA IOH 4 mA or VIL 4.4 V 0.0 0.1 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 VIN V VIH IOH 8 mA IOL 50 PA IOL 4 mA IOL 8 mA or VIL 3.0 0.36 0.44 4.5 0.36 0.44 0–5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 2.0 20.0 PA VIN VCC or GND 3 V www.fairchildsemi.com 74VHC132 Absolute Maximum Ratings(Note 2) 74VHC132 Noise Characteristics Symbol VOLP Parameter Quiet Output Maximum (Note 4) Dynamic VOL VOLV Quiet Output Maximum (Note 4) Dynamic VOL VIHD Maximum HIGH Level (Note 4) Dynamic Input Voltage VILD Maximum LOW Level (Note 4) Dynamic Input Voltage TA 25qC VCC (V) Typ Limit 5.0 0.3 0.8 V CL 50 pF 5.0 0.3 0.8 V CL 50 pF 5.0 3.5 V CL 50 pF 5.0 1.5 V CL 50 pF Units Conditions Note 4: Parameter guaranteed by design AC Electrical Characteristics Symbol tPHL Parameter Propagation Delay VCC (V) 3.3 r 0.3 tPLH 5.0 r 0.5 TA Min 25qC Typ TA Max 40qC to 85qC Min Max 6.1 11.9 1.0 14.0 8.0 15.4 1.0 17.5 3.9 7.7 1.0 9.0 5.9 9.7 1.0 11.0 10 CIN Input Capacitance 4 CPD Power Dissipation 16 10 Units ns ns Conditions CL 15 pF CL 50 pF CL 15 pF CL 50 pF pF VCC pF (Note 5) Open Capacitance Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained from the equation: ICC (opr.) CPD * VCC * IIN I CC/4 (per gate) www.fairchildsemi.com 4 74VHC132 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com 74VHC132 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74VHC132 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com 74VHC132 Quad 2-Input NAND Schmitt Trigger Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8