LM3655 Charge Control and Protection IC for embedded single cell Li-Ion/Polymer batteries 1.0 General Description 3.0 Features The LM3655 provides complete charge control, discharge control and battery safety of a single Lithium-Ion cell. It supports battery charging by using a variety of power supply types including unregulated current-limited wall adapters, regulated wall adapters and vehicle power adapters. Charge current control is achieved using an external bipolar PNP power transistor. n n n n n Furthermore, the LM3655 provides effective and comprehensive discharge control functionality. All operating load current is supplied by the Li-Ion battery and passes through this IC. This allows the battery power to disconnect due to overload, short-circuit or low battery conditions. The IC also offers extensive battery safety protection against overvoltage and over-current. The internal safety circuit is backed up by an identical circuit to provide safety redundancy. The LM3655 requires minimal external components and is packaged in a micro surface mount device for integration in a single cell battery pack. 2.0 Key Specifications n n n n n n n n n 1% precision pin-selectable nominal 4.10V and 4.16V termination voltages n Up to 1.2A full-rate charge current n Safety Shunt voltage 4.35V n 800 mW power regulation of external PNP at 25˚C allows operation up to 30V (peak-to-peak) and 18V DC Input over-voltage protection for load and battery pack Input over-current protection for load and battery pack Reverse current protection Reverse charger protection Input short circuit protection that protects the cell from a short on the charger-connector Output overload current and short circuit protection Complete charge control with pre-charging for depleted batteries, full-rate and trickle charging. Support for charging with regulated and non-regulated wall adapters and vehicle power adapters. Power regulation of the external Power PNP Chemistry selection for Li-ion and Li-polymer Complete linear Peak detector function for filtering ripple on input power supply Digital filtering of the cell voltage transients during transmit pulses when LM3655 is used in a battery pack for cell phones. 25-pin, 2.5 mm x 2.5 mm microSMD package for mounting on four layered PCB inside the battery pack. 4.0 Applications n Cell phones and other portable applications which use embedded Li-ion batteries 5.0 Typical Application Circuit 20111501 Because the LM3655 and associated external components provide safety protection for both the Li-Ion cell and the phone circuitry, appropriate precautions must be taken in system design and layout to ensure proper operation. © 2004 National Semiconductor Corporation DS201115 www.national.com LM3655 Charge Control and Protection IC for embedded single cell Li-Ion/Polymer batteries November 2004 LM3655 Table of Contents 1.0 General Description ..................................................................................................................................... 1 2.0 Key Specifications ........................................................................................................................................ 1 3.0 Features ....................................................................................................................................................... 1 4.0 Applications .................................................................................................................................................. 1 5.0 Typical Application Circuit ............................................................................................................................ 1 6.0 Connection Diagrams and Package Marking .............................................................................................. 3 7.0 LM3655 Pin Description ............................................................................................................................... 3 8.0 Ordering Information .................................................................................................................................... 4 9.0 Operation Description .................................................................................................................................. 4 10.0 Pin Functions ............................................................................................................................................. 4 10.1 VIN ............................................................................................................................................................ 4 10.2 CELL ........................................................................................................................................................ 4 10.3 RADIO_B+ ............................................................................................................................................... 4 10.4 VDETECT ................................................................................................................................................... 5 10.5 DISABLE ................................................................................................................................................. 5 10.6 CHEMISTRY ............................................................................................................................................ 5 10.7 HIB_EN .................................................................................................................................................... 5 10.8 HIS_DIS ................................................................................................................................................... 5 10.9 BATT_DETB ............................................................................................................................................ 5 10.10 CHRG_STATE ....................................................................................................................................... 5 10.11 CHRG_DET ........................................................................................................................................... 5 10.12 CNTRL ................................................................................................................................................... 5 10.13 EXT_PWR_ON ...................................................................................................................................... 6 11.0 Charge Control Functions .......................................................................................................................... 6 11.1 GENERAL OPERATION .......................................................................................................................... 6 11.2 EXTERNAL POWER SUPPLY DETECT ................................................................................................. 6 11.2.1 VDETECT Circuit ................................................................................................................................... 6 11.2.2 Debounce Function ............................................................................................................................ 7 11.2.3 Power Supply Test Pulses ................................................................................................................. 8 11.2.4 Low Cell Voltage Charging (Pre-Charging) ....................................................................................... 9 11.2.5 Full-Rate Charging ........................................................................................................................... 10 11.2.6 Trickle/Top-Off Mode ........................................................................................................................ 11 11.2.7 Peak Detector Function .................................................................................................................... 11 12.0 Discharge Control Functions .................................................................................................................... 12 12.1 GENERAL DESCRIPTION .................................................................................................................... 12 12.2 RADIO+ GENERATION ........................................................................................................................ 12 12.3 UNDER-VOLTAGE CUT-OFF ............................................................................................................... 13 12.4 POWER CUT OPERATION .................................................................................................................. 13 12.5 HIBERNATION MODE .......................................................................................................................... 13 13.0 Safety Functions ...................................................................................................................................... 13 13.1 INPUT OVER-VOLTAGE PROTECTION .............................................................................................. 13 13.1.1 Normal Operation (Q1 Control) ....................................................................................................... 13 13.1.2 Safety Shunt/Crowbar Operation ..................................................................................................... 14 13.1.3 Standby Shunt Mode ....................................................................................................................... 14 13.1.4 Thermal Crowbar Mode ................................................................................................................... 14 13.1.5 Fast Shunt Operation ...................................................................................................................... 14 13.1.6 Shunt Circuit Parametric Specifications .......................................................................................... 14 13.2 SCHOTTKY ELIMINATION MODE (CHARGER INPUT SHORT CIRCUIT/REVERSE CURRENT PROTECTION) ...................................................................................................................................................... 15 13.3 REVERSE CHARGER PROTECTION .................................................................................................. 15 13.4 OUTPUT CURRENT OVERLOAD PROTECTION (“PTC” MODE) ...................................................... 15 13.5 OUTPUT SHORT CIRCUIT CURRENT PROTECTION ....................................................................... 15 14.0 Required External Components ............................................................................................................... 17 14.1 CHARGE PASS TRANSISTOR (Q1) .................................................................................................... 17 14.2 DRIVER TRANSISTOR AND BIAS RESISTORS (R2, R3 AND R5) .................................................... 17 14.3 EXTERNAL CHARGER SENSE RESISTOR (R4) ................................................................................ 17 14.4 CAPACITORS ........................................................................................................................................ 17 14.5 FUSE (F1) ............................................................................................................................................. 17 15.0 Electrical Characteristics .......................................................................................................................... 17 15.1 GENERAL SPECIFICATION AND ABSOLUTE MAXIMUM RATINGS ................................................ 17 15.2 PASS DEVICE AND POWER SUPPLY RATINGS ............................................................................... 18 15.3 IC PIN ELECTRICAL CHARACTERISTICS ......................................................................................... 18 www.national.com 2 LM3655 Table of Contents (Continued) 16.0 Physical Dimensions ................................................................................................................................ 21 6.0 Connection Diagrams and Package Marking 20111502 20111503 MicroSMD Top View See NS Package Number TLA25 MicroSMD Bottom View 7.0 LM3655 Pin Description Pin # Name I/O Type Description A1 CHEMISTRY Input Logic A low input sets the constant voltage and termination voltage to the lower VTERML. A high input sets the constant voltage to the higher voltage level VTERMH. This pin has an internal 100 kΩ pull-down resistor and can be controlled by a peripheral IC or can be tied directly to B+ or GND. A2 HIB_DISB Input Logic This pin is internally pulled up to the CELL pin by a 100K resistor. When this pin is momentarily pulsed low, Hibernate mode is exited, which turns on M4. A3 HIB_EN Input Analog The IC is configured in hibernation mode, when this pin is pulled high after a debounce period. Activating hibernation mode turns off the internal M4 transistor. A4 EXT_PWR_ON Output Logic EXT_PWR_ON is a push-pull output. It is a logic 1 (Radio_B+ voltage level) when the cell has reached the Vphone_on level (nominally 3.0V) while the charger is connected and the battery is present. A5 CNTRL Output Analog This output pin regulates the charger current by controlling the base voltage of the external drive and pass transistors Q2 and Q1. B1, C1, C2, D1 RADIO Output Analog This is the power supply terminal for the phone. ALL load current from the cell must be sourced from this pin. B2 NC B3, C3, D3 CELL I/O Analog These pins need to be connected to the cell’s positive terminal. B4, C4, D4 VIN Input Analog Input from the pass transistor Q1. B5, C5, D5 GND Ground D2 NC E1 DISABLE This pin must be left floating. It needs to be connected to a non connected PCB pad for heat sinking. It cannot be connected to other NC pins. Ground pin for the circuit and CELLThis pin must be left floating. It needs to be connected to a non connected PCB pad for heat sinking. It cannot be connected to other NC pins. Input Logic A logic high applied to this input disables the charging. A logic low enables it. This pin has an internal 100 KΩ pull-down resistor and can be left unconnected. 3 www.national.com LM3655 7.0 LM3655 Pin Description (Continued) Pin # Name I/O Type Description E2 BATT_DETB Input Logic This pin is used to detect the presence of a battery. When the battery is missing, the internal 100K resistor will pull up this pin to the voltage on CELL. When the battery is present, this pin should be pulled low. E3 CHRG_STATE Output Open Drain This pin is used to indicate the charge status. An external 30K pull-up resistor needs to be connected between this pin and RADIO+ if output on this pin is desired. A low output signifies that the IC is charging the battery cell in full-rate mode. A high output indicates that trickle/top-off charging is in process. The output is also high when the charger is disabled (DIS pin tied high). E4 CHRG_DETB Output Open Drain An external 30K pull-up resistor needs to be connected between this pin and RADIO+ if output on this pin is desired. The CHRG_DETB indicates whether an external power supply has been detected (output = low) or not (output = high). E5 VDET Input Analog VDET provides the internal control with a signal that is proportional to the external voltage level and also provides power to the internal control circuitry. 8.0 Ordering Information Order Number LM3655TL LM3655TLX Packaging Type 25-bump Wafer Level Chip Scale (micro SMD) NSC Package Marking (*) Supplied As XY TT S50 250 units, Tape-and-Reel XY TT S50 3000 units, Tape-and-Reel (*) XY - denotes the date code marking (2 digits) in production (*) TT - refers to die/lot tracking for production (*) S - product line designator Package markings may change over the course of production 9.0 Operation Description Refer to Typical Application Circuit for external and internal component reference designators such as Q1, M5, etc. 10.0 Pin Functions 10.1 VIN VIN is the input pin for the charging current from the external power source to the battery/cell. When the phone is operating from an external supply, cell phone operating current also passes through this pin. Total input current into the VIN pin is internally sensed by monitoring the voltage drop across the series sensing FET M5. VIN is derived from the output (collector) of Q1, and not directly connected to the external source. If the external power supply (VPS) potential exceeds a maximum safe limit, Q1 will be controlled to protect the cell and phone circuits from over-voltage. Q1 provides the primary over-voltage protection mechanism for the phone circuits and the cell. 10.2 CELL CELL is connected directly to the battery/cell positive terminal. Under normal operation of the phone, it serves as the main power supply pin for the LM3655. When the phone is drawing current from the battery, current will flow into this pin and out through the internal FET M4 to supply the phone’s operating rail (RADIO_B+). When connected to an external supply to charge the battery, current will flow through M5 and out of this pin into the cell. If the phone is being operated while connected to an external power supply, the phone’s operating current (current out of the RADIO_B+ pin) will be the sum of the currents into the CELL and VIN pins. 10.3 RADIO_B+ All power for the phone’s operation (other than battery charging) is derived from this pin. The phone’s operating current flows through M4, which is controlled and monitored to prevent overload or short-circuit currents, and disabled during cell under-voltage conditions. www.national.com 4 LM3655 10.0 Pin Functions (Continued) 10.4 VDETECT This pin is coupled to the external power supply through a series resistance (R4). It is used to determine when an external source (charger) is connected, which in turn initiates the device’s charge control logic. The CHRG_DETB output is set based on input to this pin. 10.5 DISABLE The phone can stop the charge current through use of the DISABLE logic input pin of the IC. Asserting a logic high on the DISABLE Pin of the IC will force the control pin (CNTRL) to turn off the external Drive (Q2) and Pass (Q1) transistors so there is no charge current to the cell. The DISABLE input can be driven high by the phone’s logic at any time to interrupt the charge current. Use of the DISABLE pin during charging can allow the phone to measure the cell’s true voltage by peripheral circuitry (without the presence of charge current input) if desired. Additionally, a high-to-low transition on the DISABLE pin (thus re-enabling the charger operation), will reset the charge control state machine. 10.6 CHEMISTRY The CHEMISTRY pin provides a logic input to the IC that determines the termination threshold for Li-ion cell charging. A logic low applied to this pin selects the lower charging threshold or termination voltage (VTERML), a logic high selects the higher charging threshold (VTERMH). Because different cell types may require slightly different charge termination thresholds, the LM3655 supports a pinprogrammable selection between two different settings. The lower threshold is nominally 4.10V, and the higher threshold is nominally 4.16V. 10.7 HIB_EN This pin provides a logic input to the IC that when held high during a debounce period of 32 mS, M4 will be latched open even if the cell voltage is above VCHARGE_LOW. This pin has a 10K pull-down resistor internal to the IC so that the IC will default on. 10.8 HIS_DIS This pin provides a logic input to the IC that when held low momentarily, the latch holding M4 open is cleared allowing it to be closed when the cell voltage is above VCHARGE_LOW. This pin has a 100K pullup resistor to the CELL pin internal to the IC. 10.9 BATT_DETB BATT_DETB indicates to the LM3655 IC that a cell is present in the system. This pin provides a logic input to the IC that when held low, the IC will be able to detect the presence of a charger. There is a 100K pull-up resistor internal to the IC on this pin, which is supplied from the charger (not from the cell). A series 10K resistor is to be used between this pin and the removable battery to protect the IC against ESD. 10.10 CHRG_STATE CHRG_STATE is an open-drain logic output to the phone, and can be used to provide a simple battery-metering indication during charge mode. During charge mode, with current flowing into the cell, the Li-ion cell voltage cannot be used for an accurate indication of state of charge. If a battery is at a relatively low state of charge, it will remain in the “full-rate” charge mode for some period of time when connected to the external power supply. When the cell reaches a higher state of charge, the charge control switches to the trickle/top-off mode. Thus, this signal is logic low during full-rate charge mode and high during the trickle/top-off mode. The exact percentage of “full” at this crossover point will vary depending on many conditions, primarily full-rate charge current level, but is expected to be > 60% for typical use with a mid-rate charger. This information can be used to provide a simple “charging” or “ready” indication by the system for the battery status meter during charge. If combined with a timer, or other means of interaction by the system (such as periodic control of the DISABLE pin combined with cell voltage measurements during periods of no current flow) a more complete metering method may be implemented if desired. 10.11 CHRG_DET This is an open-drain output to the phone’s power management IC that indicates the connection of an external power supply. Typical application uses a 30K pull-up resistor to RADIO_B+. When a charger is detected, this output is pulled LOW by the internal logic of the LM3655. This signal may be pulled up to a low-voltage logic rail such as 2.75V or 1.8V regulated voltage. It is assumed that the voltage used to pull-up is no higher than the cell voltage. 10.12 CNTRL This is an analog output to control Q2, the NPN drive transistor. The CNTRL output is adjusted to deliver the appropriate level of current required by the charge algorithm for full-rate or trickle/top-off charging. During full-rate charging, CNTRL is set such that Q1 will be saturated. During trickle/top-off mode, CNTRL will be set in order to maintain the appropriate cell clamp voltage (4.10V or 4.16V as desired). Furthermore, if the power-monitoring circuit determines that excess power is being dissipated in, the CNTRL signal will be further reduced to limit current flowing through Q1. This ensures that the Q1 pass device remains within safe power dissipation limits. 5 www.national.com LM3655 10.0 Pin Functions (Continued) 10.13 EXT_PWR_ON EXT_PWR_ON is a digital push-pull output. A logic 1, referenced to the Radio_B+ level is output when Vcell exceeds Vphone_on (nominally 3.00V) and CHRG_DETB = 0 (charger presence is detected) and BATT_DETB is low. Otherwise, EXT_PWR_ON is held low to prevent the phone from attempting to turn on due to charger connection when there is either no battery present or when the battery is not charged enough for the phone to operate. 11.0 Charge Control Functions 11.1 GENERAL OPERATION The LM3655 circuit is able to operate with different types of charge power supplies with a wide range of input voltage and currents, including but not limited to unregulated current limited wall adapters, regulated wall adapters and Vehicle Power Adapters with 1A of current limit. The IC protects itself from high voltages by using Q1 and Q2 to stand off these voltages. It also uses resistors to current limit the VDETECT pin. High currents are handled by using current regulation during both the full-rate and the trickle/top-off phases of charging the battery. Power dissipation in Q1 is controlled using a constant-power control circuit within the IC. The LM3655 has multiple modes of operation for charging and protecting the embedded cell. The three basic modes of operation are low voltage charging, full-rate charging, and trickle charging. During the charge process, the power dissipation in the pass element Q1 is monitored and controlled to a safe maximum limit by reducing charge current as necessary. Because of quantization error or power supply voltage fluctuations, the power-limiting circuit may (in some cases) reduce cell current to a level lower than necessary for extended periods of time. To counteract this, the IC periodically activates a charger test pulse during the full-rate and trickle charging modes. This allows the power supply to deliver full-rate current, although the cell voltage is always regulated such that it does not exceed the termination voltage (4.10V or 4.16V as determined by the CHEMISTRY pin). The test pulse allows the cell to be charged at the fastest possible rate by allowing the charge control to re-enter the full-rate charge (Q1 saturated) mode whenever possible. The test pulses are enabled during full-rate and trickle/ top-off charge modes, have a nominal duration of 256 mS, and are repeated every 64 seconds. This is referred to as ‘burp’ mode. Figure 1 shows the cell voltage thresholds used in the selection of the charging modes. The horizontal (time) axis is intended to illustrate the progression of a complete charge/discharge cycle of operation. 20111504 FIGURE 1. Voltage Thresholds 11.2 EXTERNAL POWER SUPPLY DETECT 11.2.1 VDETECT Circuit The VDETECT circuit is used to determine the presence of an external charger. The equivalent circuit is illustrated below. www.national.com 6 (Continued) The Shunt Regulator (Z1) on the VDETECT pin is designed to sink a limited amount of current while maintaining certain levels of regulation. These are specified below. When there is excessive current flowing into the VDETECT pin above which Z1 can regulate, then current can flow through D1 into the cell pin. When the cell pin voltage exceeds VSHUNT, ICELL_SHUNT turns on. The ICELL_SHUNT circuit is implemented redundantly. ICELL_SHUNT shunts current to ground through effectively 100Ω when both redundant circuits are operating. 20111505 FIGURE 2. VDETECT Circuit VDETECT circuit parametric specs are summarized below. These specs apply to the entire Normal Temperature Range. Parameter Description Min Typ Max Units IDETECTMIN1 Min VDETECT pin current to allow detection of a charger IUNDETECTMAX Maximum current into the VDETECT pin for the charger to be not detected. 3 µA IDETECTMIN2 Once a charger is detected, it will remain detected unless the current into the VDETECT pin goes below this threshold 25 µA ICELL_SHUNT VCELL current. With VCELL = 4.5V ( > VSHUNT) 20 75 mA 15 mA VCELL – 5 mV VCELL ± 50 mV V VCELL 1V V IDETECTMAX Max VDETECT pin current that can maintain VDETECTMAX1 VDETECTMAX1 Normal VDETECT regulation voltage, IDETECTMIN < IDETECT < IDETECTMAX VDETECTMAX2 Secondary VDETECT voltage limit, IDETECTMAX < IDETECT < 30 mA 100 µA 11.2.2 Debounce Function The charger debounce detects a temporary disconnect/connect of the charging power supply. This can occur when the end-user inserts the power supply to the phone and the connection is not made cleanly, or if the connection is disturbed (such as dropping the phone). When the IC first senses the power supply input voltage it will delay τDEBOUNCE_ON before the charger detect signal is confirmed. If there is disconnect of the charge power supply, the IC will delay τDEBOUNCE_OFF before the disconnection is confirmed. The IC will ignore the interruptions of duration shorter than specified. These specs apply to the entire Normal Temperature Range. 7 www.national.com LM3655 11.0 Charge Control Functions LM3655 11.0 Charge Control Functions Specification (Continued) Min Typ Max Units Debounce Connection Delay “τDEBOUNCE_ON” IDETECT stepped from 0 mA to 1 mA Test Conditions 22 32 64 ms Debounce Connection Delay “τDEBOUNCE_OFF” IDETECT stepped from 1 mA to 0 mA 22 32 64 ms 11.2.3 Power Supply Test Pulses The purpose of the test pulse operation is for the IC to periodically test the charging power supply’s full-rate current capability. This operation only occurs when the cell voltage is above VPHONE_ON. The test pulse has a period of τTEST_PERIOD and pulse width of τTEST_WIDTH. During test pulses the IC will fully turn on the M5 pass devices and attempts to draw ICHRG_MAX current from the charging power supply. The charging power supply will respond by delivering the full-rate current up to ICHRG-MAX to the load (Q1 will be forced into saturation). During the test pulse, the IC constantly monitors the cell voltage with its internal voltage regulation control circuit and the charge current with its current regulation control circuit. The power dissipation of Q1 is not controlled during the test pulse. The IC determines which charge rate to apply at the end of each test pulse. The interaction between the three control circuits is such that the voltage regulation is the most dominant so the cell voltage will not exceed VTERMX. (VTERMX being either VTERMH or VTERML, depending on the logic level applied to the CHEMISTRY pin). When the test pulse is high, one of the following can occur: 1. VPHONE_ON < VCELL < VTERMX and Charge Current < ICHRG_MAX: The charging power supply will continue to deliver full-rate current during and after the test pulse. Q1 remains in saturation and all M5 sense resistor switches remain on. 2. VPHONE_ON < VCELL < VTERMX and Charge Power Supply wants to deliver more than ICHRG_MAX (e.g. Failed Vehicular Power Adaptor and phone is connected directly to car battery): The internal current regulation control of the LM3655 IC will try to maintain the charge current at ICHRG_MAX by forcing the external Q1 and Q2 transistors into linear operation. This may exceed Q1 power dissipation limit. After the test pulse, the IC internal power regulation control senses the voltage across Q1 VCE above Q1UNSAT and determines the appropriate M5 sense resistor array switches to turn on. The effective resistance will determine the amount of charge current allow such that Q1 power dissipation is within limit of PPASS_MAX. If Q1UNSAT is exceeded at the end of a test pulse, CHRG_STATE will not go high as the Top-off signal is only created when VCELL reaches VTERMX. Unless a non-supported power supply is used, because of burp mode, it is expected that the system will mend itself and go back into full-rate when the next test pulse comes along. 3. VCELL reaches VTERMX (desired maximum cell clamp level): The IC internal voltage regulation control will dominate the charger control logic, and control the charge current to maintain VCELL at VTERMX. To accomplish this, the voltage regulation control forces Q1 and Q2 from saturation back in linear mode to reduce the charge current to a level that will maintain VCELL at VTERMX. After the test pulse, Q1 VCE above Q1UNSAT indicates the charge current to be reduced to trickle current. Q1 may or may not be in power-limit regulation. In order to prevent a transient situation when transitioning from trickle to full-rate between test pulses, the voltage regulation control will reset to zero for τTEST_DELAY and the current regulation control will then be forced to turn off Q1 and Q2. This in effect will set the charge current to zero. After τTEST_DELAY the voltage regulator will be allowed to ramp back up and the charge current will also ramp from zero to full-rate current. Figure 3 illustrates the charge profile. www.national.com 8 LM3655 11.0 Charge Control Functions (Continued) 20111506 FIGURE 3. Li-ion Charge Profile In region 1 the cell voltage is below VTERMX and the charge current is in full-rate, the charging will continue in full-rate after the test pulse. At the end of region 1 when the cell voltage reaches VTERMX, the charge current now drops to trickle current and the cell voltage drops slightly due to the IR drop of the cell internal impedance. The trickle current will continue in region 2 until the next test pulse arrives in region 3, the internal circuit will delay the test pulse for τTEST_DELAY while resetting the charge current to zero. After the delay the current will then ramp back to full-rate and the cell voltage will charge back to VTERMX. The test pulse stays high for at least τTEST_WIDTH and then reset to off as seen in region 4. In this region the charge current drops to trickle current as the cell voltage also drops slightly. In regions 5, 6, and 7, the circuit continues charging the cell while cell voltage gradually tapers to VTERMX and the height of pulse current is gradually getting smaller. In regions 8 and 9 the cell voltage reaches VTERMX before the next pulse arrives, the trickle charge current will begin to reduce to less than ITRICKLE-MAX. The current will continue to reduce in region 10 and so on until the current goes to zero. The cell voltage will be at the maximum charge capacity voltage of VTERMX. The charge profile will be different for different types of power supplies and discharge currents. Specification Test Conditions Pulse width of Voltage Regulator Reset “τTEST_DELAY” Fast Charging Pulse Width “τTEST_WIDTH” Fast Charging Pulse Period “τTEST_PERIOD” Falling edge of previous pulse to rising edge of next pulse Min Typ Max Units 0.7 1.0 1.3 ms 180 256 332 ms 44 64 84 Sec 11.2.4 Low Cell Voltage Charging (Pre-Charging) When the cell is very deeply discharged, the IC’s normal cell voltage rail may be too low for proper operation. When connected to a power supply, if full-rate charge were immediately entered, the external supply voltage would collapse to the (very low) cell voltage level once the power supply’s current limit has been reached. To avoid this situation, and also to protect a deeply-discharged cell from potential damage by fast-charging too rapidly, a reduced current charge is applied to the cell until it reaches a minimum “safe” operating level, VPHONE_ON. The current the IC draws from the cell to operate its internal circuitry when the charge power supply is detected is IQ_CHRG. When the cell voltage is less than the Phone On Voltage Threshold, 3.00V, and above the Secondary Under-voltage threshold, 1.98V, the cell will be charged at a low charge current. In this mode, the power dissipation management circuit is active thus Q1 will not be over-dissipated. Burp mode is not active in this voltage range. A special charge circuit is provided that operates for cell voltages between 0V and 1.98V. This circuit is active only if a charger is applied and the cell is in this voltage range. The charge current is limited to 70 mA maximum in this mode in order to limit the power dissipation of Q1 and M5 to 800 mW for power supply voltages of 18V or less. Once the cell increases to 1.98V, the sub-2V charging deactivates and the conventional charger takes over. A diode path from the VDETECT pin to the CELL + pin allows for a trickle charge current (limited by R4A and R4B ) for deeply charged cells ( < 0.7V). 9 www.national.com LM3655 11.0 Charge Control Functions (Continued) Unless otherwise specified, limits are for Normal Operating range. Specification Test Conditions Min Typ Max Units Quiescent Current when charge power supply is detected “IQ_CHRG” VCELL ^ VPUV to VTERMX; VIN = 0; No Load at Radio B+; CHRG_DETB, CHEMISTRY, DISABLE, CHRG_STATE and CNTRL pins. IDETECT = 300 µA; - - 800 µA Low Charge Voltage Threshold “VCHRG_LOW” @ T= 25˚C Transition from Charge State High to Charge State Low 2.50 2.575 2.65 V Low Charge Voltage Threshold VCHRG_LOW (normal operating temperature range) Transition from Charge State High to Charge State Low 2.475 2.675 V Maximum Trickle Charge Current “ITRICKLE-MAX” @ 25˚C range (current out of CELL pin) VCELL = 3.5V, IDETECT = 1.250 mA, VPS = 6V Maximum Trickle Charge Current “ITRICKLE-MAX” - normal operating range (current out of CELL pin) VCELL = 3.5V, IDETECT = 1.250 mA, VPS = 6V Minimum Trickle Charge Current “ITRICKLE-MIN” - normal operating range (current out of CELL pin) VCELL = 3.5V, IDETECT = 12 mA, VPS = 27.5V Maximum Sub 2V Charge Current “ISUB2V-MAX” - @ 25˚C (current into VIN pin and out of CELL pin) VCELL = 1.1V, VPS = 6V (For 1V < VCELL < 2V, ISUB2V will monotonically increase) Maximum Sub 2V Charge Current “ISUB2V-MAX” - normal operating range (current into VIN pin and out of CELL pin) VCELL = 1.1V, VPS = 6V (For 1V < VCELL < 2V, ISUB2V will monotonically increase) Maximum Sub 2V Charge Current “ISUB2V-MAX” - @ 25˚C (current into VIN pin and out of CELL pin) VCELL = 1.8V, VPS = 6V (For 1V < VCELL < 2V, ISUB2V will monotonically increase) Maximum Sub 2V Charge Current “ISUB2V-MAX” - normal operating range (current into VIN pin and out of CELL pin) VCELL = 1.8V, VPS = 6V (For 1V < VCELL < 2V, ISUB2V will monotonically increase) 190 mA 150 250 mA 20 55 mA 37.5 12.5 mA 70 37.5 12.5 mA mA 70 mA 11.2.5 Full-Rate Charging Once the cell voltage rises above VPHONE_ON, the cell will be charged at full-rate unless the cell voltage drops below VCHARGE_LOW. The charge power supply will deliver all the charge current it can into the load while the IC is monitoring the power dissipation of Q1 with the maximum of PPASS_MAX and the maximum charge current of ICHRG-MAX. Should the power dissipation of Q1 or the charge current exceed these limits, the IC will revert to trickle charge mode to protect Q1 from over-dissipation. Q1 is saturated when the charge current is in full-rate and Q1 is operated in linear mode when the charge current is in trickle charging mode. Because transient loads on Radio B+ (such as when the phone is in its pulsed transmit mode) can cause voltage transients on the cell pin, it is determined that Q1 is NOT saturated ONLY after the peak detected Q1 emitter voltage minus the cell pin’s voltage exceeds Q1UNSAT for a debounce period of 8 ms. This debounce is applied to all uses of Q1UNSAT in the IC. Q1UNSAT is the voltage between the cell pin and the emitter of Q1, which corresponds to the voltage drop across M5 and the saturation drop across Q1. The CHRG_STATE output pin of the IC will change its state when VCELL reaches VTERMX. It will not go high because Q1UNSAT is exceeded. Unless otherwise noted, the following specifications apply over the Normal Temperature Range. Specification Test Conditions Min Typ Max Units V Charge Control Voltage Threshold “VTERMX” “VTERMX = VTERML” @ 25˚C Chemistry Pin LOW 4.065 4.10 4.135 “VTERMX = VTERMH” @ 25˚C Chemistry Pin HIGH 4.13 4.16 4.19 V 45 65 80 mW 4.17 V “VTERMH” – “VTERML” @ 25˚C “VTERMX = VTERML” 0˚C to +50˚C Chemistry Pin LOW 4.03 “VTERMX = VTERMH” 0˚C to +50˚C Chemistry Pin HIGH 4.10 4.22 V “VTERMX = VTERML” −20˚C to +70˚C Chemistry Pin LOW 3.90 4.25 V www.national.com 10 LM3655 11.0 Charge Control Functions (Continued) Unless otherwise noted, the following specifications apply over the Normal Temperature Range. Specification “VTERMX = VTERMH” −20˚C to +70˚C Test Conditions Chemistry Pin HIGH Min Typ 3.90 Max Units 4.25 V Q1 Unsaturated Threshold “Q1UNSAT” @ 25˚C 550 - 795 mW Over Normal Temperature Range 550 - 795 mW 2.88 3.00 3.12 V “VPHONE_ON” at CELL Pin Cell voltage at which phone is operational Maximum Full Rate Current “ICHRG-MAX” @ 25˚C 1.0 1.2 1.4 A Over Normal Temperature Range 1.0 1.2 1.4 A @ 25˚C 530 650 800 mW @ −20˚C 530 650 880 mW @ +70˚C 475 650 800 mW Maximum Power Dissipation of Pass Transistor For R4A + R4B = 2 kΩ “PPASS_MAX” VPS – VCELL = 5V to 22V 11.2.6 Trickle/Top-Off Mode After the full-rate charge is completed and the cell is charged to VTERMX, the current will be reduced to the trickle charge current. The pass transistor Q1 will no longer be in saturation and will now operate in linear mode. The maximum trickle current is ITRICKLE_MAX unless the power dissipation of Q1 exceeds PPASS_MAX. If the power dissipation of Q1 exceeds PPASS_MAX, the trickle current will be further reduced until the power dissipation of Q1 is less than or equal to PPASS_MAX. During the transition from full-rate to trickle charge, the voltage of the cell will relax (IR drop due to cell internal impedance), but the cell will again eventually be charged up again to VTERMX. While the LM3655 allows the trickle current continue to flow to the cell, it will constantly monitor the cell voltage not to exceed VTERMX. The IC will maintain the cell voltage at VTERMX by gradually reducing the trickle current, and eventually no charge current will flow into the cell. The charge rate between VSUV and VCHARGE_LOW is limited to the lowest setting of the Trickle charge range (ITRICKLEMIN). Once VCHARGE_LOW is reached, the trickle charger will remain charging but can use the full range of trickle charge, from ITRICKLEMIN to ITRICKLEMAX. 11.2.7 Peak Detector Function The LM3655 device uses two independent peak detector circuits. One is used for filtering the ripple from the input power supply, and the other for minimizing the IR drop of the cell voltage during transmit pulses (if the phone is operated while connected to a charger). The peak detector circuits allow the device to be less sensitive to the ripple-induced noise that could unintentionally trigger the internal circuit thresholds of the IC. The peak detector circuit for smoothing the power supply ripple has its input connected across to the emitter of Q1 to CELL for monitoring Q1 VCE voltage and voltage across M5. The filtered voltage from the peak detector is used by the circuit that regulates the power of the external PNP pass transistor Q1. The power limiting circuit determines the maximum charge current such that the maximum power dissipation of Q1 [(Q1 VCE +Ma5)* Ic] is lways at PPASS_MAX. The peak detector for the cell voltage is used to smooth the sensed values for cell voltage drop during the transmit pulses. The peak detector is in essence a digital filter with transient response characteristics as outlined below. Two parameters are associated with the peak detector, decay rate and attack rate. Figure 4 a) and b) below show the decay and attack rates of the power supply ripples and for the transmit pulses on the cell (output) voltage respectively. The typical input voltage filter decay and attack rates are respectively 5.0 ms and 15.6 µs. The typical output voltage filter decay and attack rates are respectively 4 mV/ms and 1.4V/ms. 11 www.national.com LM3655 11.0 Charge Control Functions (Continued) 20111507 FIGURE 4. Peak Detector Response 12.0 Discharge Control Functions 12.1 GENERAL DESCRIPTION Depending on the state of charge of the cell (cell voltage), charging and discharging can occur simultaneously. There are two scenarios: discharge while the charger power supply is connected and discharge while the charger power supply is disconnected. This will impact the operations of the internal PMOS/NMOS devices and the pass transistor Q1. Figure 5 illustrates the relevant components of the system. 20111508 FIGURE 5. Circuit Block Diagram The charge current will flow through M5 and some current will flow into the cell and some current will flow through M4 and to the phone. When the charge power supply is not connected the pass transistor Q1 will be turned off and M5 will be off. The current will be discharged from the cell through M4. 12.2 RADIO+ GENERATION All current for the phone is sourced through the RADIO_B+ pin. This allows M4 to regulate or disable the battery load current in the event of an overload condition, internal phone short circuit, or extremely low cell voltage not detected by the phone’s power management logic. www.national.com 12 LM3655 12.0 Discharge Control Functions (Continued) 12.3 UNDER-VOLTAGE CUT-OFF Two thresholds for cell under-voltage detection are used to prevent the cell from being discharged below levels that could cause irreversible damage. The higher level, Primary Under-Voltage, is designated VPUV, and the secondary level is VSUV. Nominal values are 2.350V and 1.98V respectively. When the VPUV threshold is crossed, a timer is initiated. If the cell voltage remains below VPUV but above VSUV for the delay time τPUV (nominally 64 ms), the IC enters sleep mode. The IC will go into sleep mode with no time delay if the cell voltage drops below VSUV. In sleep mode, all of the sequential logic is reset to a standby state. The safety shunt circuits are still powered up in order to protect the chip and cell from an accidental path for high energy to the VIN pin. M4 control circuits are powered down (M4 remains off). Operating Current Parametric Specs Unless otherwise noted, the following specifications apply over the Normal Temperature Range. Specification Test Conditions Min Typ Max Units Quiescent Current w/no external power supply “IQ_DISG” @ 25˚C VCELL = VPUV to VTERMX No Load at Radio B+, IVIN = 0, VDETECT = 0V, ICNTRL = 0A - 20 30 µA Quiescent Current w/no external power supply “IQ_DISG” @ −20˚C < T < 60˚C VCELL = VPUV to VTERMX No Load at Radio B+, ICIN = 0, VDETECT = 0V, ICNTRL = 0A - - 50 µA Sleep Mode Current “IQ_SLEEP” @ T = 25˚C Sleep mode AND VCELL = VPUV to 0V No Load at Radio B+ VDETECT = 0V, ICNTRL = 0A - 9.0 15 µA Sleep Mode Current “IQ_SLEEP” @ Normal Temperature Range Sleep mode AND VCELL = VPUV to 0V No Load at Radio B+ VDETECT = 0V, ICNTRL = 0A - - 20 µA Primary Under Voltage “VPUV” at CELL Pin Time delay entry into sleep mode = τPUV 2.275 2.350 2.425 V Hibernation Delay “τHIBERNATION” 22 32 64 ms Primary Under Voltage Delay “τPUV” 44 64 84 ms 1.90 1.98 2.06 V 100 200 300 mV Secondary Under Voltage “VSUV” at CELL Pin No delay entry into sleep mode “VCHRG-LOW − VPUV = ∆CHRGLOW-PUV” 12.4 POWER CUT OPERATION A power cut is defined as momentary loss of contact between the battery/cell and the phone circuitry, typically caused by contact bounce. During a power cut, the connection between the cell’s positive terminal and the IC’s CELL pin may be lost as well as the ground connection between the cell’s negative terminal and the IC’s ground pins. During Power Cut the IC will go into the sleep mode. Once the connection is re-established and the cell voltage is greater than VCHRG_LOW (nominally 2.575V), the IC will power up its internal circuitry and allow the operations (charging and discharging) to continue. A power cut is differentiated from an under-voltage condition by monitoring the cell voltage level. 12.5 HIBERNATION MODE When the cell is in its normal voltage range ( > 2.575V), M4 is closed. Thus any radio current consumption can discharge the battery. This is generally desired except when the phone is stored for a long time without use and without being charged. When hibernation mode is enabled, then M4 is opened so that the battery cell will discharge only due to the consumption of this IC and not because of any Radio B+ current consumption. When Hibernation is enabled, the IC will be put into ‘sleep’ which allows the IC to have a smaller quiescent current when compared to ‘normal’ mode. Hibernation mode is entered when HIB_EN is held high for a debounce period of 32 ms. Hibernation mode is exited and M4 subsequently closed when a charger is connected to LM3655 or when the HIB_DISB input pin goes low. 13.0 Safety Functions 13.1 INPUT OVER-VOLTAGE PROTECTION 13.1.1 Normal Operation (Q1 Control) Under normal conditions, the Q1 pass device prevents excessively high voltages from reaching RADIO_B+. In the case of full-rate charging, the external supply voltage will normally collapse to a level just above the cell voltage as the supply current limit is reached. As charge current is reduced, the supply voltage may increase, but the voltage difference is dropped across Q1 as 13 www.national.com LM3655 13.0 Safety Functions (Continued) it operates in linear mode. Q1 typically has an input voltage rating of 30V (see Section 14.1 CHARGE PASS TRANSISTOR (Q1)). However, if Q1 fails as a short, the shunt control mechanism of the IC will still protect the phone and cell from high voltages. The internal M3 shunt transistor is used to clamp the VIN, CELL and RADIO_B+ power pins to safe values. 13.1.2 Safety Shunt/Crowbar Operation The LM3655 only activates the over-voltage protection if there is an internal failure of the LM3655 or a failure to the external components, such as Q1 being shorted. Should one of these failures occur and the cell voltage exceeds a nominal level of 4.35V (VSHUNT), M3 will operate as a shunt regulator limiting the voltage at the cell terminal to VSHUNT. A secondary shunt activation mechanism occurs if VIN exceeds a nominal level of 5.2V (VSHUNT_INPUT). When operating as a shunt regulator (in the linear mode of M3), excessive current may cause M3 power dissipation to exceed safe limits if uncontrolled. If the M3 current limit of 4 Amps (typical IFAST_CB) is exceeded, the IC will protect itself by turning M3 fully on in order to shunt the current. When in the safety shunt crowbar mode, the IC will turn off Q1 to stop the charge current assuming that the external components and the control circuit of the IC are still operational. 13.1.3 Standby Shunt Mode Another protection feature of the IC is a Standby shunt mode. When there is no charger present M3 is turned on as it would be in Crowbar mode. Q1 is already turned off because the charger isn’t present. M3 is turned off when there becomes a charger present. In this condition, the other crowbar modes function as is. Standby shunt mode doesn’t interfere with the fast and thermal (see Section 13.1.4 Thermal Crowbar Mode and Section 13.1.5 Fast Shunt Operation) crowbar modes. 13.1.4 Thermal Crowbar Mode Another safety protection feature of the IC is the thermal crowbar protection. As the charge power supply’s current compliance increases, significant power dissipation occurs and the junction temperature of the IC could approach TCB. This is the ‘Crowbar1’ initiation temperature and the power NMOS device M3 will be switched to full conduction mode in order to protect the IC. The PMOS device M5 is switched off in Crowbar mode to prevent high cell discharge currents. The charge power supply’s current may or may not open the external discrete fuse. If the fuse survives, the only recovery method from Crowbar1 mode is for the junction temperature to reduce below TRESET while in this mode for at least τcrowbar1. When in the thermal crowbar mode, the IC will turn off Q1 to stop the charge current assuming that the external components and the control circuit of the IC are still operational. 13.1.5 Fast Shunt Operation The VIN pin voltage is also AC-coupled to the shunt control network to provide a “fast comparator” function that can activate the shunt transistor quickly in response to a fast-rising transient on the input. This allows the shunt device to be activated prior to the other means of activation such as exceeding IFAST_CB or thermal crowbar mode and bypasses the delays associated with the DC-level sensitive comparator circuits. In actual operation it will typically be very unlikely to activate the input shunt without activating the cell-initiated shunt mechanism because the two voltages are related via M5 conduction. 13.1.6 Shunt Circuit Parametric Specifications Unless otherwise noted, the following shunt specifications apply over the Normal Temperature Range. Min Typ Max Crowbar Temperature “TCB” Specification ISHUNT = 1A Test Conditions 105 120 135 Units ˚C Crowbar Reset Temperature “TRESET” ISHUNT = 0A 60 75 90 ˚C 4 7.5 A 50 µs Fast Crowbar Current “IFAST_CB” τFAST_CB = minimum 2 Fast Crowbar Delay “τFAST_CB” ISHUNT = 10A 1 Crowbar1 Sustain Time “τCROWBAR1” ISHUNT = 1A 4 8 16 s Crowbar2 Sustain Time “τCROWBAR2” ISHUNT = 10A 32 64 128 ms Primary Shunt Control Voltage “VSHUNT” at (CELL) Pin @ 25˚C @ Normal Termperature Range IVIN = 50 mA, IDETECT = 200 µA 4.30 4.25 4.35 4.35 4.40 4.45 V V 100 190 350 mV 4.7 5.2 5.7 V 1 2 5 ms 0.5 1.1 2.2 V VSHUNT_CELL – VTERMH Secondary Shunt Control Voltage at VIN Pin (VSHUNT_INPUT) IVIN = 50 mA, VDETECT = 0 τSTBYSHUNT Delay when CP goes from 1 to 0 before M3 gets turned on. VSTBY_SHUNT 0.1A to 2A into VIN www.national.com 14 LM3655 13.0 Safety Functions (Continued) 13.2 SCHOTTKY ELIMINATION MODE (CHARGER INPUT SHORT CIRCUIT/REVERSE CURRENT PROTECTION) In the case that the external input is shorted during charge, the initial state of M5 will be conducting, and reverse current will begin to flow through M5 (draining the battery). To prevent the need for an additional external schottky blocking diode, the IC will sense reverse current flow through M5 and turn the device off. 13.3 REVERSE CHARGER PROTECTION The IC will protect against a reverse charger by sensing the charging power supply input voltage at VIN terminal below VREVERSE for τREVERSE. Initially, Q1 is disabled to protect the phone and battery. Additional reverse charger protection exists in case the Pass Transistor Q1 cannot be turned off. The IC will activate the M3 crowbar operation and turn off pass device M5. This clamps the input from going negative without shunting the cell voltage. These specs apply to the entire Normal Temperature Range Min Typ Max Units Reverse Charger Voltage “VREVERSE” at VIN Pin Specification VCELL > VSUV Test Conditions 0 −0.5 −1.0 V Reverse Charger Crowbar Duty Cycle (% of time spent in Crowbar during Reverse Charge Pulsing mode) VCELL = 3.6V IVIN = −100 mA 75 Reverse Charger Delay “τREVERSE” following application of the reversed voltage prior to the first Crowbar event VIN = −1.0V 0.01 % - 7 ms Fault conditions at VIN could occur in either polarity. The reverse charger detection circuitry will sense the occurrence of VIN < −0.5V and activate full conduction of M3 (called crowbar mode) after a time delay, τREVERSE. This clamping action prevents the potential for damage to the IC. Continuous reverse energy will result in a pulsating activation of crowbar. 13.4 OUTPUT CURRENT OVERLOAD PROTECTION (“PTC” MODE) The power PMOS device M4 operates as a switch/pass element for controlling the discharge current of the cell while the PMOS device M5 is off. In “PTC Mode”, the LM3655 emulates a Positive Temperature Coefficient device such as a polymeric resetable fuse. During discharge the current is flowing out from the cell through the PMOS M4 to the load. The circuit will regulate the current below IREG while the junction temperature of the IC is monitored in discharge. As long as the current is less than IREG and the junction temperature does not exceed TPTC, the circuit will deliver the current with no interruption. If the junction temperature exceeds TPTC, the current regulation activate, causing the current to continuously decrease as the temperature continues to increase. Once TPTC is exceeded, this circuit will effectively latch a thermostatic control system that reduces the discharge current to a level that limits the power dissipation on the IC. During discharge mode, almost all of the heat generated in the IC will be due to the PMOS M4. Once this mode is activated, the regulation current is reduced to several hundred mA and will only recover from this mode of operation when the cell’s load current reduces to a level that allows the die temperature to decrease. These specs apply to the entire Normal Temperature Range. Specification Test Conditions Maximum Regulated Discharge Current “IREG” Thermostatic Junction Temperature of M4 “TPTC- Thermostatic Junction Temperature of M5 “TPTC- M4” M5” Min Typ Max Units VCELL = 3.6V 2.5 4 6.5 A Cell Charging RADIO B+ = 3.5V VCELL = 4.0V 90 105 125 ˚C Cell Charging, VCELL = 3.6V 90 105 125 ˚C ∆ (TCB – TPTC M4) Delta between TCB & TPTC M4 10 - 30 ˚C ∆ (TCB – TPTC M5) Delta between TCB & TPTC M5 10 - 30 ˚C 13.5 OUTPUT SHORT CIRCUIT CURRENT PROTECTION In an event that the RADIO B+ terminal becomes shorted to ground, the IC will interrupt the short circuit current exceeding ISHUTOFF by turning off M4 PMOS immediately for a period of tSHUTOFF. After this period the regulation circuit will slew the M4 PMOS back to the regulation current. If the short circuit current still persists and the junction temperature exceeds TPTC, the IC will initiate the PTC operation to reduce the current. Figure 6 shows an example of a short circuit protection waveform. 15 www.national.com LM3655 13.0 Safety Functions (Continued) 20111509 FIGURE 6. Short-Circuit Protection Waveform These specs apply to the entire Normal Temperature Range. Specification Test Conditions Short Circuit Discharge Current “ISHUTOFF-THRESH” The voltage here divided by M4 resistance = ISHUTOFF. Short Circuit Discharge Current Recovery “τSHUTOFF” Min Typ Max Units VCELL = 3.6V Voltage across M4 −20˚C to +70˚C −20˚C to +125˚C 425 350 1000 1000 mV mV IRADIO_B+ = ISHUTOFF 0.01 10 ms ISHUTOFF-THRESH refers to a voltage threshold between the Cell pins and the Radio B+ pins. When the voltage between these pins exceeds this voltage threshold, M4 is to open. This circuit reacts very quickly as it is intended to be immediate. This voltage threshold is then referred to current by dividing it by the resistance of M4 (the resistance between the Cell and Radio B+ pins). For example the threshold current (ISHUTOFF) is 7 amps for a threshold voltage of 700 mV and a resistance of 100 mΩ. It is specified in this manner to reflect the circuit implementation. If the short circuit current is less than the lower limit, there will be no interruption of IRADIOB+ short-circuit current. IREG will reduce IRADIOB+ to 4A in approximately 400 µs. If the current is greater than the upper limit, the short-circuit event will be guaranteed to activate ISC. The sequence is: PMOS M4 is turned off for τSHUTOFF and allowed to turn on with the current regulating loop limiting current to 4 Amps in 400 µs. Very large currents and associated energy are avoided for this 400 µs settling period. www.national.com 16 LM3655 14.0 Required External Components 20111510 14.1 CHARGE PASS TRANSISTOR (Q1) Q1 is a PNP device capable of sustaining a minimum of 0.8W continuous power dissipation. ON Semiconductor MMJT9435 or equivalent is to be used. 14.2 DRIVER TRANSISTOR AND BIAS RESISTORS (R2, R3 AND R5) The NPN transistor is a MMBT3904LT1 type (or equivalent) with a BVCEO > 40V. The base resistor (R2) is 1K. The emitter and collector resistors (R3 and R5) are 75Ω each. The power rating on R3 and R5 is to be at least 100 mW. 14.3 EXTERNAL CHARGER SENSE RESISTOR (R4) Value = 2K total for R4A+ R4B. Two series resistors are used for higher reliability. Having two resistors in series significantly reduces the probability of the entire 2K of resistance being shorted. The power rating of R4A and R4B needs to be at least 100 mW each. 14.4 CAPACITORS The capacitor C1 is to be a 0.1 uF, which is used for both RF bypass and ESD protection reasons. The capacitors C2 and C3 are 0.1 uF capacitors, which are used in the application to keep M4 from momentarily opening when the ground plane of the phone takes an ESD discharge. These capacitors C2 and C3 should be adjacent to the pins on the IC. C4 on Radio B+ is 10uF. 14.5 FUSE (F1) Parameter Operating Temperature Insulation Resistance (After Opening) Opening Time at 25˚C 100% of Ampere Rating 200% of Ampere Rating 300% of Ampere Rating Min Typ Max Units −55 25 90 ˚C 10000 - - Ω 4 5 0.2 - - Hour Sec. Sec. Ampere Rating 2.0 A Nominal Resistance Colda 0.036 Ω Melting I2t 0.104 A2Sec. Volting Rating 32 V Interrupting Rating @ 32V AC/DC 35 A 15.0 Electrical Characteristics 15.1 GENERAL SPECIFICATION AND ABSOLUTE MAXIMUM RATINGS (Note 1) Symbol Parameter Min Typ Max Units Pin Voltage Ratings 17 www.national.com LM3655 15.0 Electrical Characteristics Symbol VIN (Continued) Parameter Maximum Input Voltage (VIN), 10 mS duration (Note 6) Min Typ Max Units −0.3 - +6.3 V - +5.7 V - +20 mA Maximum Input Voltage on all pins (Note 4) (Subject to the condition that maximum input current is not exceeded) −0.3 Maximum Input Current (All Pins) −20 θJA Thermal Resistance Junction to Ambient (Notes 2, 9) 35 PD Maximum Power Dissipation (Notes 2, 9) 950 TA Normal Operating Range (Note 5) −20 TJ Junction Temperature Range (Note 10) −20 TJE Extended Junction Temperature Range (Note 8) ˚C/W mW - +70 ˚C - +125 ˚C - 175 ˚C Storage Temperature Range −65 - +150 ˚C ESD (Note 3) (human body model) 2.0 - - kV ESD (Note 3) (machine model) 200 - - V Min Typ Max Units - 100 - 200 mΩ mΩ - 100 - 150 mΩ mΩ - 200 - 300 mΩ mΩ −0.3 - - V 15.2 PASS DEVICE AND POWER SUPPLY RATINGS Unless otherwise specified, limits are provided for TA = 25˚C and Normal Operating range Symbol Parameter Maximum NMOS M3 ON Resistance (VGS = 2.8V) RON_M3 RON_M3 TA = 25˚C Normal Operating Range (Note 5) Maximum PMOS M4 ON Resistance (VGS = 2.8V) RON_M4 RON_M4 TA = 25˚C Normal Operating Range (Note 5) Maximum PMOS M5 ON Resistance (VGS = 2.8V) RON_M5 RON_M5 TA = 25˚C Normal Operating Range (Note 5) VPSMIN Minimum Power Supply Input Voltage Rating VPSMAX Maximum Power Supply Input Voltage Rating VCLAMP Peak Voltage - - 30 V Continuous Voltage - - 18 V Maximum Clamping Voltage VIN (This is the maximum voltage at VIN Pin when input transient of 20 Amps or less occurs. This can happened only when Q1 fails short) - - 6.30 V Min Typ Max Units - - - - - - 0.6 V 1.5 - - V 15.3 IC PIN ELECTRICAL CHARACTERISTICS Unless otherwise specified, limits are provided for TA = 25˚C and Normal Operating range Pin Symbol CELL CHEMISTRY CHRG_DETB VIL_CHEMISTRY (Note 7) Pulled low to set VTERMX to VTERML. VIH_CHEMISTRY (Note 7) Pulled high to set VTERMX to VTERMH. RCHEMISTRY CHEMISTRY pull-down resistance 50 100 200 kΩ VOL RL 30 kΩ to Radio B+, and VPS > VIN - - 0.3 V VOH RL 30 kΩ to Radio B+, and VPS > VIN 0.9* Radio B+ - - V - - 0.3 V 0.9* Radio B+ - - V CHRG_STATE VOL VOH www.national.com Test Conditions See Pin Voltage Rating in 6.1 RL 30 kΩ to Radio B+ Full-Rate Charge Mode RL 30 kΩ to Radio B+ Trickle Charge Mode or DISABLE High. 18 LM3655 15.0 Electrical Characteristics (Continued) Unless otherwise specified, limits are provided for TA = 25˚C and Normal Operating range Pin CNTRL DISABLE BATT_DETB Min Typ Max Units VCNTRL1 Symbol Maximum Control Voltage1 VCELL > VPUV, IDETECT = 200 µA Test Conditions VCELL – 0.3 - VCELL V VCNTRL2 Maximum Control Voltage2 VCELL > VPUV, IDETECT = 200 µA VCELL – 0.95 - VCELL V RCNTRL Effective Control Pin Output Resistance IDETECT = 200 µA, VCELL > VPUV ICNTRL = Current into an external short to Ground on the Control Pin, Charger Present RCNTRL = VCELL/ICNTRL 150 - 350 Ω - - 0.6 V 1.5 - - V 50 100 200 kΩ - - 20% of VCELL 80% - - of VCELL 50 100 200 kΩ - - 0.6 V 1.5 - - V 5 10 20 kΩ - - 20% of VCELL 80% - - of VCELL 50 100 200 kΩ VIL_DISABLE (Note 7) Pulled low to enable Q1 charge. VIH_DISABLE (Note 7) Pulled high to disable Q1 charge. RDISABLE Measured from DISABLE input resistance to ground. VIL_BATTDETB (Note 7) Pulled low to allow CP to function VIH_BATTDETB (Note 7) Floats high to disallow CP to function RBATTDETB Internal pull-up to the Cell voltage if CP = 1 VIL_HIBEN (Note 7) Pulled low when not used. VIH_HIBEN (Note 7) Pulled high to enable Hibernation mode. RHIBEN Measured from HIB_EN input resistance to ground VIL_HIBDISB (Note 7) Pulled low to clear Hibernation Latch VIH_HIBDISB (Note 7) Floats high when not used. RHIBDISB MEASURED from HIB_DISB input resistance to CELL pin. RADIO_B+ - See Pin Voltage Rating in 6.1 - - - - VIN VCLAMP Maximum external voltage clamp level when Q1 fails shorted, < 20A current forced into pin; see (Note 6). - - 6.3 V HIB_EN HIB_DISB VDETECT IDETECTMIN1 Min VDETECT pin current to allow detection of a charger IDETECTMIN2 Once a charger is detected, it will remain detected unless the current into the VDETECT pin goes below this threshold IDETECT_MAX Max VDETECT pin current that can maintain VDETECTMAX1 IUNDETECT_MAX Below this current level into the VDETECT pin, a charger will always not be detected. VDETECTMAX1 Normal VDETECT regulation voltage, IDETECTMIN < IDETECT < IDETECTMAX VDETECTMAX2 Secondary VDETECT Voltage limit, IDETECTMAX < IDETECT < 30 mA 19 100 - µA - µA 15 mA 3 µA VCELL VCELL −5 mV - 25 V ± 50 mV - VCELL 1V V www.national.com LM3655 15.0 Electrical Characteristics (Continued) Note 1: Absolute Maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see electrical characteristics per each section. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: With PCB copper enhancements. Board description: Substrate Material is FR-4. Overall Dimension (LxW) is 76.2 mm x 114.3 mm. Metalization Dimension (LxW) is 60.7 mm x 60.6 mm. Thickness is 1.57 mm. 6 thermal vias of Pitch = 1.27 mm (via pitch)/0.5 mm pad pitch. Number of Cu layers = 4. Cu coverage (signal layer-top/bottom) is 4%/40%. Cu thickness (signal layer-top/bottom) = 2 oz copper. Cu coverage (power/ground layer) = 100%. Cu thickness (power/ground layer) = 1 oz. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. Note 4: Maximum voltage on any pin with exception to VDETECT pin. VDETECT pin is protected by R4A and R4B resistors in series. Note 5: NORMAL operating range. The part is expected to operate within its specified parametric limits in the normal range, and maintain all electrical specifications and full functionality when operated within these limits. The normal operating range is intended to apply to battery packs used under average to severe use conditions. Note 6: The VIN pin is protected against very high transient fault currents by activation of a shunt regulator. The internal voltage of the chip at the cell pin is limited to VSHUNT, however the external voltage of the VIN pin can increase beyond VSHUNT due to current in the lead resistance and M5. Note 7: One side of the input comparator being driven by a buffered bandgap sets all digital input thresholds level of 1.2V. As a result any logic level that is greater than approximately 1.3V will be logic high, and any logic level that is less than approximately 1.1V will be logic low. Note 8: Extended junction temperature range applies to the maximum die temperature during a transient thermal protection event. Outside of these thermal transients, the IC should not be operated where the die temperature goes outside of the Junction Temperature Range defined in table 7.1. Note 9: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: P = (TJ – TA)/θJA. where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The 950 mW rating appearing under Absolute Maximum Ratings results from substituting the Thermal Crowbar temperature, 100˚C, for TJ, 70˚C for TA, and 35˚C/W for θJA. More power can be dissipated safely at ambient temperatures below 70˚C. Less power can be dissipated safely at ambient temperatures above 70˚C. Note 10: Junction Temperature minimum is set equal to the Normal Operating Temperature Range, The IC can be stored down to −65˚C without damage to the IC. www.national.com 20 inches (millimeters) unless otherwise noted NS Package Number TLA25 The dimensions for X1, X2 and X3 are as given: X1 = 2.568mm +/- 0.03mm X2 = 2.822mm +/- 0.03mm x3 = 0.6mm +/- 0.075mm National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 LM3655 Charge Control and Protection IC for embedded single cell Li-Ion/Polymer batteries 16.0 Physical Dimensions