Power Supply IC Series for TFT-LCD Panels 12V Input Multi-channel System Power Supply IC BD8160AEFV No.09035EBT01 ●Description The BD8160AEFV is a system power supply for the TFT-LCD panels used for liquid crystal TVs. Incorporates two high-power FETs with low on resistance for large currents that employ high-power packages, thus driving large current loads while suppressing the generation of heat. A charge pump controller is incorporated as well, thus greatly reducing the number of application components. ●Features 1) Step-up and step-down DC/DC converter 2) Incorporates 2.6 A N-channel FET. 3) Incorporates positive/negative charge pumps. 4) Input voltage limit: 8 V to 18 V 5) Feedback voltage: 1.162 V ± 1% 6) Switching frequency: 500 kHz / 750kHz 7) Protection circuit: Under voltage lockout protection circuit Thermal shutdown circuit Overcurrent protection circuit Short Circuit Protection Overvoltage protection circuit for VS voltage (Boost DC/DC output) 8) HTSSOP-B28 Package ●Applications Power supply for the TFT-LCD panels used for LCD TVs ●Absolute maximum ratings (Ta = 25°C) Parameter Supply Voltage Symbol Rating Unit SUP,VIN 20 V Pd 4700* mW Power Dissipation Operating Temperature Range Topr -40～+85 ℃ Storage Temperature Range Tstg -55～+150 ℃ Tjmax 150 ℃ Junction Temperature SW Voltage VSW 21 V SWB Voltage VSWB 19 V VEN1,VEN2 19 V EN1,EN2 Voltage * Derating in done 37.6mW/℃ for operating above Ta≧25℃(On 4-layer 70.0mm×70.0mm×1.6mm board) ●Recommendable Operation Range (Ta=25℃) Parameter Limits Symbol Unit Min Typ Max SUP,VIN 8 12 18 V VS VIN+2 15 18 V Switch current for SW ISW － － 2.6** A Switch current for SWB ISWB － － 2.0** A EN1,EN2,FREQ Voltage VEN1,VEN2,VFREQ － － 18 V Supply Voltage VS Voltage ** Pd, ASO should not be exceeded www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/18 2009.07 - Rev.B BD8160AEFV Technical Note ●Electrical characteristics (unless otherwise specified VIN=12V and Ta=25°C) 1. DC/DC converter controller block Parameter Symbol Limits Unit Conditions Min Typ Max ISO 6 10 14 µA FB and FBB input bias current IFB12 - 0.1 2 µA Feedback voltage for boost converter VFB 1.150 1.162 1.174 V Feedback voltage for buck converter VFBB 1.188 1.213 1.238 V On resistance N-channel RONN - 0.2 0.3 Ω IO=0.8A Leak current N-channel ILEAKN1 - 0 10 µA VSW =18V ISW 2.6 - - A MDUTY 75 90 97 % FB= 0V On resistance N-channel RONH - 0.2 0.3 Ω IO=0.8A Leak current N-channel ILEAKN2 - 0 10 µA VINB=18V , VSWB =0V ISWB 2.0 - - A VSWOVP 18.5 19 19.5 V Soft start – SS SS source current VSS=0.5V Error amplifier block – FB and FBB Voltage follower SW block – SW Switch current limit for SW Maximum duty cycle SW block – SWB Switch current limit for SWB Protections Over Voltage Protection for SW 2. Charge pump driver block Parameter Symbol Limits Min Typ Max Unit Conditions Error amplifier block – FBP and FBN FBP, FBN input bias current IFBP, IFBN - 0.1 1 µA Feedback voltage for VGH VFBP 1.188 1.213 1.238 V Feedback voltage for VGL VFBN 0.18 0.2 0.22 V IDLY1, IDLY2 2 5 9 µA VDLY=0.5V On resistance N-channel RONN - 5 - Ω IO=20mA On resistance P-channel RONP - 3 - Ω IO=20mA Delay start block DLY1, DLY2 source current DRP, DRN block www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/18 2009.07 - Rev.B BD8160AEFV Technical Note ●Electrical characteristics (unless otherwise specified VIN=12V and Ta=25°C) 3. General Parameter Limits Symbol Unit Conditions Min Typ Max ICC - 5 8 mA Oscillation frequency1 FOSC1 600 750 900 kHz FREQ = High Oscillation frequency2 FOSC2 400 500 600 kHz FREQ = low Under voltage lockout threthold1 VUVLO1 6.9 7.4 7.9 V VIN rising Under voltage lockout threthold2 VUVLO2 6.5 7.0 7.5 V VIN falling Thermal Shutdown TTSD - 175 - ℃ *1 Short Circuit Protection Time 1 TSCP1 153 219 285 ms FREQ = High Short Circuit Protection Time 2 TSCP2 230 328 426 ms FREQ = Low FB threshold1 for SCP VFBSCP1 0.985 1.065 1.145 V FB rising FB threshold2 for SCP VFBSCP2 - 0.969 - V FB falling FBB threshold1 for SCP VFBBSCP1 - 1.055 - V FBB rising FBB threshold2 for SCP VFBBSCP2 - 0.874 - V FBB falling FBP threshold1 for SCP VFBPSCP1 - 0.967 - V FBP rising FBP threshold2 for SCP VFBPSCP2 - 0.859 - V FBP falling FBN threshold1 for SCP VFBNSCP1 - 0.406 - V FBN falling FBN threshold2 for SCP VFBNSCP2 - 0.505 - V FBN rising VREF 1.188 1.213 1.238 V Gate drive threshold VGD 0.985 1.065 1.145 V GD output low voltage VOL - 0.7 1.4 V GD output leakage current ILK - 0 10 µA High level input voltage VIH 2.0 - - V Low level input voltage VIL - - 0.8 V Supply current Average supply current Oscillator Protections Reference Voltage Reference Voltage Gate Drive I=1mA Logic signals EN1, EN2, FREQ * This product is not designed for protection against radioactive rays. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/18 2009.07 - Rev.B BD8160AEFV Technical Note ●Reference Data (Unless otherwise specified, Ta = 25°C) 5 700 10 8 600 4.8 6 4.4 4 400 2 ISTB ［uA］ ISUP ［uA］ Icc [mA] 4.6 500 300 0 -2 -4 200 4.2 -6 100 -8 4 0 10 12 14 16 18 8 10 12 14 VIN : [V] Fig.1 SUPPLY CURRENT Fig.2 SUPPLY CURRENT 1.217 18 8 10 12 14 16 18 AVIN : [V] Fig.3 STANDBY CURRENT 800 1.216 12 700 1.215 750 kHz 600 1.214 11.5 500 1.213 f [kHz] REF [V] 16 VIN : [V] 1.212 1.211 400 Iss [uA] 8 -10 500 kHz 11 300 1.210 200 1.209 10.5 100 1.208 1.207 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 10 -40 -30 -20 -10 T a : [℃] 0 10 20 30 40 50 60 70 80 -40 -30 -20 -10 Fig.4 REF VOLTAGE 7 10 20 30 40 50 60 70 80 T a : [℃] Fig.6 SS SOURCE CURRENT Fig.5 SWITCHING FREQUENCY 0.1 0.1 6.8 0.08 0.08 0.06 6.6 0.06 6.4 0.04 6 5.8 IFB [uA] 0.04 6.2 IFB [uA] IDLY [uA] 0 Ta : [℃] 0.02 0 0.02 0 -0.02 -0.04 5.6 -0.02 5.4 -0.06 -0.04 5.2 5 -0.08 -0.1 -0.06 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 0 0.5 Ta : [℃] 1 1.5 0 2 0.5 Fig.7 DLY1,2 SOURCE CURRENT 1 1.5 V FBP, VFBN [V] V FB, V FBB [V] Fig.9 INPUT BIAS CURRENT Fig.8 INPUT BIAS CURRENT 2.5 0.3 14 0.25 12 2 0.2 Ron [Ω] Vs [V] DLY1 ［ V ］ 10 1.5 8 6 1 0.15 0.1 4 0.5 0.05 2 0 0 0 0.5 1 1.5 2 0 0 0.5 1 1.5 2 VEN1 ［V］ VEN2 [V] Fig.10 EN1 THRESHOLD VOLTAGE Fig.11 EN2 THRESHOLD VOLTAGE www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/18 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 T a [℃] Fig.12 SW ON RESISTANCE 2009.07 - Rev.B 2 BD8160AEFV Technical Note ●Reference Data (Unless otherwise specified, Ta = 25°C) 0.3 4.5 4.5 4 4 3.5 3.5 0.25 3 0.15 0.1 3 Ron [Ω] Ron [Ω] Ron [Ω] 0.2 2.5 2 1.5 1.5 1 0.5 0.5 0 -40 -30 -20 -10 0 0 -40 -30 -20 -10 10 20 30 40 50 60 70 80 2 1 0.05 0 2.5 0 10 20 30 40 50 60 70 80 -40 -30 -20 -10 Fig.13 SWB ON RESISTANCE 100 500kHz 98 90 80 75 70 94 92 88 86 60 84 55 82 80 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 8 Iout [A] Fig.16 OVP WAVEFORM 100 EFFICIENCY [%] EFFICIENCY [%] 80 750kHz 70 60 50 40 20 10 0 0 0.8 1 1.2 1.4 1.6 1.8 2 Iout [A] Fig.19 STEP DOWN EFFICIENCY www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14 VS 750kHz Vlogic 40 10 0.6 13 50 20 0.4 12 Fig.18 STEP UP EFFICIENCY 60 30 0.2 11 70 30 0 10 500kHz 90 80 9 VIN [V] Fig.17 STEP UP EFFICIENCY 500kHz 750kHz 90 65 50 90 500kHz 96 750kHz 85 EFFICIENCY [%] EFFICIENCY [%] SW 30 40 50 60 70 80 Fig.15 DRN ON RESISTANCE 95 VS 10 20 T a [℃] Fig.14 DRP ON RESISTANCE 100 100 0 T a [℃] T a [℃] VGH VGL 8 9 10 11 12 13 14 VIN [V] Fig.20 STEP DOWN EFFICIENCY 5/18 Fig.21 START UP WAVEFORM 2009.07 - Rev.B BD8160AEFV Technical Note ●Block Diagram AVIN OS REF VREF FREQ OSC PG UVLO TSD VREG GD CURRENT SENSE OVP SW SW OCP S DRV EN2 SOFT START SS SLOPE PWM PGND R CURRENT SENSE VINB VINB OCP ERR FB S EN1 COMP SLOPE DRV PWM SWB R SOFT START BOOT ERR FBB SUP EN1 DETECTOR Short Circuit Protection FB FBB FBP FBN PG EN2 SUP POSITIVE CHARGE PUMP ERR FBP DRP EN2 SUP NEGATIVE CHARGE PUMP FBN DRN IDLY DLY 1 IDLY 1 IDLY DLY 2 IDLY 2 GND Fig.22 Block Diagram ●Typical Application VIN 12V L1 10μH Boostout C40 4*10μF C18 1μF 8 12 20 21 22 16 D4D5 DAN217U VGL -5V/50mA C8 4.7μF C2 0.022μ 9 11 13 R3 51k 24 6 R4 10k 7 28 C9 0.047μF 25 C3 0.1μF D2 RSX501 SUP SW FREQ SW VINB FB VINB OS AVIN GN EN1 GD EN2 DRP DRN FBP FBN BOOT REF SW PGN NC PGN FBB COMP SS DLY1 C5 0.047μF DLY2 4 5 C6 120pF R12 47k R5 120k C28 3*10μF 1 R6 10k 3 23 Vs 15V/1.5A Q1 RSQ035P0 3 D4D6 DAN217U C21 20μF C27 0μF C23 0.1μF R2 0Ω R15 47k 27 10 C14 0.1μF 14 R9 22k 17 C22 4.7μF VGH 28V/50mA R10 1k 18 19 15 2 C1 2200pF C11 0.1μF 26 C4 0.1μF R1 7.5k D1 RSX501 ○ EN1 terminal should be pulled-up to VIN terminal. VLOGIC 3.3V/1.5A L2 10μH R7 200k C15 68pF C12 4*10μF R8 115k Fig.23 Typical Application www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/18 2009.07 - Rev.B BD8160AEFV Technical Note DLY2 DLY1 REF GND AVIN VINB VINB N.C. SWB BOOT EN1 FBB SW SW PGND PGND SUP EN2 DRP DRN FREQ FBN FBP GD COMP OS SS FB ●Pin Assignment Diagram Fig. 24 Pin Assignment Diagram ●Pin Assignment and Pin Function Pin No. Pin name Function 1 FB 2 Pin No. Pin name Function Feedback input 1 for VS 15 FBB Feedback input for Vlogic COMP Error amp output 16 EN1 Enable pin for Vlogic and VGL 3 OS Output sense pin 17 BOOT Capacitance connection pin for booting 4 SW Switching pin for VS 18 SWB Switching pin for Vlogic 5 SW Switching pin for VS 19 N.C. Non-connect pin 6 PGND Ground pin 20 VINB Power supply input pin 7 PGND Ground pin 21 VINB Power supply input pin 8 SUP Power supply input pin 22 AVIN Power supply input pin 9 EN2 Enable pin for VS and VGH 23 GND Analog Ground pin 10 DRP Switching pin for VGH 24 REF Internal reference output pin 11 DRN Switching pin for VGL 25 DLY1 Delay start capacitance connection pin for VGL 12 FREQ Frequency 26 DLY2 Delay start capacitance connection pin for VS 13 FBN Feedback input 1 for VGL 27 GD Gate drive pin for load switch 14 FBP Feedback input 1 for VGH 28 SS Soft start capacitance connection pin for VS www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/18 2009.07 - Rev.B BD8160AEFV Technical Note ●Block Operation VREG A block to generate constant-voltage for DC/DC boosting. VREF A block that generates internal reference voltage of 2.9 V (Typ.). TSD/UVLO TSD (Thermal shutdown)/UVLO (Under Voltage Lockout) protection block. The TSD circuit shuts down IC at 175°C (Typ.) The UVLO circuit shuts down the IC when the Vcc is 7 V (Typ.) or below. Error amp block (ERR) This is the circuit to compare the reference voltage and the feedback voltage of output voltage. The COMP pin voltage resulting from this comparison determines the switching duty. At the time of startup, since the soft start is operated by the SS pin voltage, the COMP pin voltage is limited to the SS pin voltage. Oscillator block (OSC) This block generates the oscillating frequency. SLOPE block This block generates the triangular waveform from the clock created by OSC. Generated triangular waveform is sent to the PWM comparator. PWM block The COMP pin voltage output by the error amp is compared to the SLOPE block's triangular waveform to determine the switching duty. Since the switching duty is limited by the maximum duty ratio which is determined internally, it does not become 100%. DRV block A DC/DC driver block. A signal from the PWM is input to drive the power FETs. CURRENT SENSE Current flowing to the power FET is detected by voltage at the CURRENT SENSE and the overcurrent protection operates at 2.0/2.6A (min.). When the overcurrent protection operates, switching is turned OFF and the SS pin capacitance is discharged. DELAY START A start delay circuit for positive/negative charge pump and Boost converter. Soft start circuit Since the output voltage rises gradually while restricting the current at the time of startup, it is possible to prevent the output voltage overshoot or the rush current. Positive charge pump A controller circuit for the positive-side charge pump. The switching amplitude is controlled so that the feedback voltage FBP will be set to 1.213 V (Typ.). The start delay time can be set in the DLY2 pin at the time of startup. When the DLY2 voltage reaches 0.65 V (Typ.), switching waves will be output from the DRP pins. Negative charge pump A controller circuit for the negative-side charge pump. The switching amplitude is controlled so that the feedback voltage FBN will be set to 0.2 V (Typ.). The start delay time can be set in the DLY1 pin at the time of startup. When the DLY2 voltage reaches 0.65 V (Typ.), switching waves will be output from the DRN pins. Over Voltage protection of the Boost Converter The boost converter has an overvoltage protection to protect the internal power MOS FET (SW) in case the feed back (FB) pin is floating or shorted to GND. Vs voltage is monitored with comparator over the OS pin. When the voltage of OS pin reached 19V (typ.), the Boost Converter stops its switching until the OS pin voltage falls below the comparator threshold. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/18 2009.07 - Rev.B BD8160AEFV Technical Note ●Start-up Sequence The DC/DC converter of this IC incorporates a soft start function, and the charge pump incorporates a delay function, for which independent time settings are possible through external capacitors. As the capacitance, 0.01 µF to 0.1 µF is recommended. If the capacitance is set lower than 0.01 µF, the overshooting may occur on the output voltage. If the capacitance is set larger than 0.1 µF, the excessive back current flow may occur in the internal parasitic elements when the power is turned OFF and it may damage IC. When the capacitor more than 0.1 µF is used, be sure to insert a diode to VIN in series, or a bypass diode between the SS and VIN pins. Bypass diode Back current prevention diode VIN Fig.25 Example of Bypass Diode Use When there is the activation relation (sequences) with other power supplies, be sure to use the high-precision product (such as X5R). Soft start time may vary according to the input voltage, output loads, coils, voltage, and output capacitance. Be sure to verify the operation using the actual product. A delay of the charge pump starts from a point where VLOGIC reaches 85% of its nominal value (Typ.). Soft start time of DC/DC converter block: tss Delay time of charge pump block: t DELAY Tss = (Css × 0.6 V) / 10 μA [s] t DELAY = (Css ×0.65) / 5 μA [s] Where, Css is an external capacitor. Where, Css is an external capacitor. Startup example EN2 DLY2 EN1 VGH Vs Vin VLOGIC DLY1 VGL GD Fig. 26 Output Timing Sequence with EN2 always high (EN2=VIN) EN2 DLY2 EN1 Vin VGH Vs VLOGIC DLY1 VGL GD Fig. 27 Output Timing Sequence(with using EN1 and EN2) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/18 2009.07 - Rev.B BD8160AEFV Technical Note ●Short Circuit Protection BD8160AEFV has a short circuit protection feature to prevent the large current flowing when the output is shorted to GND. This function is monitoring VS, VLOGIC, VGH and VGL voltage and starts the timer when at least one of the outputs is not operating properly (when the output voltage was lower than expected) After TBD ms (Typ) of this abnormal state, BD8160AEFV will shutdown the all outputs and latch the state. The timer operation will be done even when BD8160AEFV starts up. Therefore, please adjust the capacitor for SS, DLY1 and DLY2 (Softstart and Delaystart) so that the all output voltage reach the expected value within the Short Circuit Protection Time (TBD ms Typ) VS FB - 219 / 328 ms (Typ) of this abnormal state, 219 / 328 ms (typ) Counter + BD8160AEFV will shutdown the all outputs and latch the state. Reset VLOGIC FBB ALL SHUTDOWN & LATCH - + VS is shorted to GND VIN 92% detection VGH 84% detection VLOGIC is shorted FBP VS to GND - 82% detection + 72% detection VLOGIC 80% detection 70% detection VGH VGH,VGL are shorted + - to GND VGL 80% detection Start Up time 70% detection Short Circuit Protection Time (Start up time should be less than Short Circuit Protection Time) Fig. 28 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/18 2009.07 - Rev.B BD8160AEFV Technical Note ●Selecting Application Components (1) Output LC constant (Boost Converter) The inductance L to use for output is decided by the rated current ILR and input current maximum value IOMAX of the inductance. VCC IOMAX + IL should not reach the rated value level IL IL ILR Vo IOMAX mean current L Co t Fig. 29 Fig. 30 Adjust so that IOMAX + ∆IL does not reach the rated current value ILR. At this time, ∆IL can be obtained by the following equation. 1 Vo-Vcc 1 Vcc [A] ∆IL = L Vo f Set with sufficient margin because the inductance L value may have the dispersion of ± 30%. For the capacitor C to use for the output, select the capacitor which has the larger value in the ripple voltage VPP permissible value and the drop voltage permissible value at the time of sudden load change. Output ripple voltage is decided by the following equation. 1 Vcc ∆IL = ILMAX RESR + ( ILMAX ) [V] ∆VPP fCo Vo 2 Perform setting so that the voltage is within the permissible ripple voltage range. For the drop voltage VDR during sudden load change, please perform the rough calculation by the following equation. ∆I 10 µs [V] VDR = Co However, 10 µs is the rough calculation value of the DC/DC response speed. Make Co settings so that these two values will be within the limit values. (2) Output LC constant (Buck Converter) The inductance L to use for output is decided by the rated current ILR and input current maximum value IOMAX of the inductance. IOMAX + IL should not reach the rated value level IL VCC ILR IL IOMAX mean current L Vo Co t Fig. 31 Fig. 32 Adjust so that IOMAX + ∆IL does not reach the rated current value ILR. At this time, ∆IL can be obtained by the following equation. 1 Vo 1 (Vcc - Vo) ∆IL = [A] L Vcc f Set with sufficient margin because the inductance L value may have the dispersion of ± 30%. For the capacitor C to use for the output, select the capacitor which has the larger value in the ripple voltage VPP permissible value and the drop voltage permissible value at the time of sudden load change. Output ripple voltage is decided by the following equation. Vo 1 ∆IL [V] = ∆IL RESR + ∆VPP 2Co Vcc f Perform setting so that the voltage is within the permissible ripple voltage range. For the drop voltage VDR during sudden load change, please perform the rough calculation by the following equation. ∆I VDR = 10 µs [V] Co However, 10 µs is the rough calculation value of the DC/DC response speed. Make Co settings so that these two values will be within the limit values. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 11/18 2009.07 - Rev.B BD8160AEFV Technical Note (3) Phase compensation Phase Setting Method The following conditions are required in order to ensure the stability of the negative feedback circuit. Phase lag should be 150° or lower during gain 1 (0 dB) (phase margin of 30° or higher). Because DC/DC converter applications are sampled using the switching frequency, the overall GBW should be set to 1/10 the switching frequency or lower. The target application characteristics can be summarized as follows: Phase lag should be 150° or lower during gain 1 (0 dB) (phase margin of 30° or higher). The GBW at that time (i.e., the frequency of a 0-dB gain) is 1/10 of the switching frequency or below. In other words, because the response is determined by the GBW limitation, it is necessary to use higher switching frequencies to raise response. One way to maintain stability through phase compensation involves canceling the secondary phase lag (-180°) caused by LC resonance with a secondary phase advance (by inserting 2 phase advances). The GBW (i.e., the frequency with the gain set to 1) is determined by the phase compensation capacitance connected to the error amp. Increase the capacitance if a GBW reduction is required. (a) Standard integrator (low-pass filter) (b) Open loop characteristics of integrator (a) A ＋ COMP A Feedback R -20 dB/decade Gain [dB] GBW(b) 0 － FB F 0 C -90° Phase -90 [°] Phase margin -180° -180 F Fig. 33 Point (a) fa = Fig. 34 1 2πRCA [Hz] Point (b) fb = GBW = 1 2πRC [Hz] The error amp performs phase compensation of types (a) and (b), making it act as a low-pass filter. For DC/DC converter applications, R refers to feedback resistors connected in parallel. From the LC resonance of output, the number of phase advances to be inserted is two. LC resonant frequency fp = Vo R1 2π√LC [Hz] C1 ＋ R2 1 － A COMP Phase advance fz1 = 1 2πC1R1 [Hz] Phase advance fz2 = 1 2πC2R3 [Hz] C2 R3 Fig. 35 Set a phase advancing frequency close to the LC resonant frequency for the purpose of canceling the LC resonance. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 12/18 2009.07 - Rev.B BD8160AEFV Technical Note (4) Design of Feedback Resistance constant Set the feedback resistance as shown below. Reference voltage (FB:1.162V FBB:1.213V) VS VLOGIC ＋ R1 ERR － FB FBB R2 VS, VLOGIC = R1 + R2 R2 Reference Voltage [V] Fig. 36 (5) Positive-side Charge Pump Settings The IC incorporates a charge pump controller, thus making it possible to generate stable gate voltage. The output voltage is determined by the following equation. As the setting range, 10kΩ to 330kΩ is recommended. If the resistor is set lower than 10kΩ, it causes reduction of power efficiency. If it is set more than 330kΩ, the offset voltage becomes larger by the input bias current of 0.1µA (Typ.) in the internal error amp. Vo2 Reference voltage 1.213V R6 ＋ Vo2 = ERR FBP R7 － R6 + R7 R7 Reference Voltage [V] Fig. 37 By connecting capacitance to the DLY2 pin, the rising delay time can be set for the positive-side charge pump output. The delay time is determined by the following equation. Delay time of charge pump block t DELAY t DELAY = (CDLS 0.65) / 5 µA [s] Where, CDLS is an external capacitor. (6) Negative-side Charge Pump Settings BD8160AEFV incorporates a charge pump controller for negative voltage, thus making it possible to generate stable gate voltage. The output voltage is determined by the following equation. As the setting range, 10kΩ to 330kΩ is recommended. If the resistor is set lower than 10kΩ, it causes reduction of power efficiency. If it is set more than 330kΩ, the offset voltage becomes larger by the input bias current of 0.1µA (Typ.) in the internal error amp. VGL 0.2V R8 － VGL = ERR ＋ R9 - R8 R9 1.013 + 0.2 V [V] FBN REF 1.213V Fig.38 Like the positive-side charge pump, the rise delay time can be set by connecting capacitance to the DLY1 pin. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 13/18 2009.07 - Rev.B BD8160AEFV Technical Note ●Selecting the Feedforward Capacitor (Boost Converter) Across the upper resistor R1, a bypass capacitor is needed to have a stable converter loop. C1 will set a zero in the loop together with R1. L=10µH C1 R1 1 2πfz1R1 C1 = Fz1=11kHz @L=10µH COMP R2 C2 Fig.39 The regulator loop can be compensated by adjusting the exfernal components connected to the COMP pin. C2,R2 are decided by the following formula. 1 2πC2R2 Fz1=11kHZ = ●Selecting the Feedforward Capacitor (Buck converter) The feedforward capacitor across the upper feedback resistor divider sets a zero in the control loop. L=l0µH C3 = R3 1 2πfz2R3 Fz2=12kHz @L=10µH C3 FBB Fig.40 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14/18 2009.07 - Rev.B BD8160AEFV Technical Note ●I/O Equivalent Circuit Diagram 18.SWB 17.BOOT Vcc 25.DLY1 26.DLY2 28.SS Vcc PVcc REG SW 2.COMP 24.REF VR 1.FB Vcc 9.EN2 12.FREQ 16.EN1 13.FBN 14.FBP 15.FBB 27.GD VR 10.DRP 11.DRN 4.SW 5.SW Vo1 3.OS Fig.41 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 15/18 2009.07 - Rev.B BD8160AEFV Technical Note ●Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. 3) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 7) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 8) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when the resistors and transistors are connected to the pins as shown in Fig.42, a parasitic diode or a transistor operates by inverting the pin voltage and GND voltage. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements such as by the application of voltages lower than the GND (P substrate) voltage to input and output pins. Resistor Transistor (NPN) (Pin B) ～ ～ B E ～ ～ C (Pin B) ～ ～ B (Pin A) GND N P P+ N N Parasitic elements N (Pin A) P substrate Parasitic elements GND N P+ ～ ～ P+ N P GND N P P+ Parasitic elements C E Parasitic elements GND GND Fig. 42 Example of a Simple Monolithic IC Architecture 9) Overcurrent protection circuits An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative characteristics to temperatures. 10) Thermal shutdown circuit (TSD) This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the chip's junction temperature Tj will trigger the TSD circuit to turn off all output power elements. Operation of the TSD circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD circuit. 11) Testing on application boards At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. 12) EN1 terminal EN1 terminal should be pulled up to VIN terminal. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 16/18 2009.07 - Rev.B BD8160AEFV Technical Note POWER DISSIPATION: PD [mW] ●Power Dissipation On 70 70 1.6 mm glass epoxy PCB 5000 (4)4700mW 4000 (3)3300mW (1) 1-layer board (Backside copper foil area 0 mm 0 mm) (2) 2-layer board (Backside copper foil area 15 mm 15 mm) (3) 2-layer board (Backside copper foil area 70 mm 70 mm) (4) 4-layer board (Backside copper foil area 70 mm 70 mm) 3000 (2)1850mW 2000 1000 (1)1450mW 0 0 25 50 75 100 125 150 AMBIENT TEMPERATURE: Ta [°C] Fig. 43 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 17/18 2009.07 - Rev.B BD8160AEFV Technical Note ●Ordering part number B D 8 Part No. 1 6 0 A E Part No. F V Package EFV : HTSSOP-B28 - E 2 Packaging and forming specification E2: Embossed tape and reel HTSSOP-B28 <Tape and Reel information> 9.7±0.1 (MAX 10.05 include BURR) (5.5) 1 Tape Embossed carrier tape (with dry pack) Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 14 +0.05 0.17 -0.03 1PIN MARK 1.0MAX 0.625 1.0±0.2 (2.9) 0.5±0.15 15 4.4±0.1 6.4±0.2 28 +6° 4° −4° 0.08±0.05 0.85±0.05 S 0.08 S 0.65 +0.05 0.24 -0.04 0.08 1pin M (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Reel 18/18 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.07 - Rev.B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. R0039A