TI BQ3285LDSSTR Real-time clock (rtc) Datasheet

bq3285ED/LD
Real-Time Clock (RTC)
Features
General Description
➤ ACPI-compliant
day-of-month alarm
The CMOS bq3285ED/LD is a lowpower microprocessor peripheral providing a time-of-day clock and 100year calendar with alarm features
and battery operation. The architecture is based on the bq3285/7 RTC
with added features: low-voltage operation, 32.768kHz output, 128 additional bytes of CMOS, and a day-ofmonth alarm to be compliant with
the ACPI RTC specification.
➤ Direct clock/calendar replacement for IBM® AT-compatible
computers and other applications
➤ 2.7–5.5V operation (bq3285LD);
4.5–5.5V operation (bq3285ED)
➤ 242 bytes of general nonvolatile
storage
➤ Dedicated 32.768kHz output pin
➤ System wake-up capability—
alarm interrupt output active in
battery-backup mode
➤ Less than 0.55µA load under battery operation
➤ Selectable Intel or Motorola bus
timing
➤ 24-pin plastic SSOP
Pin Connections
A 32.768kHz output is available for
sustaining power-management activities. The bq3285ED/LD 32kHz
output is always on whenever VCC is
valid. In V CC standby mode, the
32kHz is active, and the bq3285LD
typically draws 100µA while the
bq3285ED typically draws 300µA.
Wake-up capability is provided by
an alarm interrupt, which is active
in battery-backup mode. In batterybackup mode, current drain is less
than 550nA.
The bq3285ED/LD write-protects the
clock, calendar, and storage registers
during power failure. A backup
battery then maintains data and operates the clock and calendar.
The bq3285ED/LD is a fully compatible real-time clock for IBM ATcompatible computers and other applications. The only external components are a 32.768kHz crystal and a
backup battery.
The bq3285ED is intended for use in
5V systems. The bq3285LD is intended for use in 3V systems; the
bq3285LD, however, may also operate at 5V and then go into a 3V
power-down state, write-protecting
as if in a 3V system.
Pin Names
AD0–AD7
Multiplexed address/
data input/output
MOT
Bus type select input
CS
Chip select input
AS
Address strobe input
DS
Data strobe input
R/W
Read/write input
INT
Interrupt request output
RST
Reset input
32K
32.768kHz output
EXTRAM Extended RAM enable
MOT
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
32k
EXTRAM
RCL
BC
INT
RST
DS
VSS
R/W
AS
CS
24-Pin SSOP
PN3285ED/LD.eps
July 1997
1
RCL
RAM clear input
BC
3V backup cell input
X1–X2
Crystal inputs
VCC
Power supply
VSS
Ground
bq3285ED/LD
Block Diagram
X1
TimeBase
Oscillator
X2
4
3
RST
÷8
÷ 64
÷ 64
16 : 1 MUX
32K
32K
Driver
Control/Status
Registers
MOT
CS
µP
Bus
I/F
R/W
AS
AD0–AD7
User Buffer
(14 Bytes)
DS
Control/Calendar
Update
Storage Registers
(114 Bytes)
RCL
INT
Interupt
Generator
Clock/Calendar, Alarm
and Control Bytes
Storage Registers
(128 Bytes)
EXTRAM
CS
VCC
PowerFail
Control
BC
VOUT
Write
Protect
BD328501.eps
AD0–AD7
Pin Descriptions
MOT
Bus type select input
The bq3285ED/LD bus cycle consists of two
phases: the address phase and the datatransfer phase. The address phase precedes the data-transfer phase. During the
address phase, an address placed on
AD0–AD7 and EXTRAM is latched into the
bq3285ED/LD on the falling edge of the AS
signal. During the data-transfer phase of
the bus cycle, the AD0–AD7 pins serve as a
bidirectional data bus.
MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to VCC for Motorola timing or to VSS for
Intel timing (see Table 1). The setting
should not be changed during system operation. MOT is internally pulled low by a 30K
Ω resistor.
Table 1. Bus Setup
AS
Bus
Type
MOT
DS
R/W
AS
Level Equivalent Equivalent Equivalent
Motorola
VCC
DS, E, or
Φ2
R/W
Intel
VSS
RD,
MEMR, or
I/OR
WR,
MEMW, or ALE
I/OW
Multiplexed address/data
input/output
Address strobe input
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the address on AD0–AD7 and EXTRAM. This demultiplexing process is independent of the
CS signal. For DIP and SOIC packages
with MOT = VSS, the AS input is provided a
signal similar to ALE in an Intel-based system.
AS
July 1997
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bq3285ED/LD
DS
RCL
Data strobe input
When MOT = VCC, DS controls data transfer during a bq3285ED/LD bus cycle. During a read cycle, the bq3285ED/LD drives
the bus after the rising edge on DS. During
a write cycle, the falling edge on DS is used
to latch write data into the chip.
A low level on the RCL pin causes the contents of each of the 242 storage bytes to be
set to FF(hex). The contents of the clock
and control registers are unaffected. This
pin should be used as a user-interface input
(pushbutton to ground) and not connected
to the output of any active component. RCL
input is only recognized when held low for
at least 125ms in the presence of VCC. Using RAM clear does not affect the battery
load. This pin is connected internally to a
30kΩ pull-up resistor.
When MOT = VSS, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.
R/W
Read/write input
BC
When MOT = VCC, the level on R/W identifies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.
Upon power-up, a voltage within the VBC
range must be present on the BC pin for
the oscillator to start up.
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cycle accessing the bq3285ED/LD.
INT
RST
Interrupt request output
Reset may be disabled by connecting RST
to VCC. This allows the control bits to reta i n th e i r s ta te s th ro u g h p o w erdown/power-up cycles.
X1–X2
32.768 kHz output
Crystal inputs
The X1–X2 inputs are provided for an external 32.768kHz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capacitance. A trimming capacitor may be necessary for extremely precise time-base generation.
32K provides a buffered 32.768 kHz output.
The frequency remains on and fixed at
32.768kHz as long as VCC is valid.
EXTRAM
Reset input
The bq3285ED/LD is reset when RST is
pulled low. When reset, INT becomes high
impedance, and the bq3285ED/LD is not accessible. Table 4 in the Control/Status Registers section lists the register bits that are
cleared by a reset.
INT is an open-drain output. This allows
alarm INT to be valid in battery-backup
mode. To use this feature, connect INT
through a resistor to a power supply other
than VCC. INT is asserted low when any
event flag is set and the corresponding
event enable bit is also set. INT becomes
high-impedance whenever register C is read
(see the Control/Status Registers section).
32K
3V backup cell input
BC should be connected to a 3V backup cell
for RTC operation and storage register nonvolatility in the absence of system power.
When VCC slews down past VBC (3V typical), the integral control circuitry switches
the power source to BC. When VCC returns
above VBC, the power source is switched to
VCC.
When MOT = VSS, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intelbased system. The rising edge on R/W
latches data into the bq3285ED/LD.
CS
RAM clear input
Extended RAM enable
In the absence of a crystal, a 32.768kHz
waveform can be fed into the X1 input.
Enables 128 bytes of additional nonvolatile
SRAM. It is connected internally to a 30kΩ
pull-down resistor. To access the RTC registers, EXTRAM must be low.
July 1997
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bq3285ED/LD
Functional Description
each update period (see Figure 2). The alarm flag bit
may also be set during the update cycle.
Address Map
The bq3285ED/LD copies the local register updates into
the user buffer accessed by the host processor. When a 1
is written to the update transfer inhibit bit (UTI) in register B, the user copy of the clock and calendar bytes remains unchanged, while the local copy of the same bytes
continues to be updated every second.
The bq3285ED/LD provides 14 bytes of clock and control/status registers and 242 bytes of general nonvolatile
storage. Figure 1 illustrates the address map for the
bq3285ED/LD.
The update-in-progress bit (UIP) in register A is set
tBUC time before the beginning of an update cycle (see
Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.
Update Period
The update period for the bq3285ED/LD is one second.
The bq3285ED/LD updates the contents of the clock and
calendar locations during the update cycle at the end of
0
16 Bytes
13
Clock and
Control Status
Registers
14
00
0
1
0D
0E
Storage
Registers
with
EXTRAM = 0
114
Bytes
00
Seconds
Seconds Alarm 01
2
Minutes
02
3
Minutes Alarm
03
4
Hours
04
5
Hours Alarm
05
127
7F
6
Day of Week
06
0
00
7
Date of Month
07
8
Month
08
9
Year
09
10
Register A
0A
11
Register B
Register C
Day of Month
Alarm
0B
Storage
Registers
with
EXTRAM = 1
128
Bytes
12
127
13
7F
BCD
or
Binary
Format
0C
0D
FG328501.eps
Figure 1. Address Map
Update Period
(1 sec.)
UIP
tUC (Update Cycle)
tBUC
TD3285e1.eps
Figure 2. Update Period Timing and UIP
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bq3285ED/LD
Programming the RTC
2.
Write new values to all the time, alarm, and
calendar locations.
The time-of-day, alarm, and calendar bytes can be written in either the BCD or binary format (see Table 2).
3.
Clear the UTI bit to allow update transfers.
On the next update cycle, the RTC updates all 10 bytes
in the selected format.
These steps may be followed to program the time, alarm,
and calendar:
1.
Modify the contents of register B:
a.
Write a 1 to the UTI bit to prevent transfers between RTC bytes and user buffer.
b.
Write the appropriate value to the data
format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.
c.
Write the appropriate value to the hour
format (HF) bit.
Table 2. Time, Alarm, and Calendar Formats
Range
Address
RTC Bytes
Decimal
Binary
Binary-Coded
Decimal
0
Seconds
0–59
00H–3BH
00H–59H
1
Seconds alarm
0–59
00H–3BH
00H–59H
2
Minutes
0–59
00H–3BH
00H–59H
3
Minutes alarm
0–59
00H–3BH
00H–59H
Hours, 12-hour format
1–12
01H–OCH AM;
81H–8CH PM
01H–12H AM;
81H–92H PM
Hours, 24-hour format
0–23
00H–17H
00H–23H
Hours alarm, 12-hour format
1–12
01H–OCH AM;
81H–8CH PM
01H–12H AM;
81H–92H PM
Hours alarm, 24-hour format
0–23
00H–17H
00H–23H
6
Day of week (1=Sunday)
1–7
01H–07H
01H–07H
7
Day of month
1–31
01H–1FH
01H–31H
8
Month
1–12
01H–0CH
01H–12H
9
Year
0–99
00H–63H
00H–99H
D
Day of month alarm
1–31
01H-1FH
01–31H
4
5
July 1997
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bq3285ED/LD
The bq3285ED/LD provides for a 32.768kHz output, and
the output is always active whenever VCC is valid (VPFD
+ tCSR). The bq3285ED/LD output is not affected by the
bit settings in Register A. Time-keeping aspects, however, still require setting OS0-OS2.
Each of the three interrupt events is enabled by an individual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corresponding event enable bit is also set, then an interrupt
request is generated. The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT high-impedance.
Interrupts
Two methods can be used to process bq3285ED/LD interrupt events:
The bq3285ED/LD allows three individually selected interrupt events to generate an interrupt request. These
three interrupt events are:
n Enable interrupt events and use the interrupt
request output to invoke an interrupt service routine.
n The periodic interrupt, programmable to occur once
every 122µs to 500ms.
n Do not enable the interrupts and use a polling
routine to periodically check the status of the flag
bits.
32kHz Output
n The alarm interrupt, programmable to occur once per
second to once per day, is active in battery-backup
mode, providing a “wake-up” feature.
The individual interrupt sources are described in detail
in the following sections.
n The update-ended interrupt, which occurs at the end
of each update cycle.
Table 3. Periodic Interrupt Rate
Register A Bits
Periodic Interrupt
OSC2
OSC1
OSC0
RS3
RS2
RS1
RS0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
3.90625
ms
0
1
0
0
0
1
0
7.8125
ms
0
1
0
0
0
1
1
122.070
µs
0
1
0
0
1
0
0
244.141
µs
0
1
0
0
1
0
1
488.281
µs
0
1
0
0
1
1
0
976.5625
0
1
0
0
1
1
1
1.95315
ms
0
1
0
1
0
0
0
3.90625
ms
0
1
0
1
0
0
1
7.8125
ms
0
1
0
1
0
1
0
15.625
ms
0
1
0
1
0
1
1
31.25
ms
0
1
0
1
1
0
0
62.5
0
1
0
1
1
0
1
125
ms
0
1
0
1
1
1
0
250
ms
0
1
0
1
1
1
1
500
ms
0
1
1
X
X
X
X
Period
Units
None
µs
ms
same as above defined
by RS3–RS0
July 1997
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bq3285ED/LD
n If the day-of-the-month, hour, minute, and second
alarm bytes are “don't care,” the frequency is once
per second.
Periodic Interrupt
If the periodic interrupt event is enabled by writing a 1
to the periodic interrupt enable bit (PIE) in register C,
an interrupt request is generated once every 122µs to
500ms. The period between interrupts is selected with
bits RS3-RS0 in register A (see Table 3).
Update Cycle Interrupt
The update cycle ended flag bit (UF) in register C is set to
a 1 at the end of an update cycle. If the update interrupt
enable bit (UIE) of register B is 1, and the update transfer
inhibit bit (UTI) in register B is 0, then an interrupt request is generated at the end of each update cycle.
Alarm Interrupt
The alarm interrupt is active in battery-backup mode,
providing a “wake-up” capability. During each update
cycle, the RTC compares the day-of-the-month, hours,
minutes, and seconds bytes with the four corresponding
alarm bytes. If a match of all bytes is found, the alarm
interrupt event flag bit, AF in register C, is set to 1. If
the alarm event is enabled, an interrupt request is generated.
Accessing RTC bytes
The EXTRAM pin must be low to access the RTC registers. Time and calendar bytes read during an update
cycle may be in error. Three methods to access the time
and calendar bytes without ambiguity are:
An alarm byte may be removed from the comparison by
setting it to a “don't care” state. The seconds, minutes,
and hours alarm bytes are set to a “don't care” state by
writing a 1 to each of its two most-significant bits. The
day-of-the-month alarm byte is set to a “don’t care” state
by setting DA5–DA0, in register D, to all zeros. A “don't
care” state may be used to select the frequency of alarm
interrupt events as follows:
n Enable the update interrupt event to generate
interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).
n Poll the update-in-progress bit (UIP) in register A. If
UIP = 0, the polling routine has a minimum of tBUC
time to access the clock bytes (see Figure 3).
n If none of the four alarm bytes is “don't care,” the
frequency is once per month, when day-of-the-month,
hours, minutes, and seconds match.
n Use the periodic interrupt event to generate
interrupt requests every tPI time, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler has a minimum of tPI/2 + tBUC
time to access the clock bytes (see Figure 3).
n If only the day-of-the-month alarm byte is “don’t
care”, the frequency is once per day, when hours,
minutes, and seconds match.
n If only the day-of-the-month and hour alarm byte is
“don't care,” the frequency is once per hour, when
minutes and seconds match.
Oscillator Control
n If only the day-of-the-month, hour and minute alarm
bytes are “don't care,” the frequency is once per
minute, when seconds match.
When power is first applied to the bq3285ED/LD and
VCC is above VPFD, the internal oscillator and frequency
divider are turned on by writing a 010 pattern to bits 4
through 6 of register A. A pattern of 11X turns the oscillator on but keeps the frequency divider disabled. Any
1 Sec.
UIP
tUC
(tPl)/2
(tPl)/2
tPl
tBUC
PF
UF
T3285L02.eps
Figure 3. Update-Ended/Periodic Interrupt Relationship
July 1997
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bq3285ED/LD
other pattern to these bits keeps the oscillator off. A
pattern of 010 must be set for the bq3285ED/LD to keep
time in battery backup mode.
Register A
7
UIP
Power-Down/Power-Up Cycle
The bq3285ED and bq3285LD power-up/power-down cycles are different. The bq3285LD continuously monitors
VCC for out-of-tolerance. During a power failure, when
VCC falls below VPFD (2.53V typical), the bq3285LD writeprotects the clock and storage registers. The power source
is switched to BC when VCC is less than VPFD and BC is
greater than VPFD, or when VCC is less than VBC and VBC
is less than VPFD. RTC operation and storage data are
sustained by a valid backup energy source. When VCC is
above VPFD, the power source is VCC. Write-protection continues for tCSR time after VCC rises above VPFD.
6
OS2
5
OS1
Register A Bits
4
3
2
OS0 RS3 RS2
1
RS1
0
RS0
1
RS1
0
RS0
Register A programs:
n The frequency of the periodic event rate.
n Oscillator operation.
n Time-keeping
Register A provides:
n Status of the update cycle.
RS0–RS3 - Frequency Select
The bq3285ED continuously monitors VCC for out-oftolerance. During a power failure, when VCC falls below
VPFD (4.17V typical), the bq3285ED write-protects the
clock and storage registers. When VCC is below VBC (3V
typical), the power source is switched to BC. RTC operation and storage data are sustained by a valid backup
energy source. When V CC is above V BC, the power
source is VCC. Write-protection continues for tCSR time
after VCC rises above VPFD.
7
-
6
-
5
-
4
-
3
RS3
2
RS2
These bits select the periodic interrupt rate, as shown in
Table 3.
OS0–OS2 - Oscillator Control
7
-
Control/Status Registers
The four control/status registers of the bq3285ED/LD
are accessible regardless of the status of the update cycle (see Table 4).
6
OS2
5
OS1
4
OS0
3
-
2
-
1
-
0
-
These three bits control the state of the oscillator and
divider stages. A pattern of 010 or 011 enables RTC operation by turning on the oscillator and enabling the frequency divider. This pattern must be set to turn the oscillator on and to ensure that the bq3285ED/LD keeps
time in battery-backup mode. A pattern of 11X turns the
oscillator on, but keeps the frequency divider disabled.
When 010 is written, the RTC begins its first update after 500ms.
Table 4. Control/Status Registers
Reg.
Bit Name and State on Reset
Loc.
(Hex) Read Write
1
7 (MSB)
6
5
4
3
A
0A
Yes
Yes
UIP
na OS2 na OS1 na OS0 na
B
0B
Yes
Yes
UTI
na
PIE
0
C
0C
Yes
No
INTF
0
PF
0
D
0D
Yes
Yes2
VRT
na
-
0
Notes:
AIE
0
UIE
0
AF
0
UF
0
DA5 na DA4 na
RS3
DA3
2
1
0 (LSB)
na RS2 na RS1 na
0
DF
na
HF
0
-
na
-
RS0 na
na DSE na
0
na DA2 na DA1 na
-
0
DA0 na
na = not affected.
1. Except bit 7.
2. Except bits 6 and 7.
July 1997
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bq3285ED/LD
DF - Data Format
UIP - Update Cycle Status
7
UIP
6
-
5
-
4
-
3
-
2
-
1
-
0
-
7
-
This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.
6
PIE
5
-
4
-
3
-
2
DF
1
-
0
-
This bit selects the numeric format in which the time,
alarm, and calendar bytes are represented:
1 = Binary
0 = BCD
Register B
7
UTI
6
-
Register B Bits
5
4
3
2
AIE UIE
DF
UIE - Update Cycle Interrupt Enable
1
HF
0
DSE
7
-
Register B enables:
6
-
5
-
4
UIE
3
-
2
-
1
-
0
-
This bit enables an interrupt request due to an update
ended interrupt event:
n Update cycle transfer operation
1 = Enabled
n Interrupt events
0 = Disabled
n Daylight saving adjustment
The UIE bit is automatically cleared when the UTI bit
equals 1.
Register B selects:
n Clock and calendar data formats
AIE - Alarm Interrupt Enable
All bits of register B are read/write.
7
-
Bit 3 - Unused Bit.
6
-
5
AIE
4
-
3
-
2
-
1
-
0
-
DSE - Daylight Saving Enable
7
-
6
-
5
-
4
-
3
-
2
-
1
-
This bit enables an interrupt request due to an alarm
interrupt event:
0
DSE
1 = Enabled
0 = Disabled
This bit enables daylight-saving time adjustments when
written to 1:
PIE - Periodic Interrupt Enable
n On the last Sunday in October, the first time the
bq3285ED/LD increments past 1:59:59 AM, the time
falls back to 1:00:00 AM.
7
-
6
PIE
5
-
4
-
3
-
2
-
1
-
0
-
n On the first Sunday in April, the time springs
forward from 2:00:00 AM to 3:00:00 AM.
This bit enables an interrupt request due to a periodic
interrupt event:
HF - Hour Format
7
-
6
-
5
-
4
-
3
-
2
-
1
HF
1 = Enabled
0
-
0 = Disabled
UTI - Update Transfer Inhibit
This bit selects the time-of-day and alarm hour format:
7
UTI
1 = 24-hour format
0 = 12-hour format
July 1997
9
6
-
5
-
4
-
3
-
2
-
1
-
0
-
bq3285ED/LD
AIE = 1 and AF = 1
This bit inhibits the transfer of RTC bytes to the user
buffer:
PIE = 1 and PF = 1
1 = Inhibits transfer and clears UIE
UIE = 1 and UF = 1
0 = Allows transfer
Reading register C clears this bit.
Register C
7
INTF
6
PF
Register D
Register C Bits
5
4
3
AF
UF
0
2
-
1
0
0
0
7
VRT
6
0
5
DA5
Register D Bits
4
3
2
DA4 DA3 DA2
1
DA1
0
DA0
Register C is the read-only event status register.
Register D provides for the read-only data integrity
status bit, and the day-of-the-month alarm.
Bits 0, 1, 2, 3 - Unused Bits
Bits 6 - Unused Bit
7
-
6
-
5
-
4
-
3
0
2
-
1
0
0
0
7
-
6
0
5
-
4
-
3
-
2
-
1
-
0
-
3
-
2
-
1
-
0
-
These bits are always set to 0.
This bit is always set to 0.
UF - Update Event Flag
7
-
6
-
5
-
4
UF
3
-
2
-
1
-
VRT - Valid RAM and Time
0
-
7
VRT
6
-
5
-
4
-
This bit is set to a 1 at the end of the update cycle.
Reading register C clears this bit.
1 = Valid backup energy source
AF - Alarm Event Flag
0 = Backup energy source is depleted
7
-
6
-
5
AF
4
-
3
-
2
-
1
-
0
-
When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.
This bit is set to a 1 when an alarm event occurs. Reading register C clears this bit.
DA0–DA5
7
-
PF - Periodic Event Flag
7
-
6
PF
5
-
4
-
3
-
2
-
1
-
0
-
6
-
5
DA5
4
DA4
3
DA3
2
DA2
1
0
DA1 DA0-
These bits store the value for the day-of-the-month
alarm. If DA0–DA5 are set to zero, then the day-of-themonth alarm is disabled . These bits are not affected by
a reset.
This bit is set to a 1 every tPI time, where tPI is the time
period selected by the settings of RS0–RS3 in register A.
Reading register C clears this bit.
INTF - Interrupt Request Flag
7
INTF
6
-
5
-
4
-
3
-
2
-
1
-
0
-
This flag is set to a 1 when any of the following is true:
July 1997
10
bq3285ED/LD
Absolute Maximum Ratings—bq3285ED
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to 7.0
V
VT ≤ VCC + 0.3
TOPR
Operating temperature
0 to +70
°C
Commercial
TSTG
Storage temperature
-55 to +125
°C
TBIAS
Temperature under bias
-40 to +85
°C
TSOLDER
Soldering temperature
260
°C
Note:
For 10 seconds
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Absolute Maximum Ratings—bq3285LD
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to 7.0
V
VT ≤ VCC + 0.3
TOPR
Operating temperature
0 to +70
°C
Commercial
TSTG
Storage temperature
-55 to +125
°C
TBIAS
Temperature under bias
-40 to +85
°C
TSOLDER
Soldering temperature
260
°C
Note:
For 10 seconds
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
July 1997
11
bq3285ED/LD
Recommended DC Operating Conditions—bq3285ED (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VCC
Supply voltage
4.5
5.0
5.5
V
VSS
Supply voltage
0
0
0
V
VIL
Input low voltage
-0.3
-
0.8
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
VBC
Backup cell voltage
2.4
-
4.0
V
Note:
Typical values indicate operation at TA = 25°C.
Recommended DC Operating Conditions—bq3285LD (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VCC
Supply voltage
2.7
3.0
5.5
V
VSS
Supply voltage
0
0
0
V
VIL
Input low voltage
-0.3
-
0.6
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
VBC
Backup cell voltage
2.4
-
4.0
V
Note:
Typical values indicate operation at TA = 25°C.
Crystal Specifications—bq3285ED/LD (DT-26 or Equivalent)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
-
32.768
-
kHz
6
-
pF
25
30
°C
-0.042
ppm/°C
fO
Oscillation frequency
CL
Load capacitance
-
TP
Temperature turnover point
20
k
Parabolic curvature constant
-
-
Q
Quality factor
40,000
70,000
-
R1
Series resistance
-
-
45
KΩ
pF
C0
Shunt capacitance
-
1.1
1.8
C0/C1
Capacitance ratio
-
430
600
DL
Drive level
-
-
1
µW
∆f/fO
Aging (first year at 25°C)
-
1
-
ppm
July 1997
12
bq3285ED/LD
DC Electrical Characteristics—bq3285ED (TA = TOPR, VCC = 5V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions/Notes
ILI
Input leakage current
-
-
±1
µA
VIN = VSS to VCC
ILO
Output leakage current
-
-
±1
µA
AD0–AD7 and INT in
high impedance,
VOUT = VSS to VCC
VOH
Output high voltage
2.4
-
-
V
IOH = -2.0 mA
VOL
Output low voltage
-
-
0.4
V
IOL = 4.0 mA
ICC
Operating supply current
-
7
15
mA
Min. cycle, duty = 100%,
IOH = 0mA, IOL = 0mA
ICCSB
Standby supply current
-
300
-
µA
VIN = VSS or VCC,
CS ≥ VCC - 0.2
VSO
Supply switch-over voltage
-
VBC
-
V
ICCB
Battery operation current
-
0.4
0.55
µA
VPFD
Power-fail-detect voltage
4.0
4.17
4.35
V
IRCL
Input current when RCL = VSS.
-
-
185
µA
Internal 30K pull-up
Input current when MOT = VCC
-
-
-185
µA
Internal 30K pull-down
Input current when MOT = VSS
-
-
0
µA
Internal 30K pull-down
Input current when EXTRAM =
VCC
-
-
-185
µA
Internal 30K pull-down
Input current when EXTRAM =
VSS
-
-
0
µA
Internal 30K pull-down
IMOTH
VBC = 3V, TA = 25°C
IXTRAM
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V or VBC = 3V.
July 1997
13
bq3285ED/LD
DC Electrical Characteristics—bq3285LD (TA = TOPR, VCC = 3V)
Symbol
Parameter
Minimum Typical1 Maximum
Unit
Conditions/Notes
ILI
Input leakage current
-
-
±1
µA
VIN = VSS to VCC
ILO
Output leakage current
-
-
±1
µA
AD0–AD7 and INT in high
impedance,
VOUT = VSS to VCC
VOH
Output high voltage
2.2
-
-
V
IOH = -1.0 mA
VOL
Output low voltage
-
-
0.4
V
IOL = 2.0 mA
ICC
Operating supply current
-
52
9
mA
Min. cycle, duty = 100%,
IOH = 0mA, IOL = 0mA
ICCSB
Standby supply current
-
1003
-
µA
VIN = VSS or VCC,
CS ≥ VCC - 0.2
-
V
VBC > VPFD
Supply switch-over voltage
VPFD
-
VSO
-
VBC
-
V
VBC < VPFD
VBC = 3V, TA = 25°C,
VCC < VBC
ICCB
Battery operation current
-
0.4
0.55
µA
VPFD
Power-fail-detect voltage
2.4
2.53
2.65
V
IRCL
Input current when RCL = VSS.
-
-
120
µA
Internal 30K pull-up
Input current when MOT = VCC
-
-
-120
µA
Internal 30K pull-down
Input current when MOT = VSS
-
-
0
µA
Internal 30K pull-down
Input current when EXTRAM =
VCC
-
-
-120
µA
Internal 30K pull-down
Input current when EXTRAM =
VSS
-
-
0
µA
Internal 30K pull-down
IMOTH
IXTRAM
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 3V.
2. 7mA at VCC = 5V
3. 300µA at VCC = 5V
July 1997
14
bq3285ED/LD
Capacitance—bq3285ED/LD (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions
CI/O
Input/output capacitance
-
-
7
pF
VOUT = 0V
CIN
Input capacitance
-
-
5
pF
VIN = 0V
Note:
This parameter is sampled and not 100% tested. It does not include the X1 or X2 pin.
AC Test Conditions—bq3285ED
Parameter
Test Conditions
Input pulse levels
0 to 3.0 V
Input rise and fall times
5 ns
Input and output timing reference levels
1.5 V (unless otherwise specified)
Output load (including scope and jig)
See Figures 4 and 5
+5V
+5V
960
1.15k
For all outputs
except INT
510
INT
50pF
130pF
Figure 5. Output Load—bq3285ED
Figure 4. Output Load—bq3285ED
July 1997
15
bq3285ED/LD
AC Test Conditions—bq3285LD
Parameter
Test Conditions
0 to 2.3 V, VCC = 3V1
Input pulse levels
Input rise and fall times
5 ns
Input and output timing reference levels
1.2 V (unless otherwise specified)
Output load (including scope and jig)
Note:
See Figures 6 and 7
1. For 5V timing, please refer to bq3285ED.
+3.3V
+3.3V
1238
1.45k
For all outputs
except INT
1164
INT
130pF
50pF
Figure 6. Output Load—bq3285LD
Figure 7. Output Load B—bq3285LD
July 1997
16
bq3285ED/LD
Read/Write Timing—bq3285ED (TA = TOPR, VCC = 5V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tCYC
Cycle time
160
-
-
ns
tDSL
DS low or RD/WR high time
80
-
-
ns
tDSH
DS high or RD/WR low time
55
-
-
ns
tRWH
R/W hold time
0
-
-
ns
tRWS
R/W setup time
10
-
-
ns
tCS
Chip select setup time
5
-
-
ns
tCH
Chip select hold time
0
-
-
ns
tDHR
Read data hold time
0
-
25
ns
tDHW
Write data hold time
0
-
-
ns
tAS
Address setup time
20
-
-
ns
tAH
Address hold time
5
-
-
ns
tDAS
Delay time, DS to AS rise
10
-
-
ns
tASW
Pulse width, AS high
30
-
-
ns
tASD
Delay time, AS to DS rise (RD/WR
fall)
35
-
-
ns
tOD
Output data delay time from DS rise
(RD fall)
-
-
50
ns
tDW
Write data setup time
30
-
-
ns
tBUC
Delay time before update cycle
-
244
-
µs
tPI
Periodic interrupt time interval
-
-
-
-
tUC
Time of update cycle
-
1
-
µs
July 1997
17
Notes
See Table 3
bq3285ED/LD
Read/Write Timing—bq3285LD (TA = TOPR, VCC = 3V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tCYC
Cycle time
270
-
-
ns
tDSL
DS low or RD/WR high time
135
-
-
ns
tDSH
DS high or RD/WR low time
90
-
-
ns
tRWH
R/W hold time
0
-
-
ns
tRWS
R/W setup time
15
-
-
ns
tCS
Chip select setup time
8
-
-
ns
tCH
Chip select hold time
0
-
-
ns
tDHR
Read data hold time
0
-
40
ns
tDHW
Write data hold time
0
-
-
ns
tAS
Address setup time
30
-
-
ns
tAH
Address hold time
15
-
-
ns
tDAS
Delay time, DS to AS rise
15
-
-
ns
tASW
Pulse width, AS high
50
-
-
ns
tASD
Delay time, AS to DS rise (RD/WR fall)
55
-
-
ns
tOD
Output data delay time from DS rise
(RD fall)
-
-
100
ns
tDW
Write data setup time
50
-
-
ns
tBUC
Delay time before update cycle
-
244
-
µs
tPI
Periodic interrupt time interval
-
-
-
-
tUC
Time of update cycle
-
1
-
µs
Notes
See Table 3
July 1997
18
bq3285ED/LD
Motorola Bus Read/Write Timing—bq3285ED/LD
tASW
AS
tDAS
tASD
tCYC
DS
tDSL
tDSH
tRWS
tRWH
R/W
tCS
tCH
CS
tAS
tAH
tDW
tDHW
AD0 -AD7
(WRITE)
tOD
tAS
tAH
tDHR
AD0 -AD7
(READ)
T3285L03.eps
July 1997
19
bq3285ED/LD
Intel Bus Read Timing—bq3285ED/LD
tCYC
AS (ALE)
tASW
tASD
DS (RD)
tDSH
tDSL
R/W (WR)
tOD
tCS
tDAS
tCH
CS
tAS
tAH
tDHR
AD0 -AD7
T3285L04.eps
Intel Bus Write Timing—bq3285ED/LD
tCYC
AS (ALE)
tDAS
tASW
tASD
DS (RD)
tDSL
tDSH
R/W (WR)
tCS
tCH
CS
tAS
tAH
AD0 -AD
tDW
tDHW
T3285L05.eps
July 1997
20
bq3285ED/LD
Power-Down/Power-Up Timing—bq3285ED (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tF
VCC slew from 4.5V to 0V
300
-
-
µs
tR
VCC slew from 0V to 4.5V
100
-
-
µs
tCSR
CS at VIH after power-up
20
-
200
ms
Conditions
Internal write-protection
period after VCC passes VPFD
on power-up.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing—bq3285ED
tF
tR
4.5
VCC
4.5
VPFD
VPFD
VSO
VSO
tCSR
CS
T3285L08.eps
July 1997
21
bq3285ED/LD
Power-Down/Power-Up Timing—bq3285LD (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tF
VCC slew from 2.7V to 0V
300
-
-
µs
tR
VCC slew from 0V to 2.7V
100
-
-
µs
tCSR
CS at VIH after power-up
20
-
200
ms
Conditions
Internal write-protection
period after VCC passes VPFD
on power-up.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing—bq3285LD
tF
tR
2.7
VCC
2.7
VPFD
VPFD
VSO
VSO
tCSR
CS
INT
(Alarm)
T3285L06.eps
July 1997
22
bq3285ED/LD
Interrupt Delay Timing—bq3285ED/LD (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tRSW
Reset pulse width
5
-
-
µs
tIRR
INT release from RST
-
-
2
µs
tIRD
INT release from DS
-
-
2
µs
Interrupt Delay Timing—bq3285ED/LD
RD (Intel)
DS (Mot)
tRSW
RST
INT
tIRD
tIRR
T3285L07.eps
July 1997
23
bq3285ED/LD
24-Pin SSOP (SS)
24-Pin SS (0.150" SSOP)
Inches
Dimension
Max.
Min.
Max.
A
0.061
0.068
1.55
1.73
A1
0.004
0.010
0.10
0.25
B
0.008
0.012
0.20
0.30
C
0.007
0.010
0.18
0.25
D
0.337
0.344
8.56
8.74
E
0.150
0.157
3.81
3.99
e
July 1997
24
Millimeters
Min.
.025 BSC
0.64 BSC
H
0.230
0.244
5.84
6.20
L
0.016
0.035
0.41
0.89
bq3285ED/LD
Ordering Information
bq3285ED/LD
Temperature:
blank = Commercial (0 to +70°C)
Package Option:
SS= 24-pin SSOP (0.150)
Device:
bq3285ED Real-Time Clock with 242
bytes of general storage
or
bq3285LD Real-Time Clock with 242
bytes of general storage
(3V operation)
July 1997
25
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jul-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
BQ3285EDSS
OBSOLETE
SSOP
DB
24
TBD
Call TI
Call TI
BQ3285EDSSTR
OBSOLETE
SSOP
DB
24
TBD
Call TI
Call TI
BQ3285LDSS
ACTIVE
SSOP/
QSOP
DBQ
24
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ3285LDSSTR
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
50
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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Addendum-Page 1
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