ALTERA 5CGXC7

Cyclone V Device Handbook Volume 1: Device Overview
and Datasheet
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
101 Innovation Drive
San Jose, CA 95134
www.altera.com
CV-5V1-1.2
Document last updated for Altera Complete Design Suite version:
Document publication date:
11.1
February 2012
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
ISO
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Chapter 1. Overview for Cyclone V Device Family
Cyclone V Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Cyclone V Family Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Low-Power Serial Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
PMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
PCS Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
PCIe Gen1 and Gen2 Hard IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
FPGA GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Adaptive Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Variable-Precision DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13
Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
Dynamic and Partial Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15
Clock Networks and PLL Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15
Enhanced Configuration and Configuration via Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
SoC FPGA with HPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
Features of the HPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
System Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
HPS–FPGA AXI Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19
HPS SDRAM Controller Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19
FPGA Configuration and Processor Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19
Hardware and Software Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–20
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23
Chapter 2. Device Datasheet for Cyclone V Devices
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Internal Weak Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Transceiver Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Core Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
DSP Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
High-Speed I/O Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
DQS Logic Block and Memory Output Clock Jitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . 2–24
OCT Calibration Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
iv
Contents
Duty Cycle Distortion (DCD) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
Configuration Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
POR Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
JTAG Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
DCLK-to-DATA[] Ratio (r) for FPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
FPP Configuration Timing when DCLK to DATA[] = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
FPP Configuration Timing when DCLK to DATA[] > 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
AS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32
PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33
Remote System Upgrades Circuitry Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35
User Watchdog Internal Oscillator Frequency Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35
I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35
Programmable IOE Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36
Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–37
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–40
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter Revision Dates
The chapters in this document, Cyclone V Device Handbook, were revised on the
following dates. Where chapters or groups of chapters are available separately, part
numbers are listed.
Chapter 1.
Overview for Cyclone V Device Family
Revised:
February 2012
Part Number: CV-51001-1.2
Chapter 2.
Device Datasheet for Cyclone V Devices
Revised:
February 2012
Part Number: CV-51002-1.2
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
vi
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
Chapter Revision Dates
February 2012 Altera Corporation
1. Overview for Cyclone V Device Family
February 2012
CV-51001-1.2
CV-51001-1.2
Cyclone® V devices are designed to simultaneously accommodate the shrinking
power consumption, cost, and time-to-market requirements; and the increasing
bandwidth requirements for high-volume and cost-sensitive applications.
The Cyclone V devices are ideal for small form factor applications that are cost- and
power-sensitive in the wireless, wireline, military, broadcast, industrial, consumer,
and communications industries.
The Cyclone V device family is available in six variants:
■
Cyclone V E—optimized for the lowest system cost and power requirement for a
wide spectrum of general logic and digital signal processing (DSP) applications.
■
Cyclone V GX—optimized for the lowest cost and power requirement for
614-megabits per second (Mbps) to 3.125-gigabits per second (Gbps) transceiver
applications.
■
Cyclone V GT—the FPGA industry’s lowest cost and lowest power requirement
for 5-Gbps transceiver applications.
■
Cyclone V SE—system-on-a-chip (SoC) FPGA with integrated Cyclone V FPGA
and ARM®-based hard processor system (HPS).
■
Cyclone V SX—SoC FPGA with integrated Cyclone V FPGA, ARM-based HPS,
and 3.125-Gbps transceivers.
■
Cyclone V ST—SoC FPGA with integrated Cyclone V FPGA, ARM-based HPS,
and 5-Gbps transceivers.
The Cyclone V SoC FPGA variants feature an FPGA integrated with an HPS that
consists of a dual-core ARM Cortex™-A9 MPCore™ processor, a rich set of peripherals,
and a shared multiport SDRAM controller.
The Cyclone V device family provides the following key advantages:
■
Up to 40% lower power consumption than the previous generation device—built
on TSMC’s 28-nm low power (28LP) process and includes an abundance of hard
intellectual properties (IP).
■
Improved logic integration and differentiation capabilities—features a new
8-input adaptive logic module (ALM), up to 11.6 megabits (Mb) of dedicated
memory, and variable-precision DSP blocks.
■
Increased bandwidth capacity—a combined result of the new 3-Gbps and 5-Gbps
transceivers, and the hard memory controllers.
■
Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard IP, and
an FPGA in a single Cyclone V SoC FPGA—supports over 100 Gbps peak
bandwidth with integrated data coherency between the processor and the FPGA.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012
Subscribe
1–2
Chapter 1: Overview for Cyclone V Device Family
Cyclone V Features Summary
Cyclone V Features Summary
Some of the key features of the Cyclone V devices include:
■
Built-in hard IP blocks
■
Support for all mainstream single-ended and differential I/O standards including
3.3 V at up to 16 mA drive strengths
■
HPS for the Cyclone V SE, SX, and ST variants
■
Comprehensive design protection features to protect your valuable IP investments
■
Lowest system cost advantage—requires only two core voltages to operate, are
available in low-cost wirebond packaging, and includes innovative cost saving
features such as Configuration via Protocol (CvP) and partial reconfiguration
Table 1–1 lists a summary of the Cyclone V features.
Table 1–1. Summary of Features for Cyclone V Devices (Part 1 of 2)
Feature
Technology
Low-power
high-speed serial
interface
FPGA
General-purpose
I/Os (GPIOs)
Details
■
TSMC’s 28-nm low power (28LP) process technology
■
1.1-V core voltage
■
614 Mbps to 5.0 Gbps integrated transceiver speed
■
Transmitter pre-emphasis and receiver equalization
■
Dynamic partial reconfiguration of individual channels
■
875 Mbps LVDS receiver and 840 Mbps LVDS transmitter
■
400 MHz/800 Mbps external memory interface
■
On-chip termination (OCT)
■
3.3-V support with up to 16 mA drive strength
Embedded
transceiver I/O
Hard IP blocks
Variable-precision
DSP
Memory controller
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
PCI Express® (PCIe®) Gen2 (x1 or x2) and Gen1 (x1, x2, or x4) hard IP with
multifunction support, endpoint, and root port
■
Native support for three signal processing precision levels (three 9 x 9s, two
18 x 19s, or one 27 x 27 multiplier) in the same variable-precision DSP block
■
64-bit accumulator and cascade
■
Embedded internal coefficient memory
■
Preadder/subtractor for improved efficiency
DDR3, DDR2, LPDDR, and LPDDR2
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
Cyclone V Features Summary
1–3
Table 1–1. Summary of Features for Cyclone V Devices (Part 2 of 2)
Feature
HPS
(Cyclone V SE, SX,
and ST devices
only)
High-performance
FPGA fabric
Internal memory
blocks
Phase-locked
loops (PLLs)
Clock networks
Configuration
Packaging
February 2012
Details
■
Dual-core ARM Cortex-A9 MPCore processor—up to 800 MHz maximum frequency with support
for symmetric and asymmetric multiprocessing
■
Interface peripherals—10/100/1000 Ethernet media access control (MAC), USB 2.0 On-The-GO
(OTG) controller, serial peripheral interface (SPI), Quad SPI flash controller, NAND flash controller,
SD/MMC/SDIO controller, UART, controller area network (CAN), I2C interface, and up to 71 HPS I/O
interfaces
■
System peripherals—general-purpose and watchdog timers, direct memory access (DMA)
controller, FPGA configuration manager, and clock and reset managers
■
On-chip RAM and boot ROM
■
HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA
bridges that allow the FPGA fabric to master transactions to slaves in the HPS, and vice versa.
■
FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport
front end (MPFE) of the HPS SDRAM controller
■
ARM CoreSight™ JTAG debug access port, trace port, and on-chip trace storage
Enhanced 8-input ALM with four registers
■
M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
■
Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25% of
the ALMs as MLAB memory
■
Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
■
Integer mode and fractional mode
■
550 MHz global clock network
■
Global, quadrant, and peripheral clock networks
■
Clock networks that are not used can be powered down to reduce dynamic power
■
Partial and dynamic reconfiguration of the FPGA
■
CvP
■
Active serial (AS) x1 and x4, fast passive parallel (FPP) x8 and x16, passive serial (PS), and JTAG
options
■
Enhanced advanced encryption standard (AES) design security features
■
Tamper protection
■
Wirebond low-halogen packages
■
Multiple device densities with compatible package footprints for seamless migration between
different device densities
■
RoHS-compliant options
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–4
Chapter 1: Overview for Cyclone V Device Family
Cyclone V Family Plan
Cyclone V Family Plan
Table 1–2 and Table 1–3 list the Cyclone V E, GX, and GT maximum resource counts.
Table 1–2. Maximum Resource Counts for Cyclone V E Devices—Preliminary
Cyclone V E Device
Resource
5CEA2
5CEA4
5CEA5
ALM
9,434
18,113
28,868
56,415
113,585
Logic Element (LE)
25,000
48,000
76,500
149,500
301,000
Block Memory (Kb)
1,700
2,700
3,800
6,500
11,600
MLAB Memory (Kb)
196
270
440
836
1,717
Variable-precision DSP Block
25
72
124
156
342
18 x 19 Multiplier
50
144
248
312
684
Fractional PLL
4
4
6
6
6
GPIO
288
288
272
480
448
LVDS
100
100
100
122
122
1
1
2
2
2
Hard Memory Controller
5CEA7
5CEA9
Table 1–3. Maximum Resource Counts for Cyclone V GX and GT Devices—Preliminary
Cyclone V GX Device
Cyclone V GT Device
Resource
5CGXC3
5CGXC4
5CGXC5
5CGXC7
5CGXC9
5CGTD5
5CGTD7
5CGTD9
ALM
11,698
18,868
28,868
56,415
113,585
28,868
56,415
113,585
LE
31,000
50,000
76,500
149,500
301,000
76,500
149,500
301,000
Block Memory (Kb)
1,400
2,500
3,800
6,500
11,600
3,800
6,500
11,600
MLAB Memory (Kb)
147
295
440
836
1,717
440
836
1,717
Variable-precision DSP Block
42
70
124
156
342
124
156
342
18 x 19 Multiplier
84
140
248
312
684
248
312
684
PLL (1)
4
6
6
7
8
6
7
8
Fractional
3-Gbps Transceiver
3
6
6
9
12
—
—
—
5-Gbps Transceiver
—
—
—
—
—
6
9
12
GPIO
224
368
368
480
560
368
480
560
LVDS
48
90
100
122
122
100
122
122
PCIe Hard IP Block
1
2
2
2
2
2
2
2
Hard Memory Controller
1
2
2
2
2
2
2
2
Note to Table 1–3:
(1) The maximum fractional PLLs listed include general purpose PLLs and transceiver PLLs.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
Cyclone V Family Plan
1–5
Table 1–4 and Table 1–5 list the Cyclone V SE, SX, and ST maximum resource counts.
Table 1–4. Maximum Resource Counts for Cyclone V SE Devices—Preliminary
Cyclone V SE Devices
Resource
5CSEA2
5CSEA4
5CSEA5
5CSEA6
ALM
9,434
15,094
32,075
41,509
LE
25,000
40,000
85,000
110,000
Block Memory (Kb)
1,400
2,240
3,972
5,140
MLAB Memory (Kb)
138
220
480
621
Variable-precision DSP Block
36
58
87
112
18 x 19 Multiplier
72
116
174
224
FPGA Fractional PLL
4
5
6
6
HPS PLL
3
3
3
3
FPGA GPIO
124
124
288
288
HPS I/O
188
188
188
188
LVDS
31
31
72
72
FPGA Memory Controller
—
1
1
1
HPS Memory Controller
1
1
1
1
ARM Cortex-A9 MPCore Processor Single- or dual-core Single- or dual-core Single- or dual-core Single- or dual-core
Table 1–5. Maximum Resource Counts for Cyclone V SX and ST Devices—Preliminary (Part 1 of 2)
Cyclone V SX Device
Cyclone V ST Device
Resource
5CSXC4
5CSXC5
5CSXC6
5CSTD5
5CSTD6
ALM
15,094
32,075
41,509
32,075
41,509
LE
40,000
85,000
110,000
85,000
110,000
Block Memory (Kb)
2,240
3,972
5,140
3,972
5,140
MLAB Memory (Kb)
220
480
621
480
621
Variable-precision DSP Block
58
87
112
87
112
18 x 19 Multiplier
116
174
224
174
224
FPGA Fractional PLL (1)
5
6
6
6
6
HPS PLL
3
3
3
3
3
3-Gbps Transceiver
6
9
9
—
—
5-Gbps Transceiver
—
—
—
9
9
FPGA GPIO
124
288
288
288
288
HPS I/O
188
188
188
188
188
LVDS
31
72
72
72
72
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–6
Chapter 1: Overview for Cyclone V Device Family
Cyclone V Family Plan
Table 1–5. Maximum Resource Counts for Cyclone V SX and ST Devices—Preliminary (Part 2 of 2)
Cyclone V SX Device
Cyclone V ST Device
Resource
5CSXC4
5CSXC5
5CSXC6
5CSTD5
5CSTD6
2
2
2
2
2
PCIe Hard IP Block
FPGA Memory Controller
1
1
1
1
1
HPS Memory Controller
1
1
1
1
1
Dual-core
Dual-core
Dual-core
Dual-core
Dual-core
ARM Cortex-A9 MPCore Processor
Note to Table 1–5:
(1) The maximum FPGA fractional PLLs listed include FPGA general purpose PLLs and transceiver PLLs.
Table 1–6 lists the Cyclone V E, GX, and GT package plan that shows the GPIO count,
the maximum number of transceivers available, and the vertical migration capability
for each device package and density.
Table 1–6. Package Plan for Cyclone V E, GX, and GT Devices—Preliminary (1)
F256
(17 mm)
XCVR
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
F1152
(35 mm)
GPIO
F896
(31 mm)
XCVR
F672
(27 mm)
GPIO
F484
(23 mm)
XCVR
U484
(19 mm)
GPIO
Device
U324
(15 mm)
5CEA2
144
—
176
—
288
—
288
—
—
—
—
—
—
—
5CEA4
144
—
176
—
288
—
288
—
—
—
—
—
—
—
5CEA5
—
—
—
—
272
—
272
—
—
—
—
—
—
—
5CEA7
—
—
—
—
240
—
240
—
336
—
480
—
—
—
5CEA9
—
—
—
—
—
—
224
—
336
—
448
—
—
—
5CGXC3 (2)
—
—
112
3
208
3
208
3
—
—
—
—
—
—
5CGXC4 (2)
—
—
—
—
224
6
240
6
336
6
—
—
—
—
5CGXC5 (2)
—
—
—
—
224
6
240
6
336
6
—
—
—
—
5CGXC7 (2)
—
—
—
—
240
6
240
6
336
9
480
9
—
—
5CGXC9 (2)
—
—
—
—
—
—
224
6
336
9
448
12
560
12
5CGTD5 (3)
—
—
—
—
240
6
240
6
368
6
—
—
—
—
5CGTD7 (3)
—
—
—
—
240
6
240
6
336
9
480
9
—
—
5CGTD9 (3)
—
—
—
—
—
—
224
6
336
9
448
12
560
12
Notes to Table 1–6:
(1) The arrows indicate the package vertical migration capability. You can also migrate your design across device densities in the same packaging
option if the devices have the same dedicated pins, configuration pins, and power pins.
(2) The transceiver counts listed are for 3-Gbps transceivers.
(3) The transceiver counts listed are for 5-Gbps transceivers.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
Cyclone V Family Plan
1–7
Table 1–7 lists the Cyclone V SE, SX, and ST package plan that shows the FPGA GPIO
and HPS I/O counts, the maximum number of transceivers available, and the vertical
migration capability for each device package and density.
Table 1–7. Package Plan for Cyclone V SE, SX, and ST Devices—Preliminary (1)
U484
(19 mm)
Device
5CSEA2
U672
(23 mm)
F896
(31 mm)
GPIO
XCVR
HPS I/O
GPIO
XCVR
HPS I/O
GPIO
XCVR
HPS I/O
66
—
161
124
—
188
—
—
—
5CSEA4
66
—
161
124
—
188
—
—
—
5CSEA5
66
—
161
124
—
188
288
—
188
5CSEA6
66
—
161
124
—
188
288
—
188
5CSXC4 (2)
—
—
—
124
6
188
—
—
—
5CSXC5 (2)
—
—
—
124
6
188
288
9
188
5CSXC6 (2)
—
—
—
124
6
188
288
9
188
5CSTD5 (3)
—
—
—
—
—
—
288
9
188
5CSTD6 (3)
—
—
—
—
—
—
288
9
188
Notes to Table 1–7:
(1) The arrows indicate the package vertical migration capability. You can also migrate your design across device densities in the same packaging
option if the devices have the same dedicated pins, configuration pins, and power pins.
(2) The transceiver counts listed are for 3-Gbps transceivers.
(3) The transceiver counts listed are for 5-Gbps transceivers.
1
To verify the pin migration compatibility, use the Pin Migration View window in the
Quartus II software Pin Planner.
f For more information about the verifying the pin migration compatibility, refer to the
“I/O Management” chapter in the Quartus II Handbook.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–8
Chapter 1: Overview for Cyclone V Device Family
Low-Power Serial Transceivers
Low-Power Serial Transceivers
Cyclone V devices deliver the industry’s lowest power 5-Gbps transceivers at an
estimated 88 mW maximum power consumption per channel. Cyclone V transceivers
are designed to be compliant for a wide range of protocols and data rates. The
transceivers are positioned on the left outer edge of the device, as shown in
Figure 1–1. The transceiver channels consist of the physical medium attachment
(PMA), physical coding sublayer (PCS), and clock networks.
Figure 1–1. Device Chip Overview for Cyclone V GX and GT Devices (1)
I/O, LVDS, and Memory Interface
Hard
PCS
Hard
PCS
Hard
PCS
Clock Networks
Transceiver
PMA
Transceiver
PMA
Transceiver
PMA
Fractional PLL
Fractional PLLs
I/O, LVDS, and Memory Interface
PCIe Hard IP Blocks
Fractional PLLs
Hard PCS Blocks
Transceiver PMA Blocks
Hard Memory Controller
Transceiver
Individual Channels
Distributed Memory
Core Logic Fabric and MLABs
M10K Internal Memory Blocks
Variable-Precision DSP Blocks
Hard Memory Controller
I/O, LVDS, and Memory Interface
Note to Figure 1–1:
(1) This figure represents a Cyclone V device with transceivers. Other Cyclone V devices may have a different floor plan than the one shown here.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
Low-Power Serial Transceivers
1–9
PMA Support
To prevent core and I/O noise from coupling into the transceivers, the PMA block is
isolated from the rest of the chip—ensuring optimal signal integrity. For the
transceivers, you can use the channel PLL of an unused receiver PMA as an additional
transmit PLL.
Table 1–8 lists the PMA features of the transceiver.
Table 1–8. PMA Features of the Transceivers in Cyclone V Devices
Features
Capability
Backplane support
Up to 16” FR4 PCB fabric drive capability at up to 5 Gbps
PLL-based clock recovery
Superior jitter tolerance
Programmable deserialization and word alignment
Flexible deserialization width and configurable word alignment pattern
Equalization and pre-emphasis
Up to 6 dB of pre-emphasis, up to 4 dB of equalization, and no
decision feedback equalizer (DFE)
Ring oscillator transmit PLLs
614 Mbps to 5 Gbps
Input reference clock range
20 MHz to 400 MHz
Transceiver dynamic reconfiguration
Allows the reconfiguration of a single channel without affecting the
operation of other channels
PCS Support
The Cyclone V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, or 40-bit
interface, depending on the transceiver data rate and protocol. Cyclone V devices
contain PCS hard IP to support PCIe Gen1 and Gen2, XAUI, Gbps Ethernet (GbE),
Serial RapidIO® (SRIO), and Common Public Radio Interface (CPRI). Most of the
other standard and proprietary protocols from 614 Mbps to 5.0 Gbps are supported.
Table 1–9 lists the PCS features of the transceiver.
Table 1–9. PCS Features of the Transceivers in Cyclone V Devices (Part 1 of 2)
PCS Support
3-Gbps and 5-Gbps
Basic
PCIe Gen1: x1, x2, x4
PCIe Gen2: x1, x2 (1)
Data Rates (Gbps)
0.614 to 5.0
2.5 and 5.0
GbE
February 2012
1.25
Altera Corporation
Transmitter Datapath
Receiver Datapath
■
Phase compensation FIFO
■
Word aligner
■
Byte serializer
■
Deskew FIFO
■
8B/10B encoder
■
Rate-match FIFO
■
Transmitter bit-slip
■
8B/10B decoder
■
Byte deserializer
■
Byte ordering
■
Receiver phase compensation
FIFO
■
Dedicated PCIe PHY IP core
■
Dedicated PCIe PHY IP core
■
PIPE 2.0 interface to the core logic
■
PIPE 2.0 interface to the core logic
■
Custom PHY IP core with preset
feature
■
Custom PHY IP core with preset
feature
■
GbE transmitter synchronization
state machine
■
GbE receiver synchronization state
machine
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–10
Chapter 1: Overview for Cyclone V Device Family
Low-Power Serial Transceivers
Table 1–9. PCS Features of the Transceivers in Cyclone V Devices (Part 2 of 2)
PCS Support
Data Rates (Gbps)
XAUI
3.125
SRIO 1.3 and 2.1
1.25 to 3.125
SDI, SD/HD, and
3G-SDI
0.27 (2), 1.485, and
2.97
Serial ATA Gen1 and
Gen2
CPRI 4.1 (3)
1.5 and 3.0
0.6144 to 4.9152
OBSAI RP3
0.768 to 3.072
V-by-One HS
DisplayPort 1.2 (4)
HiGig
JESD204A
Transmitter Datapath
■
Dedicated XAUI PHY IP core
■
Dedicated XAUI PHY IP core
■
XAUI synchronization state
machine for bonding four channels
■
XAUI synchronization state
machine for realigning four
channels
■
Custom PHY IP core with preset
feature
■
Custom PHY IP core with preset
feature
■
SRIO version 2.1-compliant x2
and x4 channel bonding
■
SRIO version 2.1-compliant x2
and x4 deskew state machine
■
Custom PHY IP core with preset
feature
■
Custom PHY IP core with preset
feature
■
Custom PHY IP core with preset
feature
■
Custom PHY IP core with preset
feature
■
Electrical idle
■
Signal detect
■
Wider spread of asynchronous
SSC
■
Dedicated deterministic latency
PHY IP core
■
Dedicated deterministic latency
PHY IP core
■
Transmitter (TX) manual bit-slip
mode
■
Receiver (RX) deterministic
latency state machine
■
Dedicated deterministic latency
PHY IP core
■
Dedicated deterministic latency
PHY IP core
■
TX manual bit-slip mode
■
RX deterministic latency state
machine
■
Custom PHY IP core
■
Wider spread of asynchronous
SSC
■
Custom PHY IP core
■
Wider spread of asynchronous
SSC
Up to 3.75
Custom PHY IP core
1.62 and 2.7
Custom PHY IP core
3.75
0.3125 (2) to 3.125
Receiver Datapath
■
Dedicated XAUI PHY IP core
■
Dedicated XAUI PHY IP core
■
XAUI synchronization state
machine for bonding four channels
■
XAUI synchronization state
machine for realigning four
channels
Custom PHY IP core with preset
feature
Custom PHY IP core with preset
feature
Notes to Table 1–9:
(1) PCIe Gen2 is supported only for Cyclone V GT devices.
(2) The 0.27-Gbps and 0.3125-Gbps data rates are supported using oversampling user logic that you must implement in the FPGA fabric.
(3) High-voltage output mode (1000-BASE-CX) is not supported.
(4) Pending characterization.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
PCIe Gen1 and Gen2 Hard IP
1–11
PCIe Gen1 and Gen2 Hard IP
Cyclone V GX, GT, SX, and ST devices contain PCIe hard IP—consisting of the MAC,
data link, and transaction layers—that is designed for performance, ease-of-use, and
increased functionality. The PCIe hard IP supports PCIe Gen2 end point and root port
for x1 and x2 lanes configuration, and Gen1 end point and root port for up to x4 lane
configuration.
The PCIe endpoint support includes multifunction support for up to eight functions,
as shown in Figure 1–2. The integrated multifunction support reduces the FPGA logic
requirements by up to 20 K LEs for PCIe designs that require multiple peripherals.
Figure 1–2. PCIe Multifunction for Cyclone V Devices
External System
Local
Peripheral 2
ATA
USB
Bridge
to PCIe
Local
Peripheral 1
GbE
CAN
PCIe Link
PCIe EP
Root
Complex
PCIe RP
Memory
Controller
SP1
GPIO
Host CPU
12C
Cyclone V Device
The Cyclone V PCIe hard IP operates independently from the core logic. This
independent operation allows the PCIe link to wake up and complete link training in
less than 100 ms while the Cyclone V device completes loading the programming file
for the rest of the device. In addition, the PCIe hard IP in the Cyclone V device
provides improved end-to-end datapath protection using ECC.
FPGA GPIOs
Cyclone V devices offer highly configurable GPIOs. The following list describes the
many features of the GPIOs:
February 2012
■
Programmable bus hold and weak pull-up.
■
LVDS output buffer with programmable differential output voltage (VOD) and
programmable pre-emphasis.
■
Dynamic on-chip parallel termination (RT OCT) for all I/O banks with OCT
calibration to limit the termination impedance variation to ±15%.
■
On-chip dynamic termination that has the ability to swap between serial and
parallel termination, depending on whether there is read or write on a common
bus for signal integrity.
■
Unused voltage reference (VREF) pins that can be configured as user I/Os.
■
Easy timing closure support using the hard read FIFO in the input register path,
and delay-locked loop (DLL) delay chain with fine and coarse architecture.
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–12
Chapter 1: Overview for Cyclone V Device Family
External Memory
External Memory
Cyclone V devices support up to two hard memory controllers for DDR3, DDR2,
LPDDR2, and LPDDR SDRAM devices. Each controller supports 8- to 32-bit
components of up to 4 gigabits (Gb) in density with two chip selects and optional
ECC. Cyclone V devices also support soft memory controllers for DDR3, DDR2,
LPDDR2, and LPDDR SDRAM for maximum flexibility.
Table 1–10 lists the performance of the external memory interface in Cyclone V
devices.
Table 1–10. External Memory Interface Performance in Cyclone V Devices
Interface
Voltage (V)
Hard Controller (MHz)
Soft Controller (MHz)
DDR3 SDRAM
1.5
400
300
DDR3L SDRAM
1.35
400
300
DDR3U SDRAM
1.25
333
300
1.8
400
300
1.5
400
300
LPDDR2 SDRAM
1.2
333
300
LPDDR SDRAM
1.8
200
200
DDR2 SDRAM
Adaptive Logic Module
Cyclone V devices use a 28-nm ALM as the basic building block of the logic fabric.
The ALM, as shown in Figure 1–3, uses an 8-input fracturable look-up table (LUT)
with four dedicated registers to help improve timing closure in register-rich designs
and achieve an even higher design packing capability than previous generations.
You can configure up to 25% of the ALMs in Cyclone V devices as distributed
memory using MLABs. For more information, refer to “Embedded Memory” on
page 1–14.
Figure 1–3. ALM for Cyclone V Devices
Cyclone V Device
Reg
1
2
3
4
5
6
7
8
Full
Adder
Reg
Adaptive
LUT
Reg
Full
Adder
Reg
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
Variable-Precision DSP Block
1–13
Variable-Precision DSP Block
Cyclone V devices feature a variable-precision DSP block that you can configure to
support signal processing with precisions ranging from 9 x 9, 18 x 19, and 27 x 27 bits
natively.
You can configure each DSP block during compilation as independent three 9 x 9, two
18 x 19, or one 27 x 27 multipliers. With a dedicated 64-bit cascade bus, you can
cascade multiple variable-precision DSP blocks to implement even higher precision
DSP functions efficiently.
The variable-precision DSP block also supports these features:
■
A 64-bit accumulator that is the largest in the industry.
■
A hard preadder that is available in both 18- and 27-bit modes.
■
Cascaded output adders for efficient systolic finite impulse response (FIR) filters.
■
Internal coefficient register banks, 8 deep, for each multiplier in 18- or 27-bit mode.
■
Fully independent multiplier operation.
■
A second accumulator feedback register to accommodate complex
multiply-accumulate functions.
■
Efficient support for single- and double-precision floating point arithmetic.
■
The inferability of all modes by the Quartus® II design software.
Table 1–11 lists the relevant DSP block configurations for a few usage examples.
Table 1–11. Variable-Precision DSP Block Configurations for Cyclone V Devices
Usage
Multiplier Size (Bit)
DSP Block Resource
Low precision fixed point for video applications
Three 9 x 9
1 variable-precision DSP block
Medium precision fixed point in FIR filters
Two 18 x 19
1 variable-precision DSP block
FIR filters and general DSP usage
Two 18 x 19 with accumulate
1 variable-precision DSP block
High precision fixed- or floating-point implementations
One 27 x 27 with accumulate
1 variable-precision DSP block
Table 1–12 lists the variable-precision DSP resources by bit precision for each
Cyclone V device.
Table 1–12. Number of Multipliers in Cyclone V Devices (Part 1 of 2)
Variant
Cyclone V E
February 2012
Device
Variableprecision
DSP Block
Independent Input and Output
Multiplications Operator
9x9
Multiplier
18 x 19
Multiplier
27 x 27
Multiplier
18 x 19
Multiplier
Adder Mode
18 x 18
Multiplier
Adder
Summed
with 36-bit
Input
5CEA2
25
75
50
25
25
25
5CEA4
72
216
144
72
72
72
5CEA5
124
372
248
124
124
124
5CEA7
156
468
312
156
156
156
5CEA9
342
1,026
684
342
342
342
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–14
Chapter 1: Overview for Cyclone V Device Family
Embedded Memory
Table 1–12. Number of Multipliers in Cyclone V Devices (Part 2 of 2)
Variant
Cyclone V GX
Cyclone V GT
Cyclone V SE
Cyclone V SX
Cyclone V ST
Variableprecision
DSP Block
Device
Independent Input and Output
Multiplications Operator
9x9
Multiplier
18 x 19
Multiplier
27 x 27
Multiplier
18 x 19
Multiplier
Adder Mode
18 x 18
Multiplier
Adder
Summed
with 36-bit
Input
5CGXC3
42
126
84
42
42
42
5CGXC4
70
210
140
70
70
70
5CGXC5
124
372
248
124
124
124
5CGXC7
156
468
312
156
156
156
5CGXC9
342
1,026
684
342
342
342
5CGTD5
124
372
248
124
124
124
5CGTD7
156
468
312
156
156
156
5CGTD9
342
1,026
684
342
342
342
5CSEA2
36
108
73
36
36
36
5CSEA4
58
174
116
58
58
58
5CSEA5
87
261
173
87
87
87
5CSEA6
112
336
224
112
112
112
5CSXC4
36
108
73
36
36
36
5CSXC5
58
174
116
58
58
58
5CSXC6
87
261
173
87
87
87
5CSTD5
87
261
173
87
87
87
5CSTD6
112
336
224
112
112
112
Embedded Memory
The Cyclone V embedded memory blocks are flexible and designed to provide an
optimal amount of small- and large-sized memory arrays. Cyclone V devices contain
two types of embedded memory blocks:
■
640-bit MLAB blocks—ideal for wide and shallow memory arrays. The MLAB
operates at up to 300 MHz.
■
10-Kb M10K blocks—ideal for larger memory arrays while still providing a large
number of independent ports. The M10K embedded memory operates at up to
380 MHz.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
Dynamic and Partial Reconfiguration
1–15
Table 1–13 lists the supported memory configurations for Cyclone V devices.
Table 1–13. Embedded Memory Block Configurations for Cyclone V Devices
Memory Block
Depth (bits)
Programmable Widths
MLAB
32
x1, x2, x4, x8, x9, x10, x16, x18, or x20
256
x40 or x32
512
x20 or x16
1K
x10 or x8
2K
x5 or x4
4K
x2
8K
x1
M10K
Dynamic and Partial Reconfiguration
The dynamic reconfiguration feature allows you to dynamically change the
transceiver data rates, PMA settings, or protocols of a channel, without affecting data
transfer on adjacent channels. This feature is ideal for applications that require
on-the-fly multiprotocol or multirate support. You can reconfigure the PMA and PCS
blocks with dynamic reconfiguration.
Partial reconfiguration allows you to reconfigure part of the device while other
sections of the device remain operational. This capability is important in systems with
critical uptime requirements because it allows you to make updates or adjust
functionality without disrupting services.
Apart from lowering cost and power consumption, partial reconfiguration increases
the effective logic density of the device because placing device functions that do not
operate simultaneously is not necessary. Instead, you can store these functions in
external memory and load them whenever the functions are required. This capability
reduces the size of the device because it allows multiple applications on a single
device—saving the board space and reducing the power consumption.
Altera simplifies the time-intensive task of partial reconfiguration by building this
capability on top of the proven incremental compile and design flow in the Quartus II
design software. With the Altera® solution, you do not need to know all the intricate
device architecture details to perform a partial reconfiguration.
Partial reconfiguration is supported through the FPP x16 configuration interface. You
can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to
enable simultaneous partial reconfiguration of both the device core and transceivers.
Clock Networks and PLL Clock Sources
The Cyclone V clock network architecture is based on Altera’s proven global,
quadrant, and peripheral clock structure, which is supported by dedicated clock input
pins and fractional PLLs. Cyclone V devices have 16 global clock networks capable of
up to 550 MHz operation. The Quartus II software identifies all unused sections of the
clock network and powers them down, which reduces power consumption.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–16
Chapter 1: Overview for Cyclone V Device Family
Enhanced Configuration and Configuration via Protocol
Cyclone V devices have up to eight PLLs, each with nine output counters that you can
use to reduce PLL usage in two ways:
■
Reduce the number of oscillators that are required on your board by using
fractional PLLs.
■
Reduce the number of clock pins that are used in the device by synthesizing
multiple clock frequencies from a single reference clock source.
Cyclone V devices use a fractional PLL architecture in addition to the historical
integer PLL. If you use the fractional PLL mode, you can use the PLLs for precision
fractional-N frequency synthesis—removing the need for off-chip reference clock
sources in your design. The transceiver fractional PLLs that are not used by the
transceiver I/Os can be used as general purpose fractional PLLs by the FPGA fabric.
Apart from frequency synthesis, on-chip clock deskew, jitter attenuation, counter
reconfiguration, programmable output clock duty cycles, PLL cascading, and
reference clock switchover, the PLLs in the Cyclone V devices also support the
following key features:
■
Programmable bandwidth
■
User-mode reconfiguration of PLLs
■
Low power mode for each fractional PLL
■
Reference clock switchover
■
Dynamic phase shift
■
Direct, source synchronous, ZDB, external feedback, and LVDS compensation
Enhanced Configuration and Configuration via Protocol
Cyclone V devices support 3.3-V programming voltage and several configuration
modes. Table 1–14 lists the configuration modes and features supported by the
Cyclone V devices.
Table 1–14. Configuration Modes and Features for Cyclone V Devices
Mode
AS through the EPCS
and EPCQ serial
configuration device
Data
Width
(Bit)
Maximum
Maximum
Clock
Design
Data Rate Decompression
Security
Rate
(Mbps)
(MHz)
Remote
System
Update
Partial
Reconfiguration
x1, x4
80
—
v
v
v
—
x1
125
125
v
v
—
—
FPP
x8, x16
125
—
v
v
Parallel
flash loader
16-bit only
CvP (PCIe)
x1, x2,
x4 (1)
—
—
—
v
v
v
x1
33
33
—
—
—
PS through CPLD or
external microcontroller
JTAG
Note to Table 1–14:
(1) The number of lanes instead of bit.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
Power Management
1–17
Instead of using an external flash or ROM, you can configure the Cyclone V devices
through PCIe using CvP. The CvP mode offers the fastest configuration rate and
flexibility with the easy-to-use PCIe hard IP block interface. The Cyclone V CvP
implementation conforms to the PCIe 100 ms power-up-to-active time requirement.
Power Management
Leveraging the FPGA architectural features, process technology advancements, and
transceivers that are designed for power efficiency, the Cyclone V devices consume
less power than previous generation Cyclone FPGAs:
■
Total device core power consumption—less by up to 40%.
■
Transceiver channel power consumption—less by up to 50%.
Additionally, Cyclone V devices contain several hard IP blocks that reduce logic
resources and deliver substantial power savings of up to 25% less power than
equivalent soft implementations.
SoC FPGA with HPS
Each SoC FPGA combines an FPGA fabric and an HPS in a single device. This
combination delivers the flexibility of programmable logic with the power and cost
savings of hard IP in these ways:
February 2012
■
Reduces board space, system power, and bill of materials cost by eliminating a
discrete embedded processor
■
Allows you to differentiate the end product in both hardware and software, and to
support virtually any interface standard
■
Extends the product life and revenue through in-field hardware and software
updates
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–18
Chapter 1: Overview for Cyclone V Device Family
SoC FPGA with HPS
Features of the HPS
The HPS consists of a dual-core ARM Cortex-A9 MPCore processor, a rich set of
peripherals, and a shared multiport SDRAM memory controller, as shown in
Figure 1–4.
Figure 1–4. HPS with Dual-Core ARM Cortex-A9 MPCore Processor
Configuration
Lightweight
Controller
FPGA-to-HPS HPS-to-FPGA HPS-to-FPGA
FPGA
Manager
FPGA-to-HPS SDRAM
HPS
ARM Cortex-A9 MPCore
Ethernet
MAC (2x)
USB
OTG (2x)
64 KB
Boot
ROM
NAND Flash
Controller
SD/MMC/SDIO
Controller
FPGA Fabric
Level 3
Interconnect
CPU0
CPU1
(ARM Cortex-A9
(ARM Cortex-A9
with NEON/FPU,
with NEON/FPU,
32 KB Instruction Cache,
32 KB Instruction Cache,
32 KB Data Cache, and
32 KB Data Cache, and
Memory Management Unit) Memory Management Unit)
ACP
DMA
Controller
SCU
Multiport
DDR SDRAM
Controller
with
Optional ECC
L2 Cache (512 KB)
64 KB
On-Chip
RAM
ETR
(Trace)
Debug
Access Port
Low Speed Peripherals
(Timers, GPIOs, UART, SPI, I2C, CAN, Quad SPI Flash Controller, System Manager, Clock Manager, Reset Manager, and Scan Manager)
System Peripherals
Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC/SDIO
controller module has an integrated DMA controller. For modules without an
integrated DMA controller, an additional DMA controller module provides up to
eight channels of high-bandwidth data transfers. The debug access port provides
interfaces to industry standard JTAG debug probes and supports ARM CoreSight
debug and core traces to facilitate software development.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
SoC FPGA with HPS
1–19
HPS–FPGA AXI Bridges
The HPS–FPGA bridges, which support the Advanced Microcontroller Bus
Architecture (AMBA®) Advanced eXtensible Interface (AXI™) specifications, consist
of the following bridges:
■
FPGA-to-HPS AXI bridge—a high-performance bus supporting 32-, 64-, and
128-bit data widths that allows the FPGA fabric to master transactions to the slaves
in the HPS
■
HPS-to-FPGA AXI bridge—a high-performance bus supporting 32-, 64-, and
128-bit data widths that allows the HPS to master transactions to the slaves in the
FPGA fabric.
■
Lightweight HPS-to-FPGA AXI bridge—a lower performance 32-bit width bus
that allows the HPS to master transactions to the slaves in the FPGA fabric.
The HPS–FPGA AXI bridges also allow the FPGA fabric to access the memory shared
by one or both microprocessors, and provide asynchronous clock crossing with the
clock from the FPGA fabric.
HPS SDRAM Controller Subsystem
The HPS SDRAM controller subsystem contains a multiport SDRAM memory
controller and DDR PHY that are shared between the FPGA fabric (through the
FPGA-to-HPS SDRAM interface), the level 2 (L2) cache, and the level 3 (L3) system
interconnect. The FPGA-to-HPS SDRAM interface supports AMBA AXI and Avalon®
Memory-Mapped (Avalon-MM) interface standards, and provides up to four ports
with separate read and write directions.
To maximize memory performance, the SDRAM controller subsystem supports
command and data reordering, deficit round-robin arbitration with aging, and
high-priority bypass features. The SDRAM controller subsytem supports DDR2,
DDR3, LPDDR, or LPDDR2 devices up to 4 Gb in density and runs up to 400 MHz
(800 Mbps data rate).
For easy migration, the FPGA-to-HPS SDRAM interface is compatible with the
interface of the soft SDRAM memory controller IPs and hard SDRAM memory
controllers in the FPGA fabric.
FPGA Configuration and Processor Booting
The FPGA fabric and HPS in the SoC FPGA are powered independently. You can
reduce the clock frequencies or gate the clocks to reduce dynamic power, or shut
down the entire FPGA fabric to reduce total system power.
You can configure the FPGA fabric and boot the HPS independently, in any order,
providing you with more design flexibility:
February 2012
■
You can boot the HPS before you power up and configure the FPGA fabric. After
the system is running, the HPS reconfigures the FPGA fabric at any time under
program control or through the FPGA configuration controller.
■
You can power up both the HPS and the FPGA fabric together, configure the FPGA
fabric first, and then upload the boot code to the HPS from the FPGA fabric.
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–20
Chapter 1: Overview for Cyclone V Device Family
SoC FPGA with HPS
Hardware and Software Development
For hardware development, you can configure the HPS and connect your soft logic in
the FPGA fabric to the HPS interfaces using the Qsys system integration tool in the
Quartus II software.
For software development, the ARM-based SoC FPGA devices inherit the rich
software development ecosystem available for the ARM Cortex-A9 MPCore
processor. The software development process for Altera SoC FPGAs follows the same
steps as those for other SoC devices. Altera also provides support for the Linux and
VxWorks® operating systems.
You can begin device-specific firmware and software development on the Altera
SoC FPGA Virtual Target. The Virtual Target is a fast PC-based functional simulation
of a target development system—a model of a complete development board that runs
on a PC. The Virtual Target enables the development of device-specific production
software that can run unmodified on actual hardware.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
Ordering Information
1–21
Ordering Information
Figure 1–5 and Figure 1–6 show sample ordering codes and list the options available
for Cyclone V E, GX, and GT devices.
Figure 1–5. Ordering Information for Cyclone V E Devices—Preliminary
Package Type
F : FineLine BGA (FBGA)
U : Ultra FineLine BGA (UBGA)
Embedded Hard IPs
B : No hard PCIe or hard
memory controller
F : No hard PCIe and maximum
2 hard memory controllers
5C
Family Signature
5C : Cyclone V
Operating Temperature
C : Commercial temperature (TJ = 0° C to 85° C)
I : Industrial temperature (TJ = -40° C to 100° C)
A : Automotive temperature (TJ = -40° C to 125° C)
E
F
A9
Family Variant
E : Enhanced logic/memory
:
:
:
:
:
31
C
N
7
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
FPGA Fabric Speed Grade
Package Code
FBGA Package Type
17 : 256 pins
23 : 484 pins
27 : 672 pins
31 : 896 pins
UBGA Package Type
15 : 324 pins
19 : 484 pins
Member Code
A2
A4
A5
A7
A9
F
25,000 logic elements
48,000 logic elements
76,500 logic elements
149,500 logic elements
301,000 logic elements
6 (fastest)
7
8
Figure 1–6. Ordering Information for Cyclone V GX and GT Devices—Preliminary
Embedded Hard IPs
B : No hard PCIe or hard
memory controller
F : Maximum 2 hard PCIe and
2 hard memory controllers
Family Signature
5C : Cyclone V
5C
GT
F
D9
E
Family Variant
GX : 3-Gbps transceivers
GT : 5-Gbps transceivers
Member Code
GX Variant
C3 : 31,000 logic elements
C4 : 50,000 logic elements
C5 : 76,500 logic elements
C7 : 149,500 logic elements
C9 : 301,000 logic elements
GT Variant
D5 : 76,500 logic elements
D7 : 149,500 logic elements
D9 : 301,000 logic elements
February 2012
Altera Corporation
Package Type
F : FineLine BGA (FBGA)
U : Ultra FineLine BGA (UBGA)
Transceiver Count
B : 3
C : 6
D : 9
E : 12
5
Operating Temperature
C : Commercial temperature (TJ = 0° C to 85° C)
I : Industrial temperature (TJ = -40° C to 100° C)
A : Automotive temperature (TJ = -40° C to 125° C)
F
35
C
7
N
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
Transceiver Speed Grade
5 : 5 Gbps
6 : 3.125 Gbps
7 : 2.5 Gbps
Package Code
FBGA Package Type
23 : 484 pins
27 : 672 pins
31 : 896 pins
35 : 1,152 pins
UBGA Package Type
15 : 324 pins
19 : 484 pins
FPGA Fabric Speed Grade
6 (fastest)
7
8
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–22
Chapter 1: Overview for Cyclone V Device Family
Ordering Information
Figure 1–7 and Figure 1–8 show sample ordering codes and list the options available
for Cyclone V SE, SX, and ST Devices.
‘
Figure 1–7. Ordering Information for Cyclone V SE Devices—Preliminary
Package Type
F : FineLine BGA (FBGA)
U : Ultra FineLine BGA (UBGA)
Operating Temperature
C : Commercial temperature (TJ = 0° C to 85° C)
I : Industrial temperature (TJ = -40° C to 100° C)
A : Automotive temperature (TJ = -40° C to 125° C)
Embedded Hard IPs
B : No hard PCIe or hard
memory controller
M : No hard PCIe and 1 hard
memory controller
5C
Family Signature
5C : Cyclone V
Processor Cores
1 : Single-core
2 : Dual-core
SE
M
A6
Family Variant
SE : SoC FPGA with enhanced logic/memory
F
31
C
6
2
Optional Suffix
Indicates specific device
options or shipment method
N : Lead-free packaging
ES : Engineering sample
Package Code
FBGA Package Type
31 : 896 pins
UBGA Package Type
19 : 484 pins
23 : 672 pins
Member Code
A2 : 25,000 logic elements
A4 : 40,000 logic elements
A5 : 85,000 logic elements
A6 : 110,000 logic elements
N
FPGA Fabric Speed Grade
6 (fastest)
7
8
Figure 1–8. Ordering Information for Cyclone V SX and ST Devices—Preliminary
Package Type
F : FineLine BGA (FBGA)
U : Ultra FineLine BGA (UBGA)
Embedded Hard IPs
M : No hard PCIe and 1 hard
memory controller
F : Maximum 2 hard PCIe
controllers and 1 hard
memory controller
Family Signature
5C : Cyclone V
5C
ST
Operating Temperature
C : Commercial temperature (TJ = 0° C to 85° C)
I : Industrial temperature (TJ = -40° C to 100° C)
A : Automotive temperature (TJ = -40° C to 125° C)
Transceiver Count
C : 6
D : 9
F
D6
D
4
Processor Cores
2 : Dual-core
F
31
C
6
2
N
Optional Suffix
Indicates specific device
options or shipment method
Family Variant
SX : SoC FPGA with 3-Gbps transceivers
ST : SoC FPGA with 5-Gbps transceivers
Member Code
SX Variant
C4 : 40,000 logic elements
C5 : 85,000 logic elements
C6 : 110,000 logic elements
ST Variant
D5 : 85,000 logic elements
D6 : 110,000 logic elements
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
Transceiver Speed Grade
4 : 5 Gbps
6 : 3.125 Gbps
Package Code
FBGA Package Type
31 : 896 pins
UBGA Package Type
23 : 672 pins
N : Lead-free packaging
ES : Engineering sample
FPGA Fabric Speed Grade
6 (fastest)
7
8
February 2012 Altera Corporation
Chapter 1: Overview for Cyclone V Device Family
Document Revision History
1–23
Document Revision History
Table 1–15 lists the revision history for this document.
Table 1–15. Document Revision History
Date
Version
February 2012
1.2
Changes
■
Updated Table 1–2, Table 1–3, and Table 1–6.
■
Updated “Cyclone V Family Plan” on page 1–4 and “Clock Networks and PLL Clock
Sources” on page 1–15.
■
Updated Figure 1–1 and Figure 1–6.
■
Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and Table 1–6.
■
Updated Figure 1–4, Figure 1–5, Figure 1–6, Figure 1–7, and Figure 1–8.
November 2011
1.1
■
Updated “System Peripherals” on page 1–18, “HPS–FPGA AXI Bridges” on page 1–19,
“HPS SDRAM Controller Subsystem” on page 1–19, “FPGA Configuration and Processor
Booting” on page 1–19, and “Hardware and Software Development” on page 1–20.
■
Minor text edits.
October 2011
1.0
Initial release.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
1–24
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
Chapter 1: Overview for Cyclone V Device Family
Document Revision History
February 2012 Altera Corporation
2. Device Datasheet for Cyclone V
Devices
February 2012
CV-51002-1.2
CV-51002-1.2
This chapter describes the electrical characteristics, switching characteristics, and
configuration specifications for Cyclone® V devices. Electrical characteristics include
operating conditions and power consumption. Switching characteristics list the
transceiver specifications, and core and periphery performance. Configuration
specifications cover power-on reset (POR) specifications, various configuration mode
timing parameters, remote system upgrades timing, and user watchdog internal
oscillator frequency specification. This chapter also describes I/O timing, including
programmable I/O element (IOE) delay and programmable output buffer delay.
f For more information about the densities and packages of devices in the Cyclone V
family, refer to the Overview for Cyclone V Device Family chapter.
Electrical Characteristics
The following sections describe the electrical characteristics of Cyclone V devices.
Operating Conditions
Cyclone V devices are rated according to a set of defined parameters. To maintain the
highest possible performance and reliability of the Cyclone V devices, you must
consider the operating requirements described in this chapter.
Cyclone V devices are offered in commercial and industrial grades. Commercial
devices are offered in –6 (fastest), –7, and –8 speed grades. Industrial and automotive
devices are offered in the –7 speed grade.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Cyclone V
devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied for these conditions.
c Conditions other than those listed in Table 2–1 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012
Subscribe
2–2
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
Table 2–1 lists the Cyclone V absolute maximum ratings.
Table 2–1. Absolute Maximum Ratings for Cyclone V Devices—Preliminary
Symbol
Description
Minimum
Maximum
Unit
VCC
Core voltage and periphery circuitry power supply
–0.5
1.35
V
VCCPGM
Configuration pins power supply
–0.5
3.75
V
VCC_AUX
Auxiliary supply
–0.5
3.75
V
VCCBAT
Battery back-up power supply for design security volatile key register
–0.5
3.75
V
VCCPD
I/O pre-driver power supply
–0.5
3.75
V
VCCIO
I/O power supply
–0.5
3.9
V
VCCA_FPLL
PLL analog power supply
–0.5
3.75
V
VCCH_GXB
Transceiver high voltage power
–0.5
3.75
V
VCCE_GXB
Transceiver power
–0.5
1.21
V
VCCL_GXB
Clock network power
–0.5
1.21
V
VI
DC input voltage
–0.5
4
V
IOUT
DC output current per pin
–25
40
mA
TJ
Operating junction temperature
–55
125
°C
TSTG
Storage temperature (No bias)
–65
150
°C
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in Table 2–2 and
undershoot to -2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
Table 2–2 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime. The maximum allowed
overshoot duration is specified as a percentage of high time over the lifetime of the
device. A DC signal is equivalent to 100% duty cycle. For example, a signal that
overshoots to 3.95 V can only be at 3.95 V for ~5% over the lifetime of the device; for a
device lifetime of 10 years, this amounts to half a year.
Table 2–2. Maximum Allowed Overshoot During Transitions for Cyclone V Devices—Preliminary
Symbol
Vi (AC)
Description
AC input voltage
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
Condition (V)
Overshoot Duration as % of High Time
Unit
3.7
100
%
3.75
59.79
%
3.8
33.08
%
3.85
18.45
%
3.9
10.36
%
3.95
5.87
%
4
3.34
%
4.05
1.92
%
4.1
1.11
%
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
2–3
Recommended Operating Conditions
Recommended operating conditions are the functional operation limits for the AC
and DC parameters for Cyclone V devices.
Table 2–3 lists the steady-state voltage values expected from Cyclone V devices.
Power supply ramps must all be strictly monotonic, without plateaus.
Table 2–3. Recommended Operating Conditions for Cyclone V Devices—Preliminary
Symbol
Condition
Minimum
Typical
Maximum
Unit
VCC
Core voltage, periphery circuitry power
supply, transceiver physical coding
sublayer (PCS) power supply, and
transceiver PCI Express® (PCIe®) hard IP
digital power supply
—
1.07
1.1
1.13
V
VCC_AUX
Auxiliary supply
—
2.375
2.5
2.625
V
I/O pre-driver (3.3 V) power supply
—
3.135
3.3
3.465
V
I/O pre-driver (3.0 V) power supply
—
2.85
3.0
3.15
V
I/O pre-driver (2.5 V) power supply
—
2.375
2.5
2.625
V
I/O buffers (3.3 V) power supply
—
3.135
3.3
3.465
V
I/O buffers (3.0 V) power supply
—
2.85
3.0
3.15
V
I/O buffers (2.5 V) power supply
—
2.375
2.5
2.625
V
I/O buffers (1.8 V) power supply
—
1.71
1.8
1.89
V
I/O buffers (1.5 V) power supply
—
1.425
1.5
1.575
V
I/O buffers (1.35 V) power supply
—
1.283
1.35
1.418
V
I/O buffers (1.25 V) power supply
—
1.19
1.25
1.31
V
I/O buffers (1.2 V) power supply
—
1.14
1.2
1.26
V
Configuration pins (3.3 V) power supply
—
3.135
3.3
3.465
V
Configuration pins (3.0 V) power supply
—
2.85
3.0
3.15
V
Configuration pins (2.5 V) power supply
—
2.375
2.5
2.625
V
Configuration pins (1.8 V) power supply
—
1.71
1.8
1.89
V
PLL analog voltage regulator power supply
—
2.375
2.5
2.625
V
Battery back-up power supply
(For design security volatile key register)
—
1.2
—
3.0
V
VI
DC input voltage
—
–0.5
—
3.6
V
VO
Output voltage
—
0
—
VCCIO
V
Commercial
0
—
85
°C
Industrial
–40
—
100
°C
Automotive
–40
—
125
°C
VCCPD
VCCIO
VCCPGM
VCCA_FPLL
VCCBAT
(1)
(2)
TJ
February 2012
Description
Operating junction temperature
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–4
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
Table 2–3. Recommended Operating Conditions for Cyclone V Devices—Preliminary
Symbol
tRAMP
Description
Power supply ramp time
Condition
Minimum
Typical
Maximum
Unit
Standard POR
(PORSEL=0)
200 µs
—
100 ms
—
Fast POR
(PORSEL=1)
200 µs
—
4 ms
—
Notes to Table 2–3:
(1) PLL digital voltage is regulated from VCCA_FPLL.
(2) If you do not use the design security feature in Cyclone V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. The power-on reset
(POR) circuitry monitors VCCBAT. Cyclone V devices do not exit POR if VCCBAT stays low.
Table 2–4 lists the transceiver power supply recommended operating conditions for
Cyclone V GX devices.
Table 2–4. Transceiver Power Supply Operating Conditions for Cyclone V GX Devices—Preliminary
Symbol
Minimum
Typical
Maximum
Unit
Transceiver high voltage power (left side)
2.375
2.5
2.625
V
VCCE_GXBL
Transmitter and receiver power (left side)
1.07
1.1
1.13
V
VCCL_GXBL
Clock network power (left side)
1.07
1.1
1.13
V
VCCH_GXBL
Description
Table 2–5 lists the steady-state voltage values expected from Cyclone V
system-on-a-chip (SoC) FPGA with ARM®-based hard processor system (HPS). Power
supply ramps must all be strictly monotonic, without plateaus.
Table 2–5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices—Preliminary
Symbol
VCC_HPS
VCCPD_HPS
VCCIO_HPS
VCCRSTCLK_HPS
VCCPLL_HPS
Description
Minimum
Typical
Maximum
Unit
HPS core voltage and periphery circuitry power
supply
1.07
1.1
1.13
V
HPS I/O pre-driver (3.3 V) power supply
3.135
3.3
3.465
V
HPS I/O pre-driver (3.0 V) power supply
2.85
3.0
3.15
V
HPS I/O pre-driver (2.5 V) power supply
2.375
2.5
2.625
V
HPS I/O buffers (3.3 V) power supply
3.135
3.3
3.465
V
HPS I/O buffers (3.0 V) power supply
2.85
3.0
3.15
V
HPS I/O buffers (2.5 V) power supply
2.375
2.5
2.625
V
HPS I/O buffers (1.8 V) power supply
1.71
1.8
1.89
V
HPS I/O buffers (1.5 V) power supply
1.425
1.5
1.575
V
HPS I/O buffers (1.2 V) power supply
1.14
1.2
1.26
V
HPS reset and clock input pins (3.3 V) power supply
3.135
3.3
3.465
V
HPS reset and clock input pins (3.0 V) power supply
2.85
3.0
3.15
V
HPS reset and clock input pins (2.5 V) power supply
2.375
2.5
2.625
V
HPS reset and clock input pins (1.8 V) power supply
1.71
1.8
1.89
V
HPS PLL analog voltage regulator power supply
2.375
2.5
2.625
V
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
2–5
DC Characteristics
This section lists the supply current, I/O pin leakage current, input pin capacitance,
on-chip termination tolerance, and hot socketing specifications.
Supply Current
Standby current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to estimate supply
current for your design because these currents vary greatly with the resources you
use.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
I/O Pin Leakage Current
Table 2–6 lists the Cyclone V I/O pin leakage current specifications.
Table 2–6. I/O Pin Leakage Current for Cyclone V Devices—Preliminary
Symbol
Description
Conditions
Min
Typ
Max
Unit
II
Input pin
VI = 0 V to VCCIOMAX
–30
—
30
µA
IOZ
Tri-stated I/O pin
VO = 0 V to VCCIOMAX
–30
—
30
µA
Bus Hold Specifications
Table 2–7 lists the Cyclone V device bus hold specifications.
Table 2–7. Bus Hold Parameters for Cyclone V Devices—Preliminary (Part 1 of 2) (1)
VCCIO (V)
Parameter Symbol Conditions
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
8
—
12
—
30
—
50
—
70
—
70
—
µA
–8
—
–12
—
–30
—
–50
—
–70
—
–70
—
µA
Bus-hold,
low,
sustaining
current
ISUSL
Bus-hold,
high,
sustaining
current
ISUSH
Bus-hold,
low,
overdrive
current
IODL
0V < VIN <
VCCIO
—
125
—
175
—
200
—
300
—
500
—
500
µA
Bus-hold,
high,
overdrive
current
IODH
0V < VIN <
VCCIO
—
–125
—
–175
—
–200
—
–300
—
–500
—
–500
µA
February 2012
VIN > VIL
(max.)
VIN < VIH
(min.)
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–6
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
Table 2–7. Bus Hold Parameters for Cyclone V Devices—Preliminary (Part 2 of 2) (1)
VCCIO (V)
Parameter Symbol Conditions
Bus-hold
trip point
VTRIP
—
1.2
1.5
Min
Max
0.3
0.9
Min
1.8
Max
2.5
3.0
3.3
Unit
Min
Max
Min
Max
Min
Max
Min
Max
0.375 1.125 0.68
1.07
0.7
1.7
0.8
2
0.8
2
Note to Table 2–7:
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power up for
I/O pins connected to the calibration block. Calibration accuracy for the calibrated
on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are
applicable at the moment of calibration. When process, voltage, and temperature
(PVT) conditions change after calibration, the tolerance may change.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
V
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
2–7
Table 2–8 lists the Cyclone V OCT termination calibration accuracy specifications.
Table 2–8. OCT Calibration Accuracy Specifications for Cyclone V Devices—Preliminary (1)
Calibration Accuracy
Symbol
Description
Conditions (V)
25-Ω RS
Internal series termination
with calibration
(25-Ω setting)
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
±15
±15
±15
%
50-Ω RS
Internal series termination
with calibration
(50-Ω setting)
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
±15
±15
±15
%
34-Ω and 40-Ω RS
Internal series termination
with calibration
(34-Ω and 40-Ω setting)
VCCIO = 1.5, 1.35,
1.25, 1.2
±15
±15
±15
%
48-Ω, 60-Ω, and
80-Ω RS
Internal series termination
with calibration
(48-Ω, 60-Ω, and 80-Ω
setting)
VCCIO = 1.2
±15
±15
±15
%
50-Ω RT
Internal parallel
termination with calibration
(50-Ω setting)
VCCIO = 2.5, 1.8,
1.5, 1.2
-10 to +40
-10 to +40
-10 to +40
%
20-Ω, 30-Ω,
40-Ω, 60-Ω, and
120-Ω RT
Internal parallel
termination with calibration
(20-Ω, 30-Ω, 40-Ω,
60-Ω, and 120-Ω setting)
VCCIO = 1.5, 1.35,
1.25
-10 to +40
-10 to +40
-10 to +40
%
VCCIO = 1.2
-10 to +40
-10 to +40
-10 to +40
%
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2
±15
±15
±15
%
Internal parallel
60-Ω and 120-Ω RT termination with calibration
(60-Ω and 120-Ω setting)
25-Ω RS_left_shift
Internal left shift series
termination with calibration
(25-Ω RS_left_shift setting)
Unit
C6
C7, I7
C8, A7
Speed Grade Speed Grade Speed Grade
Note to Table 2–8:
(1) OCT calibration accuracy is valid at the time of calibration only.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–8
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
Table 2–9 lists the Cyclone V OCT without calibration resistance tolerance to PVT
changes.
Table 2–9. OCT Without Calibration Resistance Tolerance Specifications for Cyclone V Devices—Preliminary
Resistance Tolerance
Symbol
Description
Conditions (V)
Unit
C6
C7, I7
C8, A7
Speed Grade Speed Grade Speed Grade
25-Ω RS
Internal series termination
without calibration
(25-Ω setting)
VCCIO = 3.0 and 2.5
±30
±40
±40
%
25-Ω RS
Internal series termination
without calibration
(25-Ω setting)
VCCIO = 1.8 and 1.5
±30
±40
±40
%
25-Ω RS
Internal series termination
without calibration
(25-Ω setting)
VCCIO = 1.2
±35
±50
±50
%
50-Ω RS
Internal series termination
without calibration (50-Ω
setting)
VCCIO = 3.0 and 2.5
±30
±40
±40
%
50-Ω RS
Internal series termination
without calibration
(50-Ω setting)
VCCIO = 1.8 and 1.5
±30
±40
±40
%
50-Ω RS
Internal series termination
without calibration
(50-Ω setting)
VCCIO = 1.2
±35
±50
±50
%
100-Ω RD
Internal differential
termination (100-Ω
setting)
VCCIO = 2.5
±25
TBD
TBD
%
OCT calibration is automatically performed at power up for the OCT-enabled I/O
pins. Table 2–10 lists OCT variation with temperature and voltage after power-up
calibration. Use Table 2–10 to determine the OCT variation after power-up calibration
and Equation 2–1 to determine the OCT variation without recalibration.
Equation 2–1. OCT Variation Without Recalibration—Preliminary (1),
(2), (3), (4), (5), (6)
dR
dR
R OCT = R SCAL  1 +  ------- × ΔT ±  ------- × ΔV 


dT
dV
Notes to Equation 2–1:
(1) The ROCT value calculated from Equation 2–1 shows the range of OCT resistance with the variation of temperature
and VCCIO.
(2) RSCAL is the OCT resistance value at power-up.
(3) ΔT is the variation of temperature with respect to the temperature at power up.
(4) ΔV is the variation of voltage with respect to VCCIO at power up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
2–9
Table 2–10 lists the OCT variation after the power-up calibration.
Table 2–10. OCT Variation after Power-Up Calibration for Cyclone V Devices—Preliminary (1)
Symbol
Description
VCCIO (V)
Typical
3.0
0.0297
2.5
0.0344
1.8
0.0499
1.5
0.0744
1.2
0.1241
3.0
0.189
2.5
0.208
1.8
0.266
1.5
0.273
1.2
0.317
OCT variation with voltage without
recalibration
dR/dV
OCT variation with temperature
without recalibration
dR/dT
Unit
%/mV
%/°C
Note to Table 2–10:
(1) Valid for a VCCIO range of ±5% and a temperature range of 0° to 85°C.
Pin Capacitance
Table 2–11 lists the Cyclone V device family pin capacitance.
Table 2–11. Pin Capacitance for Cyclone V Devices
Symbol
Description
Value
Unit
CIOTB
Input capacitance on top and bottom I/O pins
5.5
pF
CIOLR
Input capacitance on left and right I/O pins
5.5
pF
COUTFB
Input capacitance on dual-purpose clock output and feedback pins
5.5
pF
Hot Socketing
Table 2–12 lists the hot socketing specifications for Cyclone V devices.
Table 2–12. Hot Socketing Specifications for Cyclone V Devices—Preliminary
Symbol
Description
Maximum
IIOPIN (DC)
DC current per I/O pin
300 μA
IIOPIN (AC)
AC current per I/O pin
8 mA
IXCVR-TX (DC)
DC current per transceiver transmitter (TX) pin
100 mA
IXCVR-RX (DC)
DC current per transceiver receiver (RX) pin
50 mA
(1)
Note to Table 2–12:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–10
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
Internal Weak Pull-Up Resistor
Table 2–13 lists the weak pull-up resistor values for Cyclone V devices.
Table 2–13. Internal Weak Pull-Up Resistor Values for Cyclone V Devices—Preliminary
Symbol
RPU
Description
Value of the I/O pin pull-up resistor before and during
configuration, as well as user mode if you have enabled the
programmable pull-up resistor option.
(1), (2)
Conditions (V) (3)
Typ (4)
Unit
VCCIO = 3.3 ±5%
25
kΩ
VCCIO = 3.0 ±5%
25
kΩ
VCCIO = 2.5 ±5%
25
kΩ
VCCIO = 1.8 ±5%
25
kΩ
VCCIO = 1.5 ±5%
25
kΩ
VCCIO = 1.35 ±5%
25
kΩ
VCCIO = 1.25 ±5%
25
kΩ
VCCIO = 1.2 ±5%
25
kΩ
Notes to Table 2–13:
(1) All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins.
(2) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is
approximately 25 kΩ.
(3) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(4) These specifications are valid with ±10% tolerances to cover changes over PVT.
I/O Standard Specifications
Table 2–14 through Table 2–19 list the input voltage (VIH and VIL), output voltage
(VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O
standards supported by Cyclone V devices. These tables also list the Cyclone V device
family I/O standard specifications. The VOL and VOH values are valid at the
corresponding IOH and IOL, respectively.
For an explanation of terms used in Table 2–14 through Table 2–19, refer to “Glossary”
on page 2–37.
Table 2–14. Single-Ended I/O Standards for Cyclone V Devices—Preliminary (Part 1 of 2)
I/O
Standard
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
IOH
IOL
(mA) (mA)
Min
Typ
Max
Min
Max
Min
Max
Max
Min
3.3-V
LVTTL
3.135
3.3
3.465 –0.3
0.8
1.7
3.6
0.45
2.4
4
–4
3.3-V
LVCMOS
3.135
3.3
3.465 –0.3
0.8
1.7
3.6
0.2
VCCIO – 0.2
2
–2
3.0-V
LVTTL
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.4
2.4
2
–2
3.0-V
LVCMOS
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.2
VCCIO – 0.2
0.1
–0.1
3.0-V PCI
2.85
3
3.15
—
0.3 x VCCIO
0.5 x VCCIO
VCCIO + 0.3
0.1 x VCCIO
0.9 x VCCIO
1.5
–0.5
3.0-V PCI-X
2.85
3
3.15
—
0.35 x VCCIO
0.5 x VCCIO
VCCIO + 0.3
0.1 x VCCIO
0.9 x VCCIO
1.5
–0.5
2.5 V
2.375
2.5
2.625 –0.3
0.7
1.7
1.8 V
1.71
1.8
1.89
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
–0.3 0.35 x VCCIO 0.65 x VCCIO
3.6
0.4
2
1
–1
VCCIO + 0.3
0.45
VCCIO – 0.45
2
–2
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
2–11
Table 2–14. Single-Ended I/O Standards for Cyclone V Devices—Preliminary (Part 2 of 2)
I/O
Standard
VCCIO (V)
VIL (V)
Min
VIH (V)
Max
Min
VOH (V)
Max
Min
IOH
IOL
(mA) (mA)
Min
Typ
Max
1.5 V
1.425
1.5
1.575 –0.3 0.35 x VCCIO 0.65 x VCCIO
VCCIO + 0.3
0.25 x VCCIO 0.75 x VCCIO
2
–2
1.2 V
1.14
1.2
1.26
VCCIO + 0.3
0.25 x VCCIO 0.75 x VCCIO
2
–2
–0.3 0.35 x VCCIO
Max
VOL (V)
0.65 x VCCIO
Table 2–15. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Cyclone V Devices—Preliminary
I/O
Standard
VCCIO(V)
VREF(V)
VTT(V)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SSTL-2
Class I, II
2.375
2.5
2.625
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
VREF – 0.04
VREF
VREF + 0.04
SSTL-18
Class I, II
1.71
1.8
1.89
0.833
0.9
0.969
VREF – 0.04
VREF
VREF + 0.04
SSTL-15
Class I, II
1.425
1.5
1.575
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
SSTL 135
Class I, II
1.283
1.35
1.418
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
SSTL 125
Class I, II
1.19
1.25
1.26
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
HSTL-18
Class I, II
1.71
1.8
1.89
0.85
0.9
0.95
—
VCCIO/2
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.68
0.75
0.9
—
VCCIO/2
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.47 x VCCIO
0.5 x VCCIO
0.53 x VCCIO
—
VCCIO/2
—
HSUL-12
1.14
1.2
1.3
0.49 x VCCIO
0.5 x VCCIO
0.51 x VCCIO
—
—
—
Table 2–16. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Cyclone V Devices—Preliminary (Part
1 of 2)
I/O
Standard
VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
Ioh
(mA)
Min
Max
Min
Max
Max
Min
Max
Min
Iol
(mA)
SSTL-2
Class I
–0.3
VREF – 0.15
VREF + 0.15
VCCIO + 0.3
VREF – 0.31
VREF + 0.31
VTT – 0.608
VTT + 0.608
8.1
–8.1
SSTL-2
Class II
–0.3
VREF – 0.15
VREF + 0.15
VCCIO + 0.3
VREF – 0.31
VREF + 0.31
VTT – 0.81
VTT + 0.81
16.2
–16.2
SSTL-18
Class I
–0.3
VREF –
0.125
VREF + 0.125
VCCIO + 0.3
VREF – 0.25
VREF + 0.25
VTT – 0.603
VTT + 0.603
6.7
–6.7
SSTL-18
Class II
–0.3
VREF –
0.125
VREF + 0.125
VCCIO + 0.3
VREF – 0.25
VREF + 0.25
0.28
VCCIO – 0.28
13.4
–13.4
SSTL-15
Class I
—
VREF – 0.1
VREF + 0.1
—
VREF –
0.175
VREF + 0.175
0.2 x VCCIO
0.8 x VCCIO
8
–8
SSTL-15
Class II
—
VREF – 0.1
VREF + 0.1
—
VREF –
0.175
VREF + 0.175
0.2 x VCCIO
0.8 x VCCIO
16
–16
SSTL 135
—
VREF – 0.09
VREF + 0.09
—
VREF – 0.16
VREF + 0.16
TBD (1)
TBD (1)
February 2012
Altera Corporation
TBD (1) TBD (1)
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–12
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
Table 2–16. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Cyclone V Devices—Preliminary (Part
2 of 2)
VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
Max
Max
Min
Max
Min
VREF + 0.85
—
VREF – 0.15
VREF + 0.15
TBD (1)
TBD (1)
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
8
–8
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
16
–16
HSTL-15
Class I
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
8
–8
HSTL-15
Class II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
16
–16
HSTL-12
Class I
–0.1
5
VREF – 0.08
VREF + 0.08 VCCIO + 0.15
VREF – 0.15
VREF + 0.15
0.25 x VCCIO 0.75 x VCCIO
8
–8
HSTL-12
Class II
–0.1
5
VREF – 0.08
VREF + 0.08 VCCIO + 0.15
VREF – 0.15
VREF + 0.15
0.25 x VCCIO 0.75 x VCCIO
16
–16
HSUL-12
—
VREF – 0.13
VREF + 0.13
VREF – 0.22
VREF + 0.22
0.1 x VCCIO
TBD
TBD
(1)
(1)
I/O
Standard
Min
Max
Min
SSTL 125
—
VREF – 0.85
HSTL-18
Class I
—
HSTL-18
Class II
—
0.9 x VCCIO
Iol
(mA)
TBD (1) TBD (1)
Note to Table 2–16:
(1) Pending silicon characterization.
Table 2–17. Differential SSTL I/O Standards for Cyclone V Devices—Preliminary
I/O
Standard
VCCIO (V)
VSWING(DC) (V)
Min
Typ
Max
Min
SSTL-2
Class I, II
2.375
2.5
2.625
0.3
SSTL-18
Class I, II
1.71
1.8
1.89
0.25
SSTL-15
Class I, II
1.425
1.5
1.575
SSTL 135
1.283 1.35
1.45
SSTL 125
1.19
1.31
1.25
VOX(AC) (V)
Max
Min
Max
Min
Typ
Max
VCCIO + VCCIO/2
0.6
– 0.2
—
VCCIO/2
+ 0.2
0.62
VCCIO
+ 0.6
VCCIO/2
– 0.15
—
VCCIO/2
+ 0.15
VCCIO +
0.6
VCCIO/2
–
0.175
—
VCCIO/2
+ 0.175
0.5
VCCIO
+ 0.6
VCCIO/2
–
0.125
—
VCCIO/2
+
0.125
0.2
–0.2
-0.15
—
0.15
–0.35
0.35
—
VCCIO/2
—
0.2
–0.2
VREF –
0.135
VCCIO/2
VREF +
0.135
TBD
TBD
(1)
(1)
VREF
– 0.15
—
VREF
+ 0.15
TBD
TBD
TBD
TBD
TBD
(1)
(1)
(1)
(1)
(1)
(1)
—
Min
VSWING(AC) (V)
Typ
TBD
Max
VX(AC) (V)
TBD
(1)
VCCIO/2
—
Note to Table 2–17:
(1) Pending silicon characterization.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
Ioh
(mA)
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Electrical Characteristics
2–13
Table 2–18. Differential HSTL I/O Standards for Cyclone V Devices—Preliminary
VCCIO (V)
I/O
Standard
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
HSTL-18
Class I, II
1.71
1.8
1.89
0.2
—
0.78
—
1.12
0.78
—
1.12
0.4
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.2
—
0.68
—
0.9
0.68
—
0.9
0.4
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.16
VCCIO
+ 0.3
—
0.5 x
VCCIO
—
0.4 x V
0.5 x
VCCIO
0.6 x
VCCIO
0.3
VCCIO
+ 0.48
HSUL-12
1.14
0.26
0.5 x VCCIO
– 0.12
0.5 x
VCCIO
0.5 x
VCCIO
+0.12
0.5 x
VCCIO
0.6 x
VCCIO
0.44
0.44
1.2
1.3
0.26
CCIO
0.4 x V
CCIO
Table 2–19. Differential I/O Standard Specifications for Cyclone V Devices—Preliminary
VCCIO (V)
I/O Standard
Min
Typ
VID (mV)
Max
Min
Condition
VICM(DC) (V)
Max
Min
Max
(1)
VOD (V)
Min
(2)
VOCM (V)
Typ Max
Min
Typ
(2)
Max
PCML
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard.
For transmitter, receiver, and reference clock I/O pin specifications, refer to Table 2–20 on page 2–14.
2.5 V LVDS
2.375 2.5
2.625
100
VCM = 1.25 V
—
0.05
1.8
0.247
—
0.6
RSDS (HIO)
2.375 2.5
2.625
100
VCM = 1.25 V
—
0.3
1.4
0.1
0.2
0.6
0.5
1.2
1.4
Mini-LVDS
(HIO)
2.375 2.5
2.625
200
—
600
0.4
1.325
0.25
—
0.6
1
1.2
1.4
LVPECL
2.375 2.5
2.625
300
—
—
0.6
1.8
—
—
—
—
—
—
SLVS
2.375 2.5
2.625
100
VCM = 1.25 V
—
0.05
1.8
—
—
—
—
—
—
1.125 1.25 1.375
Notes to Table 2–19:
(1) The 1.4-V and 1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 2–14.
(2) RL range: 90 ≤ RL ≤ 110 Ω
Power Consumption
Altera offers two ways to estimate power consumption for a design—the Excel-based
Early Power Estimator (EPE) and the Quartus® II PowerPlay Power Analyzer feature.
1
You typically use the interactive Excel-based EPE before designing the FPGA to get a
magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer
provides better quality estimates based on the specifics of the design after you
complete place-and-route. The PowerPlay Power Analyzer can apply a combination
of user-entered, simulation-derived, and estimated signal activities that, when
combined with detailed circuit models, yields very accurate power estimates.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–14
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
Switching Characteristics
This section provides performance characteristics of Cyclone V core and periphery
blocks for commercial grade devices.
These characteristics can be designated as preliminary or final.
■
Preliminary characteristics are obtained using simulation results, process data,
and other known parameters. The title of these tables show the designation as
“Preliminary.”
■
Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no designations
on finalized tables.
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 2–20 lists the Cyclone V GX transceiver specifications.
Table 2–20. Transceiver Specifications for Cyclone V GX Devices—Preliminary (Part 1 of 3)
Symbol/
Description
C6
Speed Grade
Conditions
Min
Typ
C7, I7
Speed Grade
Max
Min
Typ
C8, A7
Speed Grade
Max
Min
Typ
Unit
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (1), HCSL, and LVDS
Input frequency from
REFCLK input pins
—
27
—
550
27
—
550
27
—
550
MHz
Duty cycle
—
45
—
55
45
—
55
45
—
55
%
Peak-to-peak
differential input voltage
—
200
—
2000
200
—
2000
200
—
2000
mV
Spread-spectrum
modulating clock
frequency
PCIe
30
—
33
30
—
33
30
—
33
kHz
Spread-spectrum
downspread
PCIe
—
—
—
—
—
—
—
On-chip termination
resistors
—
—
—
—
—
—
—
Ω
VICM (AC coupled)
—
VICM (DC coupled)
HCSL I/O
standard for the
PCIe reference
clock
250
—
550
250
—
550
250
—
550
mV
—
—
2000
±1%
—
—
2000
±1%
—
—
2000
±1%
—
Ω
RREF
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
0 to
–0.5%
100
1.1
(2)
0 to
–0.5%
100
1.1 (2)
0 to
–0.5%
100
1.1
(2)
V
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
2–15
Table 2–20. Transceiver Specifications for Cyclone V GX Devices—Preliminary (Part 2 of 3)
Symbol/
Description
C6
Speed Grade
Conditions
C7, I7
Speed Grade
C8, A7
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
—
125
—
—
125
—
—
125
—
Transceiver Clocks
fixedclk clock
frequency
PCIe
Receiver Detect
Avalon® MemoryMapped (Avalon-MM)
PHY management clock
frequency
< 150
MHz
MHz
Receiver
Supported I/O
Standards
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate
—
614
—
3125
614
—
3125
614
—
2500
Mbps
Absolute VMAX for a
receiver pin (3)
—
—
—
1.2
—
—
1.2
—
—
1.2
V
Absolute VMIN for a
receiver pin
—
–0.4
—
—
–0.4
—
—
–0.4
—
—
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before
device configuration
—
—
—
1.6
—
—
1.6
—
—
1.6
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) after
device configuration
—
—
—
2.2
—
—
2.2
—
—
2.2
V
Minimum differential
eye opening at the
receiver serial input
pins (4)
—
85
—
—
85
—
—
85
—
—
mV
85−Ω setting
—
85
—
—
85
—
—
85
—
Ω
100−Ω setting
—
100
—
—
100
—
—
100
—
Ω
120−Ω setting
—
120
—
—
120
—
—
120
—
Ω
150-Ω setting
—
150
—
—
150
—
—
150
—
Ω
Differential on-chip
termination resistors
Differential and
common mode return
loss
PCIe Gen1,
GIGE
Compliant
—
Programmable PPM
detector (5)
—
±62.5, 100, 125, 200, 250, 300, 500, and 1000
ppm
Run Length
—
—
—
200
—
—
200
—
—
200
UI
Programmable
equalization
—
—
—
4
—
—
4
—
—
4
dB
DC Gain Setting
=0
—
0
—
—
0
—
—
0
—
dB
DC Gain Setting
=1
—
3
—
—
3
—
—
3
—
dB
Programmable DC gain
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–16
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
Table 2–20. Transceiver Specifications for Cyclone V GX Devices—Preliminary (Part 3 of 3)
Symbol/
Description
C6
Speed Grade
Conditions
Min
Typ
C7, I7
Speed Grade
Max
Min
Typ
C8, A7
Speed Grade
Unit
Max
Min
Typ
Max
Transmitter
Supported I/O
Standards
1.5 V PCML
Data rate
—
614
—
3125
614
—
3125
614
—
2500
Mbps
VOCM
—
—
650
—
—
650
—
—
650
—
mV
85−Ω setting
—
85
—
—
85
—
—
85
—
Ω
100−Ω setting
—
100
—
—
100
—
—
100
—
Ω
120−Ω setting
—
120
—
—
120
—
—
120
—
Ω
150-Ω setting
—
150
—
—
150
—
—
150
—
Ω
Differential on-chip
termination resistors
Rise time
(6)
—
30
—
160
30
—
160
30
—
160
ps
(6)
—
30
—
160
30
—
160
30
—
160
ps
Supported data range
—
614
—
3125
614
—
3125
614
—
2500
Mbps
Fall time
CMU PLL
Transceiver-FPGA Fabric Interface
Interface speed
(single-width mode)
—
25
—
187.5
25
—
163.84
25
—
156.25
MHz
Interface speed
(double-width mode)
—
25
—
163.84
25
—
163.84
25
—
156.25
MHz
Notes to Table 2–20:
(1) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the
Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(5) The rate matcher supports only up to ±300 parts per million (ppm).
(6) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
2–17
Table 2–21 lists the Cyclone V GX transceiver block jitter specifications.
Table 2–21. Transceiver Block Jitter Specifications for Cyclone V GX Devices—Preliminary
Symbol/
Description
Conditions
PCIe Transmit Jitter Generation
Total jitter at
2.5 Gbps (Gen1)
C8, A7
Speed Grade
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
—
—
0.25
—
—
0.25
—
—
0.25
Unit
UI
(1)
Compliance pattern
GIGE Transmit Jitter Generation
C7, I7
Speed Grade
(1)
Compliance pattern
PCIe Receiver Jitter Tolerance
Total jitter at
2.5 Gbps (Gen1)
C6
Speed Grade
> 0.6
> 0.6
> 0.6
UI
(2)
Deterministic jitter
(peak-to-peak)
Pattern = CRPAT
—
—
0.14
—
—
0.14
—
—
0.14
UI
Total jitter
(peak-to-peak)
Pattern = CRPAT
—
—
0.279
—
—
0.279
—
—
0.279
UI
GIGE Receiver Jitter Tolerance
(2)
Deterministic jitter
tolerance
(peak-to-peak)
Pattern = CJPAT
> 0.4
> 0.4
> 0.4
UI
Combined
deterministic and
random jitter
tolerance
(peak-to-peak)
Pattern = CJPAT
> 0.66
> 0.66
> 0.66
UI
Notes to Table 2–21:
(1) The jitter numbers for PIPE are compliant to the PCIe Base Specification 2.0.
(2) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–18
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), and memory block specifications.
Clock Tree Specifications
Table 2–22 lists the clock tree specifications for Cyclone V devices.
Table 2–22. Clock Tree Performance for Cyclone V Devices—Preliminary
Performance
C6
Speed Grade
C7, I7
Speed Grade
C8, A7
Speed Grade
Unit
Global clock and Regional clock
550
550
460
MHz
Peripheral clock
155
155
155
MHz
Symbol
PLL Specifications
Table 2–23 lists the Cyclone V PLL specifications when operating in the commercial
(0° to 85°C), industrial (–40° to 100°C), and automotive (–40° to 125°C) junction
temperature ranges.
Table 2–23. PLL Specifications for Cyclone V Devices—Preliminary (1) (Part 1 of 3)
Symbol
Parameter
Min
C6 speed grade
fIN
Input clock frequency
C7, I7 speed grades
5
5
Typ
Max
Unit
—
670 (2)
MHz
—
622 (2)
MHz
MHz
5
—
500 (2)
fINPFD
Integer input clock frequency to the PFD
5
—
325
MHz
fFINPFD
Fractional input clock frequency to the PFD
50
—
TBD (1)
MHz
C6 speed grade
600
—
1600
MHz
C7, I7 speed grades
600
—
1400
MHz
C8, A7 speed grades
600
—
1300
MHz
40
—
60
%
—
550 (3)
MHz
MHz
C8, A7 speed grades
fVCO
tEINDUTY
PLL VCO operating range
Input clock or external feedback clock input duty cycle
C6 speed grade
fOUT
fOUT_EXT
Output frequency for internal global
or regional clock
Output frequency for external clock
output
—
C7, I7 speed grades
—
—
550 (3)
C8, A7 speed grades
—
—
460 (3)
MHz
C6 speed grade
—
—
667 (3)
MHz
C7, I7 speed grades
—
—
667 (3)
MHz
—
—
533 (3)
MHz
C8, A7 speed grades
tOUTDUTY
Duty cycle for external clock output (when set to 50%)
45
50
55
%
tFCOMP
External feedback clock compensation time
—
—
10
ns
—
tCONFIGPHASE
Time required to reconfigure phase shift
—
—
TBD (1)
tDYCONFIGCLK
Dynamic configuration clock
—
—
100
MHz
tLOCK
Time required to lock from end-of-device configuration or
deassertion of areset
—
—
1
ms
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
2–19
Table 2–23. PLL Specifications for Cyclone V Devices—Preliminary (1) (Part 2 of 3)
Symbol
Parameter
tDLOCK
fCLBW
Min
Typ
Max
Unit
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
—
—
1
ms
PLL closed-loop low bandwidth
—
0.3
—
MHz
PLL closed-loop medium bandwidth
—
1.5
—
MHz
—
4
—
MHz
PLL closed-loop high bandwidth
(8)
tPLL_PSERR
Accuracy of PLL phase shift
—
—
±50
ps
tARESET
Minimum pulse width on the areset signal
10
—
—
ns
Input clock cycle-to-cycle jitter (FREF ≥ 100 MHz)
—
—
0.15
UI (p-p)
Input clock cycle-to-cycle jitter (FREF < 100 MHz)
—
—
±750
ps (p-p)
tINCCJ
(4), (5)
Period jitter for dedicated clock output (FOUT ≥ 100 MHz)
(6)
tOUTPJ_DC
—
—
TBD
(1)
ps (p-p)
mUI (p-p)
Period jitter for dedicated clock output (FOUT < 100 MHz)
—
—
TBD
(1)
Cycle-to-cycle jitter for dedicated clock output
(FOUT ≥ 100 MHz)
—
—
TBD
(1)
ps (p-p)
Cycle-to-cycle jitter for dedicated clock output
(FOUT < 100 MHz)
—
—
TBD
(1)
mUI (p-p)
Period jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
—
TBD
(1)
ps (p-p)
Period jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
—
TBD
(1)
mUI (p-p)
Cycle-to-cycle jitter for clock output on regular I/O
(FOUT ≥ 100 MHz)
—
—
TBD
(1)
ps (p-p)
Cycle-to-cycle jitter for clock output on regular I/O
(FOUT < 100 MHz)
—
—
TBD
(1)
mUI (p-p)
tOUTPJ_DC_F
Period jitter for dedicated clock output in fractional mode
—
—
TBD (1)
—
tOUTCCJ_DC_F
Cycle-to-cycle jitter for dedicated clock output in fractional
mode
—
—
TBD (1)
—
tOUTPJ_IO_F
Period jitter for clock output on regular I/O in fractional
mode
—
—
TBD (1)
—
tOUTCCJ_IO_F
Cycle-to-cycle jitter for clock output on regular I/O in
fractional mode
—
—
TBD (1)
—
Period jitter for dedicated clock output in cascaded PLLs
(FOUT ≥ 100 MHz)
—
—
TBD
(1)
tCASC_OUTPJ_DC
ps (p-p)
Period jitter for dedicated clock output in cascaded PLLs
(FOUT < 100 MHz)
—
—
TBD
(1)
mUI (p-p)
(6)
tOUTCCJ_DC
tOUTPJ_IO
(6), (9)
tOUTCCJ_IO
(6), (9)
(6), (7)
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–20
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
Table 2–23. PLL Specifications for Cyclone V Devices—Preliminary (1) (Part 3 of 3)
Symbol
Parameter
tDRIFT
Frequency drift after PFDENA is disabled for a duration of
100 µs
dKBIT
Bit number of Delta Sigma Modulator (DSM)
kVALUE
Numerator of Fraction
fRES
Resolution of VCO frequency (fINPFD =100 MHz)
Min
Typ
Max
Unit
—
—
±10
%
—
24
TBD (1) 8388608
—
5.96
—
Bits
TBD (1)
—
—
Hz
Notes to Table 2–23:
(1) Pending silicon characterization.
(2) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(3) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.
(5) FREF is fIN/N when N = 1.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 2–28 on page 2–24.
(7) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 2–28 on page 2–24.
DSP Block Specifications
Table 2–24 lists the Cyclone V DSP block performance specifications.
Table 2–24. DSP Block Performance Specifications for Cyclone V Devices—Preliminary
Performance
Mode
C6
Speed Grade
C7, I7
Speed Grade
C8, A7
Speed Grade
Unit
Independent 9 x 9 Multiplication
340
300
260
MHz
Independent 18 x 19 Multiplication
287
250
200
MHz
Independent 18 x 18 Multiplication
287
250
200
MHz
Independent 27 x 27 Multiplication
250
200
160
MHz
Independent 18 x 25 Multiplication
310
250
200
MHz
Independent 20 x 24 Multiplication
310
250
200
MHz
Two 18 x 19 Multiplier Adder Mode
310
250
200
MHz
18 x 18 Multiplier Added Summed with 36-bit Input
310
250
200
MHz
310
250
200
MHz
Modes using One DSP Block
Modes using Two DSP Blocks
Complex 18 x 19 multiplication
Two 27 x 27 Multiplier Adder
250
200
160
MHz
Four 18 x 19 Multiplier Adder
310
250
200
MHz
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
2–21
Memory Block Specifications
Table 2–25 lists the Cyclone V memory block specifications.
Table 2–25. Memory Block Performance Specifications for Cyclone V Devices—Preliminary (1),
Resources Used
Memory
Mode
MLAB
M10K
Block
(2)
Performance
C6
C7, I7
C8, A7
Speed Grade Speed Grade Speed Grade
Unit
ALUTs
Memory
Single port, all supported widths
0
1
450
380
330
MHz
Simple dual-port, all supported
widths
0
1
450
380
330
MHz
Simple dual-port with read and
write at the same address
0
1
350
300
250
MHz
ROM, all supported width
0
1
450
380
330
MHz
Single-port, all supported widths
0
1
315
275
240
MHz
Simple dual-port, all supported
widths
0
1
315
275
240
MHz
Simple dual-port with the
read-during-write option set to
Old Data, all supported widths
0
1
275
240
180
MHz
True dual port, all supported
widths
0
1
315
275
240
MHz
ROM, all supported widths
0
1
315
275
240
MHz
Min Pulse Width (clock high time)
—
—
1,450
1,550
1,650
ps
Min Pulse Width (clock low time)
—
—
1,000
1,200
1,350
ps
Notes to Table 2–25:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Periphery Performance
This section describes periphery performance and the high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface.
General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-V LVTTL/LVCMOS
are capable of a typical 167 MHz and 1.2 LVCMOS at 100 MHz interfacing frequency
with 10 pF load.
1
February 2012
Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–22
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
High-Speed I/O Specification
Table 2–26 lists high-speed I/O timing for Cyclone V devices.
Table 2–26. High-Speed I/O Specifications for Cyclone V Devices—Preliminary (2),
Symbol
C6
Speed Grade
Conditions
(3)
(Part 1 of 2)
C7, I7
Speed Grade
C8, A7
Speed Grade
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fHSCLK_in (input
clock frequency)
True Differential I/O
Standards
Clock boost factor W = 1
to 40 (4)
5
—
437.5
5
—
420
5
—
320
MHz
fHSCLK_in (input
clock frequency)
Single Ended I/O
Standards
Clock boost factor W = 1
to 40 (4)
5
—
320
5
—
320
5
—
275
MHz
fHSCLK_OUT (output
clock frequency)
—
5
—
420
5
—
370
5
—
320
MHz
SERDES factor J = 4 to 10
(5)
—
840
(5)
—
740
(5)
—
640
Mbps
SERDES factor J = 1 to 2,
Uses DDR Registers
(5)
—
(7)
(5)
—
(7)
(5)
—
(7)
Mbps
Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks - fHSDR
(data rate) (6)
SERDES factor J = 4 to 10
(5)
—
640
(5)
—
640
(5)
—
550
Mbps
Emulated
Differential I/O
Standards with One
External Output
Resistor Network fHSDR (data rate) (6)
SERDES factor J = 4 to 10
(5)
—
170
(5)
—
170
(5)
—
170
Mbps
Total Jitter for Data Rate,
600 Mbps - 840 Mbps
—
—
160
—
—
160
—
—
160
ps
Total Jitter for Data Rate,
< 600 Mbps
—
—
0.1
—
—
0.1
—
—
0.1
UI
tx Jitter - Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks
Total Jitter for Data Rate
< 640 Mbps
—
—
TBD (1)
—
—
TBD (1)
—
—
TBD (1)
UI
tx Jitter - Emulated
Differential I/O
Standards with One
External Output
Resistor Network
Total Jitter for Data Rate
< 640 Mbps
—
—
TBD (1)
—
—
TBD (1)
—
—
TBD (1)
UI
Transmitter
True Differential I/O
Standards - fHSDR
(data rate)
tx Jitter - True
Differential I/O
Standards
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
2–23
Table 2–26. High-Speed I/O Specifications for Cyclone V Devices—Preliminary (2),
Symbol
tDUTY
tRISE & tFALL
TCCS
C6
Speed Grade
Conditions
(3)
(Part 2 of 2)
C7, I7
Speed Grade
C8, A7
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
TX output clock duty
cycle for both True and
Emulated Differential I/O
Standards
45
50
55
45
50
55
45
50
55
%
True Differential I/O
Standards
—
—
200
—
—
200
—
—
200
ps
Emulated Differential I/O
Standards with Three
External Output Resistor
Networks
—
—
250
—
—
250
—
—
300
ps
Emulated Differential I/O
Standards with One
External Output Resistor
Network
—
—
300
—
—
300
—
—
300
ps
True Differential I/O
Standards
—
—
200
—
—
250
—
—
250
ps
Emulated Differential I/O
Standards with Three
External Output Resistor
Networks
—
—
300
—
—
300
—
—
300
ps
Emulated Differential I/O
Standards with One
External Output Resistor
Network
—
—
300
—
—
300
—
—
300
ps
SERDES factor J = 4 to 10
(5)
—
875 (6)
(5)
—
840 (6)
(5)
—
SERDES factor J = 1 to 2,
Uses DDR Registers
(5)
—
(7)
(5)
—
(7)
(5)
—
(7)
Mbps
—
—
—
350
—
—
350
—
—
350
ps
Receiver
fHSDR (data rate)
Sampling Window
640 (6) Mbps
Notes to Table 2–26:
(1) Pending silicon characterization.
(2) When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.
(3) This is achieved by using the LVDS clock network.
(4) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
(5) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(6) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
(7) The maximum ideal frequency is the SERDES factor (J) x PLL max output frequency (fout), provided you can close the design timing and the
signal integrity simulation is clean.You can estimate the achievable maximum data rate by performing link timing closure analysis. You must
consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–24
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
DQS Logic Block and Memory Output Clock Jitter Specifications
Table 2–27 lists the DQS phase shift error for Cyclone V devices.
Table 2–27. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Cyclone V
Devices—Preliminary (1), (2)
Number of DQS Delay
Buffers
C6
Speed Grade
C7, I7
Speed Grade
C8, A7
Speed Grade
Unit
2
69
70
80
ps
Notes to Table 2–27:
(1) The numbers are preliminary pending silicon characterization.
(2) This error specification is the absolute maximum and minimum error. For example, skew on two DQS delay buffers
in a –7 speed grade is 70 ps or ±35 ps.
(3) Delay chain engineering option setting: rb_co[1:0]=“11”.
Table 2–28 lists the memory output clock jitter specifications for Cyclone V devices.
Table 2–28. Memory Output Clock Jitter Specification for Cyclone V Devices—Preliminary (1),
Clock
Network
Parameter
C6
Speed Grade
Symbol
(2), (3)
C7, I7
Speed Grade
C8, A7
Speed Grade
Min
Max
Min
Max
Min
Max
Unit
Clock period jitter
Regional
tJIT(per)
TBD
TBD
TBD
TBD
TBD
TBD
ps
Cycle-to-cycle period
jitter
Regional
tJIT(cc)
TBD
TBD
TBD
TBD
TBD
TBD
ps
Duty cycle jitter
Regional
tJIT(duty)
TBD
TBD
TBD
TBD
TBD
TBD
ps
Clock period jitter
Global
tJIT(per)
TBD
TBD
TBD
TBD
TBD
TBD
ps
Cycle-to-cycle period
jitter
Global
tJIT(cc)
TBD
TBD
TBD
TBD
TBD
TBD
ps
Duty cycle jitter
Global
tJIT(duty)
TBD
TBD
TBD
TBD
TBD
TBD
ps
Notes to Table 2–28:
(1) Pending silicon characterization.
(2) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(3) The clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by
a PLL output routed on a PHY, regional, or global clock network as specified. Altera recommends using PHY clock networks whenever possible.
OCT Calibration Block Specifications
Table 2–29 lists the OCT calibration block specifications for Cyclone V devices.
Table 2–29. OCT Calibration Block Specifications for Cyclone V Devices—Preliminary (Part 1 of 2)
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
—
20
MHz
TOCTCAL
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
—
1000
—
Cycles
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Switching Characteristics
2–25
Table 2–29. OCT Calibration Block Specifications for Cyclone V Devices—Preliminary (Part 2 of 2)
Symbol
Description
Min
Typ
Max
Unit
TOCTSHIFT
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
—
32
—
Cycles
TRS_RT
Time required between the dyn_term_ctrl and oe signal
transitions in a bidirectional I/O buffer to dynamically switch
between RS OCT and RT OCT
—
2.5
—
ns
Figure 2–1 shows the timing diagram for the oe and dyn_term_ctrl signals.
Figure 2–1. Timing Diagram for the oe and dyn_term_ctrl Signals
Tristate
RX
Tristate
TX
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
[
Duty Cycle Distortion (DCD) Specifications
Table 2–30 lists the worst-case DCD for Cyclone V devices.
Table 2–30. Worst-Case DCD on I/O Pins for Cyclone V Devices—Preliminary
Symbol
Output Duty Cycle
February 2012
Altera Corporation
C6
Speed Grade
C7, I7
Speed Grade
C8, A7
Speed Grade
Min
Max
Min
Max
Min
Max
45
55
45
55
45
55
Unit
%
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–26
Chapter 2: Device Datasheet for Cyclone V Devices
Configuration Specification
Configuration Specification
This section provides configuration specifications and timing for Cyclone V devices.
These characteristics can be designated as preliminary or final.
■
Preliminary characteristics are obtained using simulation results, process data,
and other known parameters. The title of these tables show the designation as
“Preliminary.”
■
Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no designations
on finalized tables.
POR Specifications
Table 2–31 lists the specifications for fast and standard POR delay for Cyclone V
devices.
Table 2–31. Fast and Standard POR Delay Specification for Cyclone V Devices
PORSEL Pin Setting
Minimum (ms)
Maximum (ms)
Fast (1)
POR Delay
High
4
12
Standard
GND
100
300
Note to Table 2–31:
(1) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize
after the POR trip.
JTAG Configuration Timing
Table 2–32 lists the JTAG timing parameters and values for Cyclone V devices.
Table 2–32. JTAG Timing Parameters and Values for Cyclone V Devices—Preliminary
Symbol
Description
Min
Max
Unit
tJCP
TCK clock period
30
—
ns
tJCH
TCK clock high time
14
—
ns
tJCL
TCK clock low time
14
—
ns
tJPSU (TDI)
TDI JTAG port setup time
1
—
ns
tJPSU (TMS)
TMS JTAG port setup time
3
—
ns
tJPH
JTAG port hold time
5
—
ns
tJPCO
tJPZX
tJPXZ
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
—
—
—
11
(1)
ns
14
(1)
ns
14
(1)
ns
Note to Table 2–32:
(1) A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Configuration Specification
2–27
FPP Configuration Timing
This section describes the fast passive parallel (FPP) configuration timing parameters
for Cyclone V devices.
DCLK-to-DATA[] Ratio (r) for FPP Configuration
FPP configuration requires a different DCLK-to-DATA[] ratio when you turn on
encryption or the compression feature.
Table 2–33 lists the DCLK-to-DATA[] ratio for each combination.
Table 2–33. DCLK-to-DATA[] Ratio for Cyclone V Devices—Preliminary (1)
Configuration Scheme
FPP (8-bit wide)
FPP (16-bit wide)
Encryption
Compression
DCLK-to-DATA[] ratio (r)
Off
Off
1
On
Off
1
Off
On
2
On
On
2
Off
Off
1
On
Off
2
Off
On
4
On
On
4
Note to Table 2–33:
(1) Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[]
rate in byte per second (Bps) or word per second (Wps). For example, in FPP x16 where the r is 2, the DCLK
frequency must be 2 times the DATA[] rate in Wps.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–28
Chapter 2: Device Datasheet for Cyclone V Devices
Configuration Specification
FPP Configuration Timing when DCLK to DATA[] = 1
Figure 2–2 shows the timing waveform for an FPP configuration when using a
MAX® II device as an external host. This waveform shows timing when the
DCLK-to-DATA[] ratio is 1.
1
When you enable decompression or the design security feature, the DCLK-to-DATA[]
ratio varies for FPP x8 and FPP x16. For the respective DCLK-to-DATA[] ratio, refer to
Table 2–33 on page 2–27.
Figure 2–2. DCLK-to-DATA[] FPP Configuration Timing Waveform for Cyclone V Devices When the Ratio is 1 (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
(6)
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
(4)
DCLK
tDH
DATA[15..0](5)
Word 0 Word 1 Word 2 Word 3
Word n-2 Word n-1
User Mode
Word n
tDSU
User I/O
High-Z
User Mode
INIT_DONE (7)
tCD2UM
Notes to Figure 2–2:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When
nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power up, the Cyclone V device holds nSTATUS low for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) For FPP x16, use DATA[15..0]. For FPP x8, use DATA[7..0]. DATA[15..0] are available as a user I/O pin after configuration. The state of this
pin depends on the dual-purpose pin settings.
(6) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONE is released high when the Cyclone V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization
and enter user mode.
(7) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Configuration Specification
2–29
Table 2–34 lists the timing parameters for Cyclone V devices for an FPP configuration
when the DCLK-to-DATA[] ratio is 1.
Table 2–34. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices When the Ratio is 1—Preliminary
Symbol
Parameter
(1)
Minimum
Maximum
Unit
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
µs
tSTATUS
nSTATUS low pulse width
268
1506
(2)
µs
tCF2ST1
nCONFIG high to nSTATUS high
—
1506
(3)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
1506
—
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
—
µs
tDSU
DATA[] setup time before rising edge on
DCLK
5.5
—
ns
tDH
DATA[] hold time after rising edge on DCLK
0
—
ns
tCH
DCLK high time
0.45 x 1/fMAX
—
ns
tCL
DCLK low time
0.45 x 1/fMAX
—
ns
tCLK
DCLK period
1/fMAX
—
ns
fMAX
DCLK frequency (FPP x8 and x16)
—
125
MHz
tR
Input rise time
—
40
ns
tF
Input fall time
—
40
ns
tCD2UM
CONF_DONE high to user mode
175
437
µs
tCD2CU
CONF_DONE high to CLKUSR enabled
4 × maximum DCLK period
—
—
tCD2UMC
CONF_DONE high to user mode with CLKUSR
option on
—
—
—
Cycles
Tinit
(4)
Number of clock cycles required for device
initialization
tCD2CU + (Tinit x CLKUSR
period)
17,408
Notes to Table 2–34:
(1) Use these timing parameters when the DCLK-to-DATA[] ratio is 1. To find the DCLK-to-DATA[] ratio for your system, refer to Table 2–33 on
page 2–27.
(2) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) You can obtain this value if you do not delay configuration by externally holding nSTATUS low.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
February 2012
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Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
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Chapter 2: Device Datasheet for Cyclone V Devices
Configuration Specification
FPP Configuration Timing when DCLK to DATA[] > 1
Figure 2–3 shows the timing waveform for an FPP configuration when using a
MAX II device or microprocessor as an external host. This waveform shows timing
when the DCLK-to-DATA[]ratio is more than 1.
Figure 2–3. FPP Configuration Timing Waveform for Cyclone V Devices When the DCLK-to-DATA[] Ratio is > 1
(1), (2)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (3)
CONF_DONE (4)
DCLK (6)
tSTATUS
tCF2ST0
tCF2CD
tCL
tST2CK
(8)
tCH
1
2
r
1
2
r
(7)
1
r
1
(5)
2
tCLK
Word 0
DATA[15..0] (8)
tDSU
User I/O
tDH
Word 1
Word 3
Word (n-1) Word n
User Mode
tDH
User Mode
High-Z
INIT_DONE (9)
tCD2UM
Notes to Figure 2–3:
(1) To find the DCLK-to-DATA[] ratio for your system, refer to Table 2–33 on page 2–27.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(3) After power up, the Cyclone V device holds nSTATUS low for the time as specified by the POR delay.
(4) After power up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) “r” denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design security feature enable
settings, refer to Table 2–33 on page 2–27.
(7) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[15..0] pins prior to sending
the first DCLK rising edge.
(8) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONE is released high after the Cyclone V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
(9) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Configuration Specification
2–31
Table 2–35 lists the timing parameters for Cyclone V devices when the
DCLK-to-DATA[]ratio is more than 1.
Table 2–35. DCLK-to-DATA[] FPP Timing Parameters for Cyclone V Devices when the Ratio is > 1—Preliminary (1)
Symbol
Parameter
Minimum
Maximum
Unit
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
µs
tSTATUS
nSTATUS low pulse width
268
1506
(2)
µs
tCF2ST1
nCONFIG high to nSTATUS high
—
1506
(3)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
1506
—
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
—
µs
tDSU
DATA[] setup time before rising edge on
DCLK
5.5
—
ns
tDH
DATA[] hold time after rising edge on DCLK
N–1/fDCLK (4)
—
ns
tCH
DCLK high time
0.45 x 1/fMAX
—
ns
tCL
DCLK low time
0.45 x 1/fMAX
—
ns
tCLK
DCLK period
1/fMAX
—
ns
fMAX
DCLK frequency (FPP x8 and x16)
—
125
MHz
tR
Input rise time
—
40
ns
tF
Input fall time
—
40
ns
tCD2UM
CONF_DONE high to user mode (5)
175
437
µs
tCD2CU
CONF_DONE high to CLKUSR enabled
4 × maximum DCLK period
—
—
tCD2UMC
CONF_DONE high to user mode with CLKUSR
option on
—
—
—
Cycles
Tinit
tCD2CU + (Tinit x CLKUSR
Number of clock cycles required for device
initialization
period)
17,408
Notes to Table 2–35:
(1) Use these timing parameters when you use decompression and the design security features.
(2) This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) This value can be obtained if you do not delay configuration by externally holding nSTATUS low.
(4) N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating.
(5) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
February 2012
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Chapter 2: Device Datasheet for Cyclone V Devices
Configuration Specification
AS Configuration Timing
Figure 2–4 shows the timing waveform for the active serial (AS) x1 mode and AS x4
mode configuration timing.
Figure 2–4. AS Configuration Timing for Cyclone V Devices
tPOR (1)
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
tCO
tDH
Read Address
AS_DATA0/ASDO
tSU
AS_DATA1 (2)
bit N
bit N - 1
bit 1
bit 0
tCD2UM (3)
INIT_DONE (4)
User I/O
User Mode
Notes to Figure 2–4:
(1) The AS scheme supports standard and fast POR delay (tPOR). For tPOR delay information, refer to “POR Delay Specification” in the Configuration,
Design Security, and remote System Upgrades in Cyclone V Devices chapter.
(2) If you are using AS x4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle.
(3) The initialization clock can be from the internal oscillator or the CLKUSR pin.
(4) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
Table 2–36 lists the timing parameters for AS x1 and AS x4 configurations in
Cyclone V devices.
Table 2–36. AS Timing Parameters for AS x1 and x4 Configurations in Cyclone V Devices—Preliminary
Symbol
(1), (2)
Parameter
Minimum
Maximum
Unit
tCO
DCLK falling edge to the AS_DATA0/ASDO output
—
4
µs
tSU
Data setup time before the rising edge on DCLK
1.5
—
ns
tH
Data hold time after the rising edge on DCLK
0
—
ns
tCD2UM
CONF_DONE high to user mode
175
437
µs
tCD2CU
CONF_DONE high to CLKUSR enabled
4 x maximum DCLK period
—
—
—
—
—
Cycles
tCD2UMC
Tinit
CONF_DONE high to user mode with CLKUSR
option on
Number of clock cycles required for device
initialization
tCD2CU + (Tinit x CLKUSR
period)
17,408
Notes to Table 2–36:
(1) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(2) The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in
Table 2–38 on page 2–34.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Configuration Specification
2–33
Table 2–37 lists the internal clock frequency specification for the AS configuration
scheme.
Table 2–37. DCLK Frequency Specification in the AS Configuration Scheme for Cyclone V
Devices—Preliminary (1), (2)
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
10.6
15.7
25.0
MHz
21.3
31.4
50.0
MHz
42.6
62.9
100.0
MHz
Notes to Table 2–37:
(1) This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock
source.
(2) The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz.
PS Configuration Timing
Figure 2–5 shows the timing waveform for a PS configuration when using a MAX II
device or microprocessor as an external host.
Figure 2–5. PS Configuration Timing Waveform for Cyclone V Devices (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
(6)
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
(4)
DCLK
tDH
DATA0
Bit 0 Bit 1 Bit 2 Bit 3
(5)
Bit n
tDSU
User I/O
High-Z
User Mode
INIT_DONE (7)
tCD2UM
Notes to Figure 2–5:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When
nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power up, the Cyclone V device holds nSTATUS low for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) DATA0 is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins
Option.
(6) To ensure a successful configuration, send the entire configuration data to the Cyclone V device. CONF_DONE is released high after the Cyclone V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
(7) After the option bit to enable the INIT_DONE pin is configured into the device, INIT_DONE goes low.
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–34
Chapter 2: Device Datasheet for Cyclone V Devices
Configuration Specification
Table 2–38 lists the PS timing parameter for Cyclone V devices.
Table 2–38. PS Timing Parameters for Cyclone V Devices—Preliminary
Symbol
Parameter
Minimum
Maximum
Unit
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
µs
tSTATUS
nSTATUS low pulse width
268
1506
(1)
µs
tCF2ST1
nCONFIG high to nSTATUS high
—
1506
(2)
µs
tCF2CK
nCONFIG high to first rising edge on DCLK
1506
—
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
—
µs
tDSU
DATA[] setup time before rising edge on DCLK
5.5
—
ns
tDH
DATA[] hold time after rising edge on DCLK
0
—
ns
tCH
DCLK high time
0.45 x 1/fMAX
—
ns
tCL
DCLK low time
0.45 x 1/fMAX
—
ns
tCLK
DCLK period
1/fMAX
—
ns
fMAX
DCLK frequency
—
125
MHz
tR
Input rise time
—
40
ns
tF
Input fall time
—
40
ns
tCD2UM
CONF_DONE high to user mode (3)
175
437
µs
tCD2CU
CONF_DONE high to CLKUSR enabled
4 x maximum DCLK period
—
—
tCD2UMC
CONF_DONE high to user mode with CLKUSR option on
tCD2CU + (Tinit x CLKUSR period)
—
—
Tinit
Number of clock cycles required for device initialization
17,408
—
Cycles
Notes to Table 2–38:
(1) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) You can obtain this value if you do not delay configuration by externally holding nSTATUS low.
(3) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
I/O Timing
2–35
Remote System Upgrades Circuitry Timing Specification
Table 2–39 lists the timing parameter specifications for the remote system upgrade
circuitry.
Table 2–39. Remote System Upgrade Circuitry Timing Specification for Cyclone V Devices—
Preliminary
Parameter
Minimum
Maximum
Unit
tMAX_RU_CLK (1)
—
40
MHz
tRU_nCONFIG (2)
250
—
ns
250
—
ns
tRU_nRSTIMER
(3)
Notes to Table 2–39:
(1) This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE
megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification.
(2) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to “Remote System Upgrade State Machine” in the
Device Interfaces and Integration Basics for Cyclone V Devices chapter.
(3) This is equivalent to strobing the reset timer input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to “User Watchdog Timer” in the Device Interfaces and
Integration Basics for Cyclone V Devices chapter.
User Watchdog Internal Oscillator Frequency Specification
Table 2–40 lists the frequency specifications for the user watchdog internal oscillator.
Table 2–40. User Watchdog Internal Oscillator Frequency Specifications for Cyclone V
Devices—Preliminary
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
1
February 2012
The Excel-based I/O Timing spreadsheet will be available in the future release of the
Quartus II software.
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–36
Chapter 2: Device Datasheet for Cyclone V Devices
I/O Timing
Programmable IOE Delay
Table 2–41 lists the Cyclone V IOE programmable delay settings.
Table 2–41. IOE Programmable Delay for Cyclone V Devices
(1)
Fast Model
Slow Model
Available
Settings
Minimum
Offset
Industrial
Commercial
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Parameter
C8, A7
Speed Grade
Unit
TBD
TBD
ns
TBD
TBD
TBD
ns
TBD
TBD
TBD
ns
TBD
TBD
TBD
TBD
ns
TBD
TBD
TBD
TBD
ns
C6
C7, I7
Speed Grade Speed Grade
Note to Table 2–41:
(1) Pending data extraction from the Quartus II software.
Programmable Output Buffer Delay
Table 2–42 lists the delay chain settings that control the rising and falling edge delays
of the output buffer. The default delay is 0 ps.
Table 2–42. Programmable Output Buffer Delay for Cyclone V Devices—Preliminary
Symbol
DOUTBUF
Parameter
Rising and/or falling edge
delay
(1), (2)
Typical
Unit
0 (default)
ps
50
ps
100
ps
150
ps
Notes to Table 2–42:
(1) Pending data extraction from the Quartus II software.
(2) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Glossary
2–37
Glossary
Table 2–43 lists the glossary for this chapter.
Table 2–43. Glossary Table (Part 1 of 4)
Letter
Subject
Definitions
A
B
—
—
C
Receiver Input Waveforms
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
VID
p−n=0V
VID
D
Differential I/O
Standards
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
VOD
p−n=0V
VOD
E
F
—
—
fHSCLK
Left/right PLL input clock frequency.
fHSDR
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDRDPA
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
G
H
—
—
I
February 2012
Altera Corporation
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–38
Chapter 2: Device Datasheet for Cyclone V Devices
Glossary
Table 2–43. Glossary Table (Part 2 of 4)
Letter
Subject
J
Definitions
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
TMS
TDI
J
t JCP
JTAG Timing
Specifications
t JCH
t JCL
t JPH
t JPSU
TCK
tJPZX
t JPXZ
t JPCO
TDO
K
L
—
M
—
N
O
Diagram of PLL Specifications
(1)
CLKOUT Pins
Switchover
fOUT_EXT
4
CLK
fIN
N
fINPFD
PFD
CP
LF
VCO fVCO
Core Clock
P
Counters
C0..C17
fOUT
PLL
Specifications
GCLK
RCLK
Delta Sigma
Modulator
Key
Reconfigurable in User Mode
External Feedback
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
Q
R
—
RL
—
Receiver differential input discrete resistor (external to the Cyclone V device).
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Glossary
2–39
Table 2–43. Glossary Table (Part 3 of 4)
Letter
Subject
Sampling window
(SW)
Definitions
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
The JEDEC standard for the SSTl and HSTL I/O defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing, as shown:
S
Single-Ended Voltage Referenced I/O Standard
Single-ended
voltage
referenced I/O
standard
VCCIO
VOH
VIH (AC )
VIH(DC)
VREF
VIL(DC)
VIL(AC )
VOL
VSS
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channelto-channel-skew)
The timing difference between the fastest and slowest output edges, including the tCO
variation and clock skew, across channels driven by the same PLL. The clock is included in
the TCCS measurement (refer to the Timing Diagram figure under SW in this table).
High-speed I/O block—Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
tDUTY
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
T
tFALL
Signal high-to-low transition time (80-20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input
tOUTPJ_IO
Period jitter on the general purpose I/O driven by a PLL
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL
tRISE
Signal low-to-high transition time (20–80%)
U
February 2012
—
Altera Corporation
—
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–40
Chapter 2: Device Datasheet for Cyclone V Devices
Document Revision History
Table 2–43. Glossary Table (Part 4 of 4)
Letter
V
W
Subject
Definitions
VCM(DC)
DC common mode input voltage.
VICM
Input common mode voltage—The common mode of the differential signal at the receiver.
VID
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VDIF(AC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
VDIF(DC)
DC differential input voltage— Minimum DC input differential voltage required for switching.
VIH
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
VIH(AC)
High-level AC input voltage
VIH(DC)
High-level DC input voltage
VIL
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
VIL(AC)
Low-level AC input voltage
VIL(DC)
Low-level DC input voltage
VOCM
Output common mode voltage—The common mode of the differential signal at the
transmitter.
VOD
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VSWING
Differential input voltage
VX
Input differential cross point voltage
VOX
Output differential cross point voltage
W
High-speed I/O block—Clock Boost Factor
X
Y
—
—
Z
Document Revision History
Table 2–44 lists the revision history for this chapter.
Table 2–44. Document Revision History
Date
February 2012
Version
1.2
November 2011
1.1
October 2011
1.0
Changes
■
Added automotive speed grade information.
■
Added Figure 2–1.
■
Updated Table 2–3, Table 2–8, Table 2–9, Table 2–20, Table 2–21, Table 2–22,
Table 2–23, Table 2–24, Table 2–25, Table 2–26, Table 2–27, Table 2–28, Table 2–30,
Table 2–35, and Table 2–41.
■
Minor text edits.
■
Added Table 2–5.
■
Updated Table 2–3, Table 2–4, Table 2–11, Table 2–13, Table 2–20, and Table 2–21.
Initial release.
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
Chapter 2: Device Datasheet for Cyclone V Devices
Document Revision History
February 2012
Altera Corporation
2–41
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
2–42
Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
Chapter 2: Device Datasheet for Cyclone V Devices
Document Revision History
February 2012 Altera Corporation
Additional Information
This chapter provides additional information about the document and Altera.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Contact (1)
Technical support
Technical training
Product literature
Contact Method
Address
Website
www.altera.com/support
Website
www.altera.com/training
Email
[email protected]
Website
www.altera.com/literature
Nontechnical support (general)
Email
nac[email protected]
(software licensing)
Email
[email protected]
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual Cue
Meaning
Bold Type with Initial Capital
Letters
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
bold type
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
Italic Type with Initial Capital Letters
Indicate document titles. For example, Stratix IV Design Guidelines.
Indicates variables. For example, n + 1.
italic type
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Initial Capital Letters
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
“Subheading Title”
Quotation marks indicate references to sections in a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
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Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
Info–2
Additional Information
Typographic Conventions
Visual Cue
Meaning
Indicates signal, port, register, bit, block, and primitive names. For example, data1,
tdi, and input. The suffix n denotes an active-low signal. For example, resetn.
Courier type
Indicates command line commands and anything that must be typed exactly as it
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for
example, TRI).
r
An angled arrow instructs you to press the Enter key.
1., 2., 3., and
a., b., c., and so on
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
■ ■
Bullets indicate a list of items when the sequence of the items is not important.
■
1
The hand points to information that requires special attention.
h
The question mark directs you to a software help system with related information.
f
The feet direct you to another document or website with related information.
m
The multimedia icon directs you to a related multimedia presentation.
c
A caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
w
A warning calls attention to a condition or possible situation that can cause you
injury.
The envelope links to the Email Subscription Management Center page of the Altera
website, where you can sign up to receive update notifications for Altera documents.
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