BSI BS616LV2019AIP55 Very low power cmos sram 128k x 16 bit Datasheet

Very Low Power CMOS SRAM
128K X 16 bit
BS616LV2019
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
n DESCRIPTION
Ÿ Wide VCC operation voltage : 2.4V ~ 3.6V
Ÿ Very low power consumption :
VCC = 3.0V
Operation current : 25mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.3uA (Typ.) at 25 OC
Ÿ High speed access time :
-55
55ns(Max.) at VCC=2.7~3.6V
-70
70ns(Max.) at VCC=2.4~3.6V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE and OE options
Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation
Ÿ Data retention supply voltage as low as 1.5V
The BS616LV2019 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 by 16 bits and
operates form a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.3uA at 3.0V/25OC and maximum access time of 55ns at
2.7V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BS616LV2019 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV2019 is available in DICE form, JEDEC standard
48-pin TSOP Type I package and 48-ball BGA package.
n POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
OPERATING
TEMPERATURE
STANDBY
Operating
(ICCSB1, Max)
(ICC, Max)
VCC=3.0V
VCC=3.0V
10MHz
1MHz
PKG TYPE
fMax.
BS616LV2019DC
DICE
Commercial
+0OC to +70OC
BS616LV2019AC
3.0uA
1.5mA
9mA
23mA
BGA-48-0608
BS616LV2019TC
TSOP I-48
BS616LV2019AI
Industrial
-40OC to +85OC
BS616LV2019TI
5.0uA
2mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
BGA-48-0608
25mA
TSOP I-48
n BLOCK DIAGRAM
n PIN CONFIGURATIONS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
UB
LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
10mA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BS616LV2019TC
BS616LV2019TI
A16
NC
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
GND
CE
A0
A6
A7
A8
A9
A10
A11
A15
A14
A13
A12
Address
1024
10
Input
Row
Buffer
Decoder
Memory Array
1024 x 2048
2048
DQ0
.
16
.
.
.
.
.
.
.
.
.
.
.
16
Data
Input
Buffer
Data
Output
Buffer
16
Column I/O
Write Driver
Sense Amp
16
128
Column Decoder
DQ15
A
1
2
3
4
5
6
LB
OE
A0
A1
A2
NC
B
D8
UB
A3
A4
CE
D0
C
D9
D10
A5
A6
D1
D2
D
VSS
D11
NC
A7
D3
VCC
E
VCC
D12
NC
A16
D4
VSS
F
D14
D13
A14
A15
D5
D6
G
D15
NC
A12
A13
WE
D7
H
NC
A8
A9
A10
A11
NC
CE2,CE
WE
OE
UB
LB
7
Control
Address Input Buffer
A16 A0
A1
A2
A3
A4
A5
VCC
VSS
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS616LV2019
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Revision 1.3
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2006
BS616LV2019
n PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 262,144 x 16 bit in the RAM
CE Chip Enable 1 Input
CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected. (48B BGA ignore CE2 pin)
CE2 Chip Enable 2 Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0-DQ15 Data Input/Output
16 bi-directional ports are used to read data from or write data into the RAM.
Ports
VCC
Power Supply
VSS
Ground
n TRUTH TABLE
MODE
Chip De-selected
(Power Down)
CE
CE2(1)
WE
OE
LB
UB
H
X
X
X
X
X
High Z
High Z
ICCSB, ICCSB1
X
L
X
X
X
X
High Z
High Z
ICCSB, ICCSB1
X
X
X
X
H
H
High Z
High Z
ICCSB, ICCSB1
L
H
H
H
L
X
High Z
High Z
ICC
L
H
H
H
X
L
High Z
High Z
ICC
L
L
DOUT
DOUT
ICC
H
L
High Z
DOUT
ICC
L
H
DOUT
High Z
ICC
L
L
DIN
DIN
ICC
H
L
X
DIN
ICC
L
H
DIN
X
ICC
DQ0~DQ7 DQ8~DQ15 VCC CURRENT
Output Disabled
Read
Write
L
L
H
H
H
L
L
X
1. 48BGA ignore CE2 condition.
2. H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
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BS616LV2019
(1)
n ABSOLUTE MAXIMUM RATINGS
RATING
UNITS
RANG
AMBIENT
TEMPERATURE
VCC
Terminal Voltage with
Respect to GND
Temperature Under
Bias
-0.5(2) to 5.0
V
Commercial
0OC to + 70OC
2.4V ~ 3.6V
-40 to +125
O
C
Industrial
-40OC to + 85OC
2.4V ~ 3.6V
Storage Temperature
-60 to +150
O
C
SYMBOL
VTERM
TBIAS
TSTG
n OPERATING RANGE
PARAMETER
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
n CAPACITANCE
(1)
O
(TA = 25 C, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. –2.0V in case of AC pulse width less than 30 ns.
CIN
CIO
Input
Capacitance
Input/Output
Capacitance
VIN = 0V
6
pF
VI/O = 0V
8
pF
1. This parameter is guaranteed and not 100% tested.
O
O
n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C)
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
2.4
--
3.6
V
VCC
Power Supply
VIL
Input Low Voltage
-0.5(2)
--
0.8
V
VIH
Input High Voltage
2.2
--
VCC+0.3(3)
V
IIL
Input Leakage Current
--
--
1
uA
ILO
Output Leakage Current
--
--
1
uA
VOL
Output Low Voltage
V CC = Max, IOL = 2.0mA
--
--
0.4
V
VOH
Output High Voltage
V CC = Min, IOH = -1.0mA
2.4
--
--
V
ICC(5)
Operating Power Supply
Current
CE = VIL and CE2(7) = VIH,
VCC=3.0V
--
--
25
mA
ICC1
Operating Power Supply
Current
CE = VIL and CE2(7) = VIH,
VCC=3.0V
--
--
2
mA
VCC=3.0V
--
--
0.5
mA
VCC=3.0V
--
0.3
5
uA
ICCSB
Standby Current – TTL
VIN = 0V to VCC
CE= VIH or CE2(7) = VIL
VI/O = 0V to V CC,
CE= VIH or CE2(7) = VIL or OE = VIH
IIO = 0mA, f = FMAX(4)
IIO = 0mA, f = 1MHz
CE = VIH or CE2(7) = VIL,
IIO = 0mA
ICCSB1(6)
Standby Current – CMOS
CE≧VCC-0.2V or CE2(7)≦0.2V,
VIN≧V CC-0.2V or VIN≦0.2V
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
R0201-BS616LV2019
5. ICC (MAX.) is 23mA at VCC=3.0V and TA=70OC.
6. ICCSB1(MAX.) is 3uA at VCC=3.0V and TA=70OC.
7. 48B BGA ignore CE2 condition.
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Revision 1.3
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2006
BS616LV2019
O
O
n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C)
MIN.
TYP. (1)
MAX.
UNITS
VCC for Data Retention
CE≧VCC-0.2V or CE2(4)≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
1.5
--
--
V
Data Retention Current
CE≧VCC-0.2V or CE2(4)≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
--
0.1
1.0
uA
0
--
--
ns
tRC (2)
--
--
ns
SYMBOL
VDR
(3)
ICCDR
PARAMETER
TEST CONDITIONS
Chip Deselect to Data
Retention Time
tCDR
See Retention Waveform
tR
Operation Recovery Time
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCDR(Max.) is 0.7uA at TA=70OC.
4. 48B BGA ignore CE2 condition
n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
VCC
VDR≧1.5V
VCC
tCDR
tR
CE≧VCC - 0.2V
VIH
CE
VCC
VIH
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
VDR≧1.5V
VCC
VCC
tCDR
VCC
tR
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
0.5Vcc
Output Load
WAVEFORM
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
Others
CL = 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
CL(1)
VCC
GND
90%
10%
→ ←
Rise Time:
1V/ns
90%
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
WILL BE CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
10%
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
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2006
BS616LV2019
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O
n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
CYCLE TIME : 55ns
(VCC=2.7~3.6V)
MIN. TYP. MAX.
DESCRIPTION
CYCLE TIME : 70ns
(VCC=2.4~3.6V)
MIN. TYP. MAX.
UNITS
tAVAX
tRC
Read Cycle Time
55
--
--
70
--
--
ns
tAVQX
tAA
Address Access Time
--
--
55
--
--
70
ns
tELQV1
tACS1
Chip Select Access Time
(CE)
--
--
55
--
--
70
ns
tELQV2
tACS2
Chip Select Access Time
(CE2)
--
--
55
--
--
70
ns
tBLQV
tBA
Data Byte Control Access Time
(LB, UB)
--
--
55
--
--
70
ns
tGLQV
tOE
Output Enable to Output Valid
--
--
30
--
--
35
ns
tELQX1
tCLZ1
Chip Select to Output Low Z
(CE)
10
--
--
10
--
--
ns
tELQX2
tCLZ2
Chip Select to Output Low Z
(CE2)
10
--
--
10
--
--
ns
tBLQX
tBE
Data Byte Control to Output Low Z
(LB, UB)
10
--
--
10
--
--
ns
tGLQX
tOLZ
Output Enable to Output Low Z
5
--
--
5
--
--
ns
tEHQZ1
tCHZ1
Chip Select to Output High Z
(CE)
--
--
30
--
--
35
ns
tEHQZ2
tCHZ2
Chip Select to Output High Z
(CE2)
--
--
30
--
--
35
ns
tBHQZ
tBDO
Data Byte Control to Output High Z (LB, UB)
--
--
30
--
--
35
ns
tGHQZ
tOHZ
Output Enable to Output High Z
--
--
25
--
--
30
ns
tAVQX
tOH
Data Hold from Address Change
10
--
--
10
--
--
ns
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
tRC
ADDRESS
tOH
tAA
tOH
DOUT
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BS616LV2019
READ CYCLE 2
(1,3,4)
CE
tACS1
CE2
(6)
tACS2
tCLZ
tCHZ
(5,6)
(5, 6)
DOUT
READ CYCLE 3
(1, 4)
tRC
ADDRESS
tAA
OE
tOH
tOE
tOLZ
CE
tACS1
CE2
tOHZ
(5)
tACS2(6)
tCLZ
(5,6)
tCHZ
(1,5,6)
tBA
LB, UB
tBE
tBDO
DOUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
6. 48B BGA ignore this parameters related to CE2.
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2006
BS616LV2019
O
O
n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C)
WRITE CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
DESCRIPTION
CYCLE TIME : 55ns
(VCC=2.7~3.6V)
CYCLE TIME : 70ns
(VCC=2.4~3.6V)
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
tAVAX
tWC
Write Cycle Time
55
--
--
70
--
--
ns
tAVWL
tAS
Address Set up Time
0
--
--
0
--
--
ns
tAVWH
tAW
Address Valid to End of Write
55
--
--
70
--
--
ns
tELWH
tCW
Chip Select to End of Write
55
--
--
70
--
--
ns
tBLWH
tBW
Data Byte Control to End of Write
25
--
--
30
--
--
ns
tWLWH
tWP
Write Pulse Width
30
--
--
35
--
--
ns
tWHAX1
tWR1
Write Recovery Time
(CE, WE)
0
--
--
0
--
--
ns
tWHAX2
tWR2
Write Recovery Time
(CE2)
0
--
--
0
--
--
ns
tWLQZ
tWHZ
Write to Output High Z
--
--
25
--
--
30
ns
tDVWH
tDW
Data to Write Time Overlap
25
--
--
30
--
--
ns
tWHDX
tDH
Data Hold from Write Time
0
--
--
0
--
--
ns
tGHQZ
tOHZ
Output Disable to Output in High Z
--
--
25
--
--
30
ns
tWHQX
tOW
End of Write to Output Active
5
--
--
5
--
--
ns
(LB, UB)
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1
(1)
tWC
ADDRESS
OE
CE
(5)
CE2
(5,12)
tCW
(11)
tCW
(11)
tWR1
(3)
tWR2
tBW
(3)
LB, UB
tAW
WE
tWP
tAS
tOHZ
(2)
(4,10)
DOUT
tDH
tDW
DIN
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BS616LV2019
WRITE CYCLE 2
(1,6)
tWC
ADDRESS
tCW
(5)
CE
CE2
(11)
(5,12)
tBW
(5)
LB, UB
tAW
tWP
WE
tAS
tWHZ
tWR
(2)
(4,10)
(3)
tOW
(7)
(8)
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and CE2 active and WE
low. All signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low and CE2 is high during this period, DQ pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11. tCW is measured from the later of CE going low or CE2 going high to the end of write.
12. 48B BGA ignore this parameters related to CE2.
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BS616LV2019
n ORDERING INFORMATION
BS616LV2019
X
X
Z
YY
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
D: DICE
A: BGA-48-0608
T: TSOP I-48
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
UNIT
SYMBO
L
HD
12°(2X)
1
12°(2X)
e
4
8
b
2
4
2
5
E
Seating
Plane
12°(2x)
y
"A"
D
A
A
A1
A2
b
b1
c
c1
D
E
e
HD
L
L1
y
θ
INCH
0.0433±0.004
0.004±0.002
0.039±0.002
0.009±0.002
0.008±0.001
0.004 ~ 0.008
0.004 ~ 0.006
0.645±0.004
0.472±0.004
0.020±0.004
0.708±0.008
0.0236±0.006
0.0315±
0.004 Max.
0°~8°
MM
1.10±0.10
0.10±0.05
1.00±0.05
0.22±0.05
0.20±0.03
0.10 ~ 0.21
0.10 ~ 0.16
16.40±0.10
11.80±0.10
0.50±0.10
18.00±0.20
0.60±0.15
0.80±0.10
0.1 Max.
0°~8°
A2
GAUGE PLANE
A
A1
2
4
θ
2
5
SEATING PLANE
A
12°(2x)
WITH PLATING
b
"A" DETAIL VIEW
L
L1
c c
1
BASE METAL
b1
SECTION
1
A-A
4
8
TSOP I-48 Pin
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May.
2006
BS616LV2019
n PACKAGE DIMENSIONS (continued)
NOTES
:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
1.2 Max.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
E1
e
D1
VIEW A
48 mini-BGA (6 x 8mm)
R0201-BS616LV2019
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Revision 1.3
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2006
BS616LV2019
n Revision History
Revision No.
History
Draft Date
1.2
Add Icc1 characteristic parameter
Jan. 13, 2006
1.3
Change I-grade operation temperature range
- from –25OC to –40OC
May. 25, 2006
R0201-BS616LV2019
11
Remark
Revision 1.3
May.
2006
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