Cypress CY621282BNLL-70SXE 1-mbit (128k x 8) static ram automatic power-down when deselected Datasheet

CY621282BN
MoBL Automotive

1-Mbit (128K x 8) Static RAM
Functional Description
Features
The CY621282BN[1] is a high-performance CMOS static RAM
organized as 128K words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE1), an active HIGH
Chip Enable (CE2), and active LOW Output Enable (OE). This
device has an automatic power-down feature that reduces power
consumption by more than 75% when deselected.
■
Temperature Ranges
❐ Automotive-E: –40 °C to 125 °C
■
4.5 V – 5.5 V operation
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■
Low active power
137.5 mW (max.) (25 mA)
■
Low standby power
137.5 W (max.) (25 A)
■
Automatic power-down when deselected
■
TTL-compatible inputs and outputs
■
Easy memory expansion with CE1, CE2, and OE options
■
Available in Pb-free 32-pin (450 mil-wide) small outline
integrated circuit (SOIC) package
Writing to the device is accomplished by taking Chip Enable One
(CE1) and Write Enable (WE) inputs LOW and Chip Enable Two
(CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A16).
Reading from the device is accomplished by taking Chip Enable
One (CE1) and Output Enable (OE) LOW while forcing Write
Enable (WE) and Chip Enable Two (CE2) HIGH. Under these
conditions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1 HIGH
or CE2 LOW), the outputs are disabled (OE HIGH), or during a
write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Logic Block Diagram
I/O 0
INPUT BUFFER
I/O 1
128K x 8
ARRAY
I/O 3
I/O 4
I/O 5
COLUMN
DECODER
CE1
CE2
WE
I/O 6
POWER
DOWN
I/O 7
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
OE
I/O 2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
Note
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-65526 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 6, 2011
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CY621282BN
MoBL Automotive

Contents
Product Portfolio .............................................................. 3
Pin Configuration ............................................................. 3
Pin Definition .................................................................... 3
Maximum Ratings ............................................................ 4
Operating Range .............................................................. 4
Electrical Characteristics ................................................ 4
Capacitance ...................................................................... 5
Thermal Resistance ......................................................... 5
Data Retention Characteristics ....................................... 5
Switching Characteristics ............................................... 6
Switching Waveforms ...................................................... 6
Document #: 001-65526 Rev. **
Truth Table ........................................................................ 9
Ordering Information ........................................................ 9
Ordering Code Definition ............................................. 9
Package Diagrams .......................................................... 10
Acronyms ........................................................................ 10
Document Conventions ................................................. 10
Units of Measure ....................................................... 10
Document History Page ................................................. 11
Sales, Solutions, and Legal Information ...................... 12
Worldwide Sales and Design Support ....................... 12
Products .................................................................... 12
PSoC Solutions ......................................................... 12
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CY621282BN
MoBL Automotive

Product Portfolio
CY621282BN
Automotive-E
Power Dissipation
VCC Range (V)
Product
Speed (ns)
Min
Typ
Max
4.5
5.0
5.5
[2]
Operating, ICC (mA)
Typ
70
[2]
6
Standby, ISB2 (A)
Max
Typ[2]
Max
25
2.5
25
Pin Configuration
Figure 1. Pin Configuration
Top View
SOIC
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GN
G
gnc
g
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Pin Definition
Input
A0–A16. Address inputs
Input/output
I/O0–I/O7. Data lines. Used as input or output lines depending on operation
Input/control
WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted.
Input/control
CE1. Chip Enable 1, Active LOW.
Input/control
CE2. Chip Enable 2, Active HIGH.
Input/control
OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins
Ground
GND. Ground for the device
Power supply
VCC. Power supply for the device
Note
2. Typical values are included for reference only and are not tested or guaranteed. Typical values are measured at VCC = 5.0 V, TA = 25 °C
Document #: 001-65526 Rev. **
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MoBL Automotive

DC input voltage[3,4] ............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Current into outputs (LOW) ......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static discharge voltage........................................... > 2001 V
(per MIL-STD-883, Method 3015)
Storage temperature ................................ –65 C to +150 C
Latch-up current ..................................................... > 200 mA
Ambient temperature with
power applied ........................................... –55 C to +125 C
Operating Range
Supply voltage on VCC to relative GND[3] .....–0.5 V to +7.0 V
Range
DC voltage applied to outputs
in High-Z state[3] ................................... –0.5 V to VCC + 0.5 V
Automotive-E
Ambient
Temperature
VCC
–40 C to +125 C
5 V  10%
Electrical Characteristics Over the Operating Range
Parameter
VOH
Description
Output HIGH voltage
Test Conditions
-70
Min
Typ[5]
Max
VCC =4.5 V., IOH = –1.0 mA
2.4
–
–
VCC = 5.5 V, IOH = –0.1 mA
3.95
–
–
VCC = 5 V, IOH = –0.1 mA
3.6
–
–
VCC = 4.5 V, IOH = –0.1 mA
3.25
–
–
Unit
V
VOL
Output LOW voltage
–
–
0.4
V
VIH
Input HIGH voltage
2.2
–
VCC +
0.3
V
VIL
Input LOW voltage[3]
–0.3
–
0.8
V
IIX
Input leakage current
GND  VI  VCC
–10
–
+10
A
IOZ
Output leakage
current
GND  VI  VCC,
Output Disabled
–10
+10
A
ICC
VCC operating
supply current
f = fMAX = 1/tRC
6
25
mA
f= 1 MHZ
2
12
ISB1
Automatic CE
Power-down current
—TTL inputs
VCC =5.5 V, CE1  VIH or CE2 < VIL,
VIN  VIH or VIN  VIL,
f = fMAX
–
0.1
2
mA
ISB2
Automatic CE
Power-down current
—CMOS inputs
VCC = 5.5 V, CE1  VCC – 0.3 V,
or CE2  0.3 V,
VIN  VCC – 0.3V,or VIN  0.3V, f = 0
–
2.5
25
A
VCC = 4.5 V, IOL = 2.1 mA
VCC = 5.5V,
IOUT = 0 mA
Notes
3. VIL (min.) = –2.0 V for pulse durations of less than 20 ns.
4. No input may exceed VCC + 0. 5 V.
5. Typical values are included for reference only and are not tested or guaranteed. Typical values are measured at VCC = 5.0 V, TA = 25 °C
Document #: 001-65526 Rev. **
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MoBL Automotive

Capacitance
Parameter[6]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max.
TA = 25 C, f = 1 MHz,
VCC = 5.0 V
Unit
9
pF
9
pF
Thermal Resistance
Parameter[6]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
32 pin-SOIC
Unit
66.17
C / W
30.87
C / W
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA / JESD51.
Figure 2. AC Test Loads and Waveforms
R1 1800
5V
R1 1800
5V
Output
All Input Pulses
VCC
90%
Output
R2
990
100 pF
Including
JIG and
Scope
Including
JIG and
Scope
(a)
R2
990
5 pF
90%
10%
10%
GND
Fall TIme:
1 V/ns
Rise TIme:
1 V/ns
(b)
Equivalent to:
THÉVENIN Equivalent
639
1.77 V
OUTPUT
Figure 3. Data Retention Waveform
VCC, min.
tCDR
VCC
Data Retention Mode
VDR > 2 V
VCC, min.
tR
CE1
or
CE2
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for data retention
ICCDR
Data retention current
tCDR
Chip deselect todata
retention time
Conditions
VCC = VDR = 2.0 V,
CE1 VCC – 0.3 V, or CE2  0.3 V,
VIN  VCC – 0.3 V or, VIN  0.3 V
Operation recovery time
tR
Note
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-65526 Rev. **
Min
Automotive-E
Typ
Max
Unit
2.0
–
–
V
–
1.5
25
A
0
–
–
ns
70
–
–
ns
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CY621282BN
MoBL Automotive

Switching Characteristics Over the Operating Range
Parameter[7]
CY621282BN-70
Description
Min
Max
Unit
Read Cycle
tRC
Read cycle time
70
–
ns
tAA
Address to data valid
–
70
ns
tOHA
Data hold from address change
5
–
ns
tACE
CE1 LOW to data valid, CE2 HIGH to data valid
–
70
ns
tDOE
OE LOW to data valid
–
35
ns
tLZOE
OE LOW to Low Z
0
–
ns
tHZOE
OE HIGH to High Z
[7, 9]
–
25
ns
tLZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z[9]
5
–
ns
tHZCE
CE1 HIGH to High Z, CE2 LOW to High Z
–
25
ns
tPU
CE1 LOW to Power-up, CE2 HIGH to power-up
0
–
ns
tPD
CE1 HIGH to Power-down, CE2 LOW to power-down
–
70
ns
tWC
Write cycle time
70
–
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to write end
60
–
ns
tAW
Address set-up to write end
60
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address set-up to write start
0
–
ns
tPWE
WE pulse width
50
–
ns
tSD
Data set-up to write end
30
–
ns
tHD
Data Hold from write end
0
–
ns
tLZWE
[9]
WE HIGH to Low Z
5
–
ns
tHZWE
WE LOW to High Z
[8, 9]
–
25
ns
[8, 9]
Write Cycle[10]
Switching Waveforms
Figure 4. Read Cycle No.1[11, 12]
tRC
Address
tOHA
Data Out
Previous Data Valid
tAA
Data Valid
Notes
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
11. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
12. WE is HIGH for read cycle.
Document #: 001-65526 Rev. **
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MoBL Automotive
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Switching Waveforms (continued)
Figure 5. Read Cycle No. 2 OE Controlled[13, 14]
Address
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
Data
Out
tHZCE
tLZOE
High Impedance
Data Valid
tLZCE
VCC
Supply
Current
High
Impedance
tPD
tPU
50%
50%
ICC
ISB
Figure 6. Write Cycle No. 1 CE1 or CE2 Controlled[15, 16]
tWC
Address
tSCE
CE1
CE2
tSA
tSCE
tAW
tHA
tPWE
WE
tSD
Data
I/O
tHD
Data Valid
Notes
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
15. Data I/O is high impedance if OE = VIH.
16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-65526 Rev. **
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Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 WE Controlled, OE HIGH During Write[17, 18]
tWC
Address
tSCE
CE1
CE2
tSCE
tAW
tHA
tSA
tPWE
WE
OE
tSD
Data I/O
tHD
Data IN Valid
NOTE 19
tHZOE
Figure 8. Write Cycle No.3 WE Controlled, OE LOW[17, 18]
tWC
Address
tSCE
CE1
CE2
tSCE
tAW
tSA
tHA
tPWE
WE
tSD
Data I/O
NOTE 19
tHD
Data Valid
tHZWE
tLZWE
Notes
17. Data I/O is high impedance if OE = VIH.
18. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
19. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-65526 Rev. **
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MoBL Automotive

Truth Table
CE1
CE2
OE
WE
I/O0–I/O7
Mode
Power
H
X
X
X
High Z
Power-down
Standby (ISB)
X
L
X
X
High Z
Power-down
Standby (ISB)
L
H
L
H
Data out
Read
Active (ICC)
L
H
X
L
Data in
Write
Active (ICC)
L
H
H
H
High Z
Selected, Outputs disabled
Active (ICC)
Ordering Information
Speed (ns)
70
Package
Diagram
Ordering Code
CY621282BNLL-70SXE
Package Type
51-85081
32-pin 450-Mil SOIC (Pb-free)
Operating
Range
Automotive-E
Please contact your local Cypress sales representative for availability of these parts
Ordering Code Definition
CY
621
2
82
BN
LL
70
SX
X
Temp Grade
Package Type
SX: 32-pin 450-Mil SOIC (Pb-free) SOIC
Speed Grade
Low Power
B=Technology = 250 nm
N=Nitride seal mask fix
Bus Width = x8
Density = 1 M
MoBL SRAM Family
Company ID: CY = Cypress
Document #: 001-65526 Rev. **
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MoBL Automotive

Package Diagrams
32-pin (450 Mil) Molded SOIC (51-85081)
16
1
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
17
32
0.793[20.142]
0.817[20.751]
0.006[0.152]
0.012[0.304]
0.101[2.565]
0.111[2.819]
0.118[2.997]
MAX.
0.004[0.102]
0.050[1.270]
BSC.
0.047[1.193]
0.063[1.600]
0.004[0.102]
MIN.
0.023[0.584]
0.039[0.990]
0.014[0.355]
0.020[0.508]
SEATING PLANE
51-85081-*C
All product and company names mentioned in this document are the trademarks of their respective holders.
Acronyms
Document Conventions
Acronym
Description
CMOS
complementary metal oxide semiconductor
SOIC
small outline integrated circuit
I/O
input/output
SRAM
static random access memory
Document #: 001-65526 Rev. **
Units of Measure
Symbol
Unit of Measure
°C
degree Celcius
µA
micro Amperes
mA
milli Amperes
MHz
Mega Hertz
mV
milli Volts
ns
nano seconds
pF
pico Farad
V
Volts

Ohms
W
Watts
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MoBL Automotive
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Document History Page
Document Title: CY621282BN MoBL Automotive 1-Mbit (128K x 8) Static RAM
Document Number: 001-65526
REV.
ECN NO.
Issue Date
Orig. of
Change
**
3115909
01/06/2011
RAME
Document #: 001-65526 Rev. **
Description of Change
New Data Sheet
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-65526 Rev. **
Revised January 6, 2011
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