Cypress CY7C1061AV33-10ZXC 16-mbit (1 m ã 16) static ram Datasheet

CY7C1061AV33
16-Mbit (1 M × 16) Static RAM
16-Mbit (1 M × 16) Static RAM
Features
Functional Description
■
High speed
❐ tAA = 10 ns
The CY7C1061AV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
■
Low active power
❐ 990 mW (max)
■
Operating voltages of 3.3 ± 0.3 V
■
2.0 V data retention
■
Automatic power down when deselected
■
TTL compatible inputs and outputs
To write to the device, enable the chip (CE1 LOW and CE2 HIGH)
while forcing the Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7),
is written into the location specified on the address pins (A0
through A19). If Byte High Enable (BHE) is LOW, then data from
I/O pins (I/O8 through I/O15) is written into the location specified
on the address pins (A0 through A19).
■
Easy memory expansion with CE1 and CE2 features
■
Available in Pb-free and non Pb-free 54-pin TSOP II package
and non Pb-free 60-ball fine-pitch ball grid array (FBGA)
package
To read from the device, enable the chip by taking CE1 LOW and
CE2 HIGH while forcing the Output Enable (OE) LOW and the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins will
appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O8 to I/O15. See Truth Table
on page 8 for a complete description of Read and Write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE1
HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE
and BLE are disabled (BHE, BLE HIGH), or a Write operation is
in progress (CE1 LOW, CE2 HIGH, and WE LOW).
Logic Block Diagram
1M x 16
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
I/O0–I/O7
I/O8–I/O15
A10
A11
A 12
A 13
A 14
A15
A16
A17
A18
A19
COLUMN
DECODER
BHE
WE
OE
BLE
Cypress Semiconductor Corporation
Document #: 38-05256 Rev. *K
•
198 Champion Court
•
CE2
CE1
San Jose, CA 95134-1709
•
408-943-2600
Revised April 11, 2011
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CY7C1061AV33
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 4
AC Test Loads and Waveforms ....................................... 4
AC Switching Characteristics ......................................... 5
Data Retention Waveform ................................................ 6
Switching Waveforms ...................................................... 6
Read Cycle No. 1 (Address Transition Controlled) ...... 6
Read Cycle No. 2 (OE Controlled) .............................. 6
Write Cycle No. 1 (CE1 or CE2 Controlled) ................ 7
Write Cycle No. 2 (WE Controlled, OE LOW) ............. 7
Write Cycle No. 3 (BHE/BLE Controlled) .................... 8
Document #: 38-05256 Rev. *K
Truth Table ........................................................................ 8
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Package Diagrams .......................................................... 10
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
Page 2 of 14
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CY7C1061AV33
Selection Guide
–10
Unit
10
ns
Commercial
275
mA
Industrial
275
Commercial/Industrial
50
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
mA
Pin Configurations [1, 2]
1
NC
2
60-ball FBGA
Top View
4
3
5
54-pin TSOP II
(Top View)
6
NC
NC
NC
NC
BLE
OE
A0
A1
A2
CE2
I/O 8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O 3
VCC
D
VCC
I/O12
NC
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15 DNU
A12
A13
WE
I/O7
G
A9
A10
A11
A19
H
A18
A8
A
I/O12
VCC
I/O13
I/O14
VSS
I/O15
A4
A3
A2
A1
A0
BHE
CE1
VCC
WE
CE2
A19
A18
A17
A16
A15
I/O0
VCC
I/O1
I/O2
VSS
I/O3
1
2
3
54
53
4
52
51
5
6
50
49
7
8
9
10
11
12
48
47
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
I/O11
VSS
I/O10
I/O9
VCC
I/O8
A5
A6
A7
A8
A9
NC
OE
VSS
DNU
BLE
A10
A11
A12
A13
A14
I/O7
VSS
I/O6
I/O5
VCC
I/O4
NC
NC
NC
NC
NC
NC
NC
Notes
1. NC pins are not connected on the die.
2. DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper operation.
Document #: 38-05256 Rev. *K
Page 3 of 14
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CY7C1061AV33
Maximum Ratings
DC Input Voltage [3] ............................. –0.5 V to VCC + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied .......................................... –55 C to +125 C
Range
Supply Voltage on VCC to Relative GND [3] ..–0.5 V to +4.6 V
Commercial
VCC
0 C to +70 C
3.3 V  0.3 V
–40 C to +85 C
Industrial
DC Voltage Applied to Outputs
in High Z State [3] ................................. –0.5 V to VCC + 0.5 V
Ambient
Temperature
DC Electrical Characteristics
(Over the Operating Range)
Parameter
Description
–10
Test Conditions
VOH
Output HIGH Voltage
IOH = –4.0 mA
IOL = 8.0 mA
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage [3]
IIX
Input Leakage Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply Current
VCC = max, f = fmax = 1/tRC
Min
Max
2.4
–
Unit
V
–
0.4
V
2.0
VCC + 0.3
V
–0.3
0.8
V
–1
+1
A
–1
+1
A
Commercial
–
275
mA
Industrial
–
275
mA
–
70
mA
–
50
mA
ISB1
Automatic CE Power-down
Current —TTL Inputs
CE2 < VIL, Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fmax
ISB2
Automatic CE Power-down
Current —CMOS Inputs
CE2 < 0.3 V, Max VCC,
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V,
or VIN < 0.3 V, f = 0
Commercial/
Industrial
Capacitance [4]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TSOP II
TA = 25 C, f = 1 MHz, VCC = 3.3 V
FBGA
Unit
6
8
pF
8
10
pF
AC Test Loads and Waveforms [5]
50 
VTH = 1.5 V
OUTPUT
Z0 = 50 
(a)
30 pF* * Capacitive Load consists of all
components of the test environment.
3.3 V
GND
R1 317 
3.3 V
OUTPUT
5 pF*
ALL INPUT PULSES
90%
90%
R2
351
INCLUDING
JIG AND
SCOPE
(b)
10%
10%
Rise time > 1 V/ns
(c)
Fall time:
> 1 V/ns
Notes
3. VIL (min) = –2.0 V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). As soon as 1 ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
Document #: 38-05256 Rev. *K
Page 4 of 14
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CY7C1061AV33
AC Switching Characteristics
(Over the Operating Range) [6]
Parameter
–10
Description
Min
Max
Unit
Read Cycle
tpower
VCC(typical) to the first access [7]
1
–
ms
tRC
Read Cycle Time
10
–
ns
tAA
Address to Data Valid
–
10
ns
tOHA
Data Hold from Address Change
3
–
ns
tACE
CE1 LOW/CE2 HIGH to Data Valid
–
10
ns
tDOE
OE LOW to Data Valid
–
5
ns
tLZOE
OE LOW to Low Z
1
–
ns
tHZOE
OE HIGH to High Z
[8]
–
5
ns
tLZCE
CE1 LOW/CE2 HIGH to Low Z
[8]
3
–
ns
tHZCE
CE1 HIGH/CE2 LOW to High Z [8]
–
5
ns
0
–
ns
–
10
ns
tPU
CE1 LOW/CE2 HIGH to Power Up
[9]
[9]
tPD
CE1 HIGH/CE2 LOW to Power Down
tDBE
Byte Enable to Data Valid
–
5
ns
tLZBE
Byte Enable to Low Z
1
–
ns
Byte Disable to High Z
–
5
ns
tWC
Write Cycle Time
10
–
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
7
–
ns
tAW
Address Setup to Write End
7
–
ns
tHA
Address Hold from Write End
0
–
ns
tSA
Address Setup to Write Start
0
–
ns
tPWE
WE Pulse Width
7
–
ns
tSD
Data Setup to Write End
5.5
–
ns
tHD
Data Hold from Write End
tHZBE
Write Cycle
[10, 11]
0
–
ns
tLZWE
WE HIGH to Low Z
[8]
3
–
ns
tHZWE
WE LOW to High Z [8]
–
5
ns
tBW
Byte Enable to End of Write
7
–
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the AC Test Loads and Waveforms [5] on page 4, unless
specified otherwise.
7. This part has a voltage regulator that steps down the voltage from 3 V to 2 V internally. tpower time must be provided initially before a Read/Write operation is started.
8. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms [5] on page 4.
Transition is measured 200 mV from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading
edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05256 Rev. *K
Page 5 of 14
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CY7C1061AV33
Data Retention Waveform
DATA RETENTION MODE
3.0 V
VCC
3.0 V
VDR > 2 V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [12, 13]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [13, 14]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
12. Device is continuously selected. OE, CE, BHE or BHE, or both = VIL. CE2 = VIH.
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
Document #: 38-05256 Rev. *K
Page 6 of 14
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CY7C1061AV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled) [15, 16]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA IO
NOTE 17
VALID DATA
tHZOE
Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tSA
tHA
tPWE
WE
tSD
DATA IO
NOTE 17
tHD
VALID DATA
tHZWE
tLZWE
Notes
15. Data IO is high impedance if OE, or BHE or BLE or both = VIH.
16. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
17. During this period, the IOs are in output state and input signals should not be applied.
Document #: 38-05256 Rev. *K
Page 7 of 14
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CY7C1061AV33
Switching Waveforms (continued)
Write Cycle No. 3 (BHE/BLE Controlled)
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
NOTE 18
DATA IO
tHD
VALID DATA
Truth Table
CE1
CE2
OE
WE
BLE
BHE
H
X
X
X
X
X
High Z
I/O0–I/O7
High Z
I/O8–I/O15
Power Down
Mode
Standby (ISB)
Power
X
L
X
X
X
X
High Z
High Z
Power Down
Standby (ISB)
L
H
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
H
L
H
L
H
Data Out
High Z
Read Lower Bits Only
Active (ICC)
L
H
L
H
H
L
High Z
Data Out
Read Upper Bits Only
Active (ICC)
L
H
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
H
X
L
L
H
Data In
High Z
Write Lower Bits Only
Active (ICC)
L
H
X
L
H
L
High Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Note
18. During this period, the IOs are in output state and input signals should not be applied.
Document #: 38-05256 Rev. *K
Page 8 of 14
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CY7C1061AV33
Ordering Information
The following table lists the CY7C1061AV33 key package features and ordering codes. The table contains only the parts that are
currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the
Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Speed (ns)
10
Ordering Code
CY7C1061AV33-10ZXC
Package
Diagram
51-85160
Package Type
Operating Range
54-pin TSOP II (Pb-free)
Commercial
Industrial
CY7C1061AV33-10ZXI
51-85160
54-pin TSOP II (Pb-free)
CY7C1061AV33-10BAXI
51-85162
60-ball FBGA (Pb-free)
Ordering Code Definitions
CY 7 C 1 06 1
A V33 - 10 XXX X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Package Type: XXX = ZX or BAX
ZX = 54-pin TSOP II (Pb-free)
BAX = 60-ball FBGA (Pb-free)
Speed: 10 ns
V33 = Voltage range (3 V to 3.6 V)
A = 0.16 µm Technology
1 = Data width × 16-bits
06 = 16-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Document #: 38-05256 Rev. *K
Page 9 of 14
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CY7C1061AV33
Package Diagrams
Figure 1. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm), 51-85160
51-85160 *A
Document #: 38-05256 Rev. *K
Page 10 of 14
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CY7C1061AV33
Package Diagrams (continued)
Figure 2. 60-ball FBGA (8 × 20 × 1.2 mm), 51-85162
51-85162 *E
Document #: 38-05256 Rev. *K
Page 11 of 14
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CY7C1061AV33
Acronyms
Document Conventions
Acronym
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
FBGA
fine-pitch ball grid array
ns
nano seconds
I/O
input/output
V
Volts
OE
output enable
µA
micro Amperes
SRAM
static random access memory
mA
milli Amperes
TSOP
thin small-outline package
mm
milli meter
TTL
transistor-transistor logic
ms
milli seconds
WE
Write Enable
MHz
Mega Hertz
Document #: 38-05256 Rev. *K
Symbol
Unit of Measure
pF
pico Farad
mW
milli Watts
W
Watts
°C
degree Celcius

ohms
%
percent
Page 12 of 14
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CY7C1061AV33
Document History Page
Document Title: CY7C1061AV33 16-Mbit (1 M × 16) Static RAM
Document Number: 38-05256
Revision
ECN
Submission
Date
Orig. of
Change
Description of Change
**
113725
03/28/02
NSL
New Data Sheet
*A
117058
07/31/02
DFP
Removed 15-ns bin
*B
117989
08/30/02
DFP
Added 8-ns bin
Changed Icc for 8, 10, 12 bins
tpower changed from 1 s to 1 ms.
Load Cap Comment changed (for Tx line load)
tSD changed to 5.5 ns for the 10-ns bin
Changed some 8-ns bin numbers (tHZ, tDOE, tDBE)
Removed hz<lz comments from data sheet
*C
120383
11/06/02
DFP
Final data sheet
Added note 3 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd
Updated Input/Output Caps (for 48BGA only) to 8 pF/10 pF and for the
54-pin TSOP to 6/8 pF
*D
124439
2/25/03
MEG
Changed ISB1 from 100 mA to 70 mA
Shaded fBGA production ordering information
*E
492137
See ECN
NXR
Corrected Block Diagram on page #1
Removed 8 ns speed bin
Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration
Included Note #1 and 2 on page #2
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated the Ordering Information Table
*F
508117
See ECN
NXR
Updated FBGA Pin Configuration
Updated Ordering Information table
*G
877322
See ECN
VKN
Updated Ordering Information table
*H
2897049
03/22/10
KAO
Removed inactive parts from the ordering information table. Updated
package diagrams, links in Sales, Solutions and Legal Information
*I
3109147
12/13/2010
KAO
Added Ordering Code Definitions.
*J
3160428
02/02/11
PRAS
Ordering information updates.
Template and style updates.
*K
3222127
04/11/2011
PRAS
Added Acronyms and Units of Measure.
Document #: 38-05256 Rev. *K
Page 13 of 14
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CY7C1061AV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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PSoC Solutions
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psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
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© Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05256 Rev. *K
Revised April 11, 2011
Page 14 of 14
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