12A Highly Integrated SupIRBuckTM FEATURES IR3476 DESCRIPTION Input Voltage Range: 3V to 27V Output Voltage Range: 0.5V to 12V Continuous 12A Load Capability Constant On-Time Control Compensation Loop not Required Excellent Efficiency at Very Low Output Currents Programmable Switching Frequency and Soft Start Thermally Compensated Over Current Protection Power Good Output Precision Voltage Reference (0.5V, +/-1%) Enable Input with Voltage Monitoring Capability Pre-bias Start Up Thermal Shut Down Under/Over Voltage Fault Protection The IR3476 SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC voltage regulator. The onboard constant on time hysteretic controller and MOSFETs make IR3476 a space-efficient solution that delivers up to 12A of precisely controlled output voltage. Programmable switching frequency, soft start, and thermally compensated over current protection allows for a very flexible solution suitable for many different applications and an ideal choice for battery powered applications. Additional features include pre-bias startup, very precise 0.5V reference, under/over voltage shutdown, thermal protection, power good output, and enable input with voltage monitoring capability. APPLICATIONS Notebook and Desktop Computers Forced Continuous Conduction Mode Option Consumer Electronics – STB, LCD, TV, Printers Small, Low Profile 5mm x 6mm QFN Package 12V and 24V Distributed Power Systems General Purpose POL DC-DC Converters Game Consoles and Graphics Cards BASIC APPLICATION EFFICIENCY 95% Efficiency 85% 75% 19VIN 12VIN 65% 8VIN 55% 45% 0.01 Figure 1: IR3476 Basic Application Circuit 1 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 0.1 1 10 Load Current (A) Figure 2: IR3476 Efficiency 100 12A Highly Integrated SupIRBuckTM IR3476 ORDERING INFORMATION IR3476 ― Package M Tape & Reel Qty 750 Part Number IR3476MTR1PBF M 4000 IR3476MTRPBF PBF – Lead Free TR – Tape and Reel M – Package Type MARKING INFORMATION Site/Date/Marking Code Lot Code 3476M ?YWW? xxxxx Pin 1 Identifier PIN DIAGRAM JA 30o C / W J -PCB 2o C / W 2 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 12A Highly Integrated SupIRBuckTM FUNCTIONAL BLOCK DIAGRAM Figure 3: IR3476 Functional Block Diagram 3 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 IR3476 IR3476 12A Highly Integrated SupIRBuckTM TYPICAL APPLICATION +3.3V VCC +Vins R1 10K TP2 VIN TP3 FCCM C1 1uF EN TP4 EN 4 3 FCCM +Vin1s R3 200K SW1 EN / FCCM TP5 PGND -Vins ISET TP6 PGNDS TP23 +Vsws VSW U1 IR3476 13 14 15 16 L1 1.5uH 17 1 2 + C3 68uF C4 0.22uF R4 10.5K VSW C2 22uF TP20 +Vin1s VOUT TP7 VOUT 1 12 1 2 4 3 C12 0.1uF 5 TP8 VOUTS TP10 PGND TP24 +Vsws C15 open C16 open C17 open C18 open C19 open C26 open C27 open R8 2.55K R13 open 10 +Vout2s -Vout2s TP18 VOLTAGE SENSE 5 -Vdd2s -Vout1s 9 4 +Vout1s -Vout1s -Vdd1s 8 -Vdd1s -Vdd2s Vout R12 open +Vdd2s +Vins 1 +Vin1s R11 open TP19 FB +Vdd1s C24 open R7 2.80K 3 C14 open C23 open +Vdd2s -Vdd1s -Vout1s C22 open -Vins C25 1uF VCC 7 TP25 -Vin1s 6 TP15 -Vout1s 2 -Vout1s C21 1uF +Vdd1s TP17 PGND C11 open TP21 -Vsws TP26 AGND TP16 VCC C10 47uF TP9 +Vout1s TP12 VSWS +Vdd2s -Vdd2s C9 330uF +Vdd1s NC1 C8 open 5 SS +3.3V TP14 +3.3V TP22 +Vsws C7 open 3 BOOT VIN PHASE FB 8 7 IR3476 GND1 PGND C20 0.1uF PGOOD C6 open C13 open 11 6 SS ISET VCC 5 FB TP13 SS R6 open NC2 4 2 FCCM 10 3 PGOOD FF GND 2 3VCBP 1 9 C5 open R5 10K TP11 PGOOD EN +3.3V 4 R2 10K TP1 VINS VIN R14 open Figure 4: Demoboard Schematic for VOUT = 1.05V, FS = 300kHz DEMOBOARD BILL OF MATERIALS QTY REFERENCE DESIGNATOR VALUE DESCRIPTION MANUFACTURER PART NUMBER 3 1 2 1 1 1 1 C1, C21, C25 C10 C12, C20 C2 C3 C4 C9 1.00uF 47uF 0.100uF 22.0uF 68uF 0.22uF 330uF Murata TDK TDK Taiyo Yuden Panasonic Murata Sanyo GRM188R71E105KA12D C2012X5R0J476M C1608X7R1H104K EMK316BJ226ML-T EEV-FK1E680P GRM188F51H224ZA01D 2R5TPE330M9 1 L1 1.5uH Cyntec PIMB104T-1R5MS-39 3 1 1 1 1 1 1 R1, R2, R5 R3 R4 R7 R8 SW1 U1 10.0K 200K 10.5K 2.80K 2.55K Switch IR3476 capacitor, X7R, 1.00uF, 25V, 0.1, 0603 capacitor, 47uF, 6.3V, 805 capacitor, X7R, 0.100uF, 50V, 0.1, 603 capacitor, X5R, 22.0uF, 16V, 20%, 1206 capacitor, electrolytic, 68uF, 25V, 0.2, SMD capacitor, Y5V, 0.22uF, 50V, -20%, +80%, 0603 capacitor, 330uF, 2.5V, SMD inductor, ferrite, 1.5uH, 16.0A, 3.8mOhm, SMT resistor, thick film, 10.0K, 1/10W, 0.01, 0603 resistor, thick film, 200K, 1/10W, 0.01, 603 resistor, thick film, 10.5K, 1/10W, 0.01, 603 resistor, thick film, 2.80K, 1/10W, 0.01, 603 resistor, thick film, 2.55K, 1/10W, 0.01, 0603 switch, DIP, SPST, 2 position, SMT 5mm x 6mm QFN KOA KOA KOA KOA KOA C&K Components IRF RK73H1J1002F RK73H1JLTD2003F RK73H1JLTD1052F RK73H1JLTD2801F RK73H1J2551F SD02H0SK IR3476MTRPBF 4 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 12A Highly Integrated SupIRBuckTM IR3476 PIN DESCRIPTIONS PIN # PIN NAME I/O LEVEL PIN DESCRIPTION 1 FCCM 3.3V 2 ISET 3 PGOOD 5V 4, 17 GND Reference 5 FB 3.3V Inverting input to PWM comparator, OVP / PGOOD sense. 6 SS 3.3V Soft start/shutdown. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to GND to set the startup time of the output voltage. The converter can be shutdown by pulling this pin below 0.3V. Forced Continuous Conduction Mode (CCM). Ground this pin to enable diode emulation mode or discontinuous conduction mode (DCM). Pull this pin to 3.3V to operate in CCM under all load conditions. Connecting resistor to PHASE pin sets over current trip point. 7 NC - 8 3VCBP 3.3V 9 NC - Power good open drain output – pull up with a resistor to 3.3V Bias return and signal reference. For internal LDO. Bypass with a 1.0µF capacitor to GND. - 10 VCC 5V 11 PGND Reference 12 PHASE VIN Phase node (or switching node) of MOSFET half bridge. 13 VIN VIN Input voltage for the system. 14 BOOT VIN + VCC Bootstrapped gate drive supply – connect a capacitor to PHASE. 15 FF VIN Input voltage feed forward – sets on-time with a resistor to VIN. 16 EN 5V Enable pin to turn on and off the device. Use two external resistors to set the turn on threshold (see Electrical Specifications) for input voltage monitoring. 5 VCC input. Gate drive supply. A minimum of 1.0µF ceramic capacitor is required. Power return. August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 12A Highly Integrated SupIRBuckTM IR3476 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. VIN, FF -0.3V to 30V VCC, PGOOD, EN -0.3V to 8V BOOT -0.3V to 38V PHASE -0.3V to 30V (DC), -5V (100ns) BOOT to PHASE -0.3V to 8V ISET -0.3V to 30V, 30mA PGND to GND -0.3V to +0.3V All other pins -0.3V to 3.9V Storage Temperature Range -65°C to 150°C Junction Temperature Range -40°C to 150°C ESD Classification JEDEC Class 1C Moisture Sensitivity Level JEDEC Level 2 @ 260°C (Note 2) 6 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 IR3476 12A Highly Integrated SupIRBuckTM ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN UNITS SYMBOL MIN MAX Recommended VIN Range VIN 3 27* Recommended VCC Range VCC 4.5 5.5 Recommended Output Voltage Range VOUT 0.5 12 Recommended Output Current Range IOUT 0 12 A Recommended Switching Frequency FS N/A 750 kHz Recommended Operating Junction Temperature TJ -40 125 °C V * PHASE pin must not exceed 30V. ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specifications apply over VIN = 12V, 4.5V < VCC < 5.5V, 0°C ≤ TJ ≤ 125°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT 0.495 0.5 0.505 V 280 300 320 ns 500 580 ns 8 10 12 µA -4.5 -2.5 0 mV 0.01 0.2 µA Control Loop Reference Accuracy On-Time Accuracy VREF VFB = 0.5V RFF = 180K, TJ = 65°C Min. Off Time Soft-Start Current EN = High DCM Comparator Offset Measure at VPHASE Feedback Input Current VFB = 0.5V, TA = 25°C, Note 1 Supply Current VCC Supply Current (standby) EN = Low, No Switching 23 µA VCC Supply Current (dynamic) EN = High, FS = 300kHz 8 mA FF Shutdown Current EN = Low, RFF = 180K 2 µA Forced Continuous Conduction Mode (FCCM) FCCM Start Threshold 2 V FCCM Stop Threshold 0.6 V 30 ns Gate Drive Deadtime Monitor body diode conduction on PHASE pin, Note 1 5 Bootstrap PFET Forward Voltage I(BOOT) = 10mA 300 mV VCC = 5V, ID = 12A, TJ = 25°C 20 25 mΩ VCC = 5V, ID = 12A, TJ = 25°C 10 12.5 mΩ Upper MOSFET Static Drain-to-Source On-Resistance Lower MOSFET Static Drain-to-Source On-Resistance 7 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 IR3476 12A Highly Integrated SupIRBuckTM PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT 17 19 21 µA Fault Protection ISET Pin Output Current On the basis of 25°C ISET Pin Output Current Temperature Coefficient On the basis of 25°C, Note 1 Under Voltage Threshold Falling VFB & Monitor PGOOD Under Voltage Hysteresis Rising VFB, Note 1 Over Voltage Threshold Rising VFB & Monitor PGOOD Over Voltage Hysteresis Falling VFB, Note 1 VCC Turn-on Threshold -40°C to 125°C VCC Turn-off Threshold 4400 0.37 0.43 7.5 0.586 0.625 0.655 -40°C to 125°C 3.9 4.2 4.5 V 3.6 3.9 4.2 V 1.1 EN Hysteresis 1.25 mV 1.45 400 EN Input Current EN = 3.3V PGOOD Pull Down Resistance PGOOD Delay Threshold 25 VSS Thermal Shutdown Threshold Note 1 Thermal Shutdown Threshold Hysteresis Note 1 125 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 V mV 15 µA 50 Ω 1 V 140 °C 20 °C Guaranteed by design but not tested in production Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2). Products with prior date code of 1227 are qualified with MSL3 for Consumer Market. 8 V mV 300 EN Rising Threshold V mV 7.5 VCC Threshold Hysteresis Note: 1. 2. 0.4 ppm/ °C IR3476 12A Highly Integrated SupIRBuckTM TYPICAL OPERATING DATA o 95% 100% 85% 90% 75% Efficiency Efficiency Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25 C, no airflow, unless otherwise specified. 19VIN 12VIN 65% 8VIN 80% VOUT = 1.5V; L = 2.2µH, 4.6mΩ VOUT = 3.3V; L = 3.3µH, 7.7mΩ 60% 55% 45% 0.01 0.1 1 10 Load Current (A) 50% 0.01 100 Figure 5: Efficiency vs. Load Current for VOUT = 1.05V 400 1400 350 1200 300 1000 250 200 150 50 200 0 6 9 5.0 Vout 4.0 3.0 2.0 1.0 Figure 7: Switching Frequency vs. Load Current Figure 8: RFF vs. Switching Frequency 1.060 1.060 19VIN 12VIN Output Voltage (V) Output Voltage (V) 4.5 3.5 2.5 1.5 0.5 0 200 250 300 350 400 450 500 550 600 650 700 750 Switching Frequency (kHz) 12 Load Current (A) 1.058 100 600 400 3 1 10 Load Current (A) 800 100 0 0.1 Figure 6: Efficiency vs. Load Current for VIN = 12V RFF (kOhm) Switching Frequency (kHz) VOUT = 1.05V; L = 1.5µH, 3.8mΩ 70% 8VIN 1.056 1.054 1.052 1.058 1.056 1.054 1.052 1.050 1.050 0 2 4 6 8 Load Current (A) 10 12 Figure 9: Load Regulation 9 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 8 9 10 11 12 13 14 15 16 17 18 19 Input Voltage (V) Figure 10: Line Regulation at IOUT = 12A IR3476 12A Highly Integrated SupIRBuckTM TYPICAL OPERATING DATA o Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25 C, no airflow, unless otherwise specified. EN EN PGOOD PGOOD SS SS VOUT VOUT 5V/div 5V/div 1V/div 500mV/div 5ms/div 5V/div 5V/div 1V/div 500mV/div Figure 11: Startup 500µs/div Figure 12: Shutdown VOUT VOUT PHASE PHASE iL iL 20mV/div 5V/div 5A/div 10µs/div 20mV/div 5V/div 10A/div Figure 13: DCM (IOUT = 0.1A) 2µs/div Figure 14: CCM (IOUT = 12A) PGOOD PGOOD SS FB VOUT VOUT iL iL 5V/div 1V/div 1V/div 10A/div 2ms/div 5V/div 1V/div Figure 15: Over Current Protection (tested by shorting VOUT to PGND) 10 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 500mV/div 2A/div 50µs/div Figure 16: Over Voltage Protection (tested by shorting FB to VOUT) IR3476 12A Highly Integrated SupIRBuckTM TYPICAL OPERATING DATA o Tested with demoboard shown in Figure 4, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25 C, no airflow, unless otherwise specified. VOUT VOUT PHASE PHASE iL iL 50mV/div 10V/div 5A/div 20µs/div 50mV/div 10V/div 5A/div Figure 17: Load Transient 0-8A 20µs/div Figure 18: Load Transient 4-12A FCCM FCCM PHASE PHASE VOUT VOUT iL iL 5V/div 10V/div 500mV/div 5A/div 10µs/div 2V/div 10V/div 500mV/div 5A/div 5µs/div Figure 19: DCM/FCCM Transition Figure 20: FCCM/DCM Transition Figure 21: Thermal Image at VIN = 12V, IOUT = 12A o o o (IR3476: 98 C, Inductor: 58 C, PCB: 47 C) Figure 22: Thermal Image at VIN = 19V, IOUT = 12A o o o (IR3476: 104 C, Inductor: 61 C, PCB: 50 C) 11 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 12A Highly Integrated SupIRBuckTM THEORY OF OPERATION PWM COMPARATOR The PWM comparator initiates a SET signal (PWM pulse) when the FB pin falls below the reference (VREF) or the soft start (SS) voltage. ON-TIME GENERATOR The PWM on-time duration is programmed with an external resistor (RFF) from the input supply (VIN) to the FF pin. The simplified equation for RFF is shown in equation 1. The FF pin is held to an internal reference after EN goes HIGH. A copy of the current in RFF charges a timing capacitor, which sets the on-time duration, as shown in equation 2. RFF VOUT (1) 1V 20 pF FSW TON RFF 1V 20 pF (2) VIN CONTROL LOGIC The control logic monitors input power sources, sequences the converter through the soft-start and protective modes, and initiates an internal RUN signal when all conditions are met. IR3476 reaches VSS (see Electrical Specification), SS_DELAY goes HIGH. With EN_DELAY = LOW, the capacitor voltage and SS pin is held to the FB pin voltage. A normal startup sequence is shown in Figure 23. PGOOD The PGOOD pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. The PGOOD logic monitors EN_DELAY, SS_DELAY, and under/over voltage fault signals. PGOOD is released only when EN_DELAY and SS_DELAY = HIGH and output voltage is within the OV and UV thresholds. PRE-BIAS STARTUP IR3476 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. With constant on-time control, the output voltage is compared with the soft start voltage (SS) or Vref, depending on which one is lower, and will not start switching unless the output voltage drops below the reference. This scheme prevents discharge of a pre-biased output voltage. SHUTDOWN The IR3476 will shutdown if VCC is below its UVLO limit. The IR3476 can be shutdown by pulling the EN pin below its lower threshold. Alternatively, the output can be shutdown by pulling the soft start pin below 0.3V. VCC and 3VCBP pins are continuously monitored, and the IR3476 will be disabled if the voltage of either pin drops below the falling thresholds. EN_DELAY will become HIGH when VCC and 3VCBP are in the normal operating range and the EN pin = HIGH. SOFT START With EN = HIGH, an internal 10µA current source charges the external capacitor (CSS) on the SS pin to set the output voltage slew rate during the soft start interval. The soft start time (tSS) can be calculated from equation 3. t SS C SS 0.5V (3) 10A The feedback voltage tracks the SS pin until SS reaches the 0.5V reference voltage (Vref), then feedback is regulated to Vref. CSS will continue to be charged, and when SS pin 12 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 Figure 23: Normal Startup 12A Highly Integrated SupIRBuckTM UNDER/OVER VOLTAGE MONITOR The IR3476 monitors the voltage at the FB node through a 350ns filter. If the FB voltage is below the under voltage threshold, UV# is set to LOW holding PGOOD to be LOW. If the FB voltage is above the over voltage threshold, OV# is set to LOW, the shutdown signal (SD) is set to HIGH, MOSFET gates are turned off, and PGOOD signal is pulled low. Toggling VCC or EN will allow the next start up. Figure 24 and 25 show PGOOD status change when UV/OV is detected. The over voltage and under voltage thresholds can be found in the Electrical Specification section. IR3476 MOSFET, VPHASE, is monitored for over current and zero crossing. The OCP circuit evaluates VPHASE for an over current condition typically 270ns after the lower MOSFET is gated on. This delay functions to filter out switching noise. The minimum lower gate interval allows time to sample VPHASE. The over current trip point is programmed with a resistor from the ISET pin to PHASE pin, as shown in equation 4. When over current is detected, the MOSFET gates are tristate and SS voltage is pulled to 0V. This initiates a new soft start cycle. If there is a total of four OC events, the IR3476 will disable switching. Toggling VCC or EN will allow the next start up. RSET RDSON IOC 19 A (4) * typical filter delay Figure 24: Under/Over Voltage Monitor Figure 26: Over Current Protection UNDER VOLTAGE LOCK-OUT * typical filter delay Figure 25: Over Voltage Protection OVER CURRENT MONITOR The over-current circuitry monitors the output current during each switching cycle. The voltage across the lower 13 The IR3476 has VCC and EN under voltage lock-out (UVLO) protection. When either VCC or EN is below their UVLO threshold, IR3476 is disabled. IR3476 will restart when both VCC and EN are above their UVLO thresholds. OVER TEMPERATURE PROTECTION When the IR3476 exceeds its over temperature threshold, the MOSFET gates are tri-state and PGOOD is pulled low. Switching resumes once temperature drops below the over temperature hysteresis level. August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 12A Highly Integrated SupIRBuckTM GATE DRIVE LOGIC The gate drive logic features adaptive dead time, diode emulation, and a minimum lower gate interval. An adaptive dead time prevents the simultaneous conduction of the upper and lower MOSFETs. The lower gate voltage must be below approximately 1V after PWM goes HIGH before the upper MOSFET can be gated on. Also, the differential voltage between the upper gate and PHASE must be below approximately 1V after PWM goes LOW before the lower MOSFET can be gated on. The upper MOSFET is gated on after the adaptive delay for PWM = HIGH and the lower MOSFET is gated on after the adaptive delay for PWM = LOW. When FCCM = LOW, the lower MOSFET is driven ‘off’ when the ZCROSS signal indicates that the inductor current is about to reverse direction. The ZCROSS comparator monitors the PHASE voltage to determine when to turn off the lower MOSFET. The lower MOSFET stays ‘off’ until the next PWM falling edge. When the lower peak of the inductor current is above zero, IR3476 operates in continuous conduction mode. The continuous conduction mode can also be selected for all load current levels by pulling FCCM to HIGH. Whenever the upper MOSFET is turned ‘off’, it stays ‘off’ for the Min Off Time denoted in the Electrical Specifications. This minimum duration allows time to recharge the bootstrap capacitor and allows the over current monitor to sample the PHASE voltage. COMPONENT SELECTION Selection of components for the converter is an iterative process which involves meeting the specifications and tradeoffs between performance and cost. The following sections will guide one through the process. IR3476 capacitor, the magnitude of the AC voltage ripple is determined by the total inductor ripple current flowing through the total equivalent series resistance (ESR) of the output capacitor bank. One can use equation 5 to find the required inductance. ΔI is defined as shown in Figure 27. The main advantage of small inductance is increased inductor current slew rate during a load transient, which leads to a smaller output capacitance requirement as discussed in the Output Capacitor Selection section. The drawback of using smaller inductances is increased switching power loss in the upper MOSFET, which reduces the system efficiency and increases the thermal dissipation. ΔI TON VIN VOUT (5) 2L Figure 27: Typical Input Current Waveform Input Capacitor Selection The main function of the input capacitor bank is to provide the input ripple current and fast slew rate current during the load current step up. The input capacitor bank must have adequate ripple current carrying capability to handle the total RMS current. Figure 27 shows a typical input current. Equation 6 shows the RMS input current. The RMS input current contains the DC load current and the inductor ripple current. As shown in equation 5, the inductor ripple current is unrelated to the load current. The maximum RMS input current occurs at the maximum output current. The maximum power dissipation in the input capacitor equals the square of the maximum RMS input current times the input capacitor’s total ESR. Ts IIN_RMS Inductor Selection Inductor selection involves meeting the steady state output ripple requirement, minimizing the switching loss of the upper MOSFET, meeting transient response specifications and minimizing the output capacitance. The output voltage includes a DC voltage and a small AC ripple component due to the low pass filter which has incomplete attenuation of the switching harmonics. Neglecting the inductance in series with the output 14 1 f 2 t dt Ts 0 2 1 ΔI IOUT TON Fs 1 (6) 3 IOUT The voltage rating of the input capacitor needs to be greater than the maximum input voltage because of high frequency ringing at the phase node. The typical percentage is 25%. August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 IR3476 12A Highly Integrated SupIRBuckTM Output Capacitor Selection Selection of the output capacitor requires meeting voltage overshoot requirements during load removal, and meeting steady state output ripple voltage requirements. The output capacitor is the most expensive converter component and increases the overall system cost. The output capacitor decoupling in the converter typically includes the low frequency capacitor, such as Specialty Polymer Aluminum, and mid frequency ceramic capacitors. The first purpose of output capacitors is to provide current when the load demand exceeds the inductor current, as shown in Figure 28. Equation 7 shows the charge requirement for a certain load step. The advantage provided by the IR3476 at a load step is the reduced delay compared to a fixed frequency control method. If the load increases right after the PWM signal goes low, the longest delay will be equal to the minimum lower gate on-time as shown in the Electrical Specifications section. The IR3476 also reduces the inductor current slew time, the time it takes for the inductor current to reach equality with the output current, by increasing the switching frequency up to 1/(TON + Min Off Time). This results in reduced recovery time. Load Current The second purpose of the output capacitor is to minimize the overshoot of the output voltage when the load decreases as shown in Figure 29. By using the law of energy before and after the load removal, equation 8 shows the output capacitance requirement for a load step down. VOS VOUT VL VDROP VESR Figure 29: Typical Output Voltage Response Waveform COUT L ISTEP 2 (8) VOS 2 VOUT 2 The boot capacitor starts the cycle fully charged to a voltage of VB(0). Cg equals 0.58nF in IR3476. Choose a sufficiently small ΔV such that VB(0)-ΔV exceeds the maximum gate threshold voltage to turn on the upper MOSFET. Output Inductor Slew Rate V (0) C BOOT C g B 1 (9) ΔV t Δt ISTEP IOUT Boot Capacitor Selection I STEP Charge VESR is usually much greater than VESL. The IR3476 requires a total ESR such that the ripple voltage at the FB pin is greater than 7mV. Figure 28: Charge Requirement during Load Step Q C V 0.5 ISTEP t COUT (7a) 1 L ISTEP 2 (7b) VDROP 2 VIN VOUT 1 The output voltage drop, VDROP, initially depends on the characteristic of the output capacitor. VDROP is the sum of the equivalent series inductance (ESL) of the output capacitor times the rate of change of the output current and the ESR times the change of the output current. 15 Choose a boot capacitor value larger than the calculated CBOOT in equation 9. Equation 9 is based on charge balance at CCM operation. Usually the boot capacitor will be discharged to a much lower voltage when the circuit is operating in DCM mode at light load, due to much longer lower MOSFET off time and the bias current drawn by the IC. Boot capacitance needs to be increased if insufficient turn-on of the upper MOSFET is observed at light load, typically larger than 0.1µF is needed. The voltage rating of this part needs to be larger than VB(0) plus the desired derating voltage. It’s ESR and ESL needs to be low in order to allow it to deliver the large current and di/dt’s which drive MOSFETs most efficiently. In support of these requirements a ceramic capacitor should be chosen. August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 12A Highly Integrated SupIRBuckTM DESIGN EXAMPLE DESIGN CRITERIA Input Voltage, VIN = 6V to 21V Output Voltage, VOUT = 1.25V Switching Frequency, Fs = 400kHz Inductor Ripple Current, 2ΔI = 3A Maximum Output Current, IOUT = 12A Over Current Trip, IOC = 18A Overshoot Allowance, VOS = VOUT + 50mV Undershoot Allowance, VDROP = 50mV Find RFF: 1.25V 156 k 1V 20 pF 400kHz Pick a standard value 158 kΩ, 1% resistor. Find RSET: 10m 18 A RSET 19A 2ΔI 9.5k Find a resistive voltage divider for VOUT = 1.25V: R2 VOUT 0.5V R2 R1 R2 = 1.33kΩ, R1 = 1.96 kΩ, both 1% standard resistors. Choose the soft start capacitor: Once the soft start time has chosen, such as 1000us to reach to the reference voltage, a 22nF for CSS is used to meet 1000us. Choose an inductor to meet the design specification: Choose an input capacitor: 1.25V 1 1.5 A IIN_RMS 12 A 1 2.9 A 21V 3 12 A A Panasonic 10µF (ECJ3YB1E106M) accommodates 6 Arms of ripple current at 300kHz. Due to the chemistry of multilayer ceramic capacitors, the capacitance varies over temperature and operating voltage, both AC and DC. One 10µF capacitor is recommended. In a practical solution, one 1µF capacitor is required along with 10µF. The purpose of the 1µF capacitor is to suppress the switching noise and deliver high frequency current. VOUT VIN VOUT VIN 2ΔI Fs 1.25V 21V - 1.25V 21V 3 A 400kHz 1.0H To meet the undershoot and overshoot specification, equations 7b and 8 will be used to calculate the minimum output capacitance. As a result, 200μF will be needed for 5A load removal. To meet the stability requirement, choose an output capacitor with ESR larger than 6mΩ. Combine those two requirements, one can choose a set of output capacitors from manufactures such as SP-Cap (Specialty Polymer Capacitor) from Panasonic or POSCAP from Sanyo. A 220μF (EEFSL0D221R) from Panasonic with 9mΩ ESR will meet both requirements. If an all ceramic output capacitor solution is desired, the external slope injection circuit composed of R6, C13, and C14 is required as explained in the Stability Considerations section. In this design example, we can choose C14 = 1nF and C13 = 100nF. To calculate the value of R6 with PIMB103E1R0MS-39 as our inductor: R6 L L DCR C13 1H 2.7 m 100nF 3.7k Pick a standard value for R6 = 3.74kΩ. Choose the inductor with the lowest DCR and AC power 16 1.25V 21V - 1.25V 3A 21V 1H 400kHz Choose an output capacitor: Pick a 9.53kΩ, 1% standard resistor. VFB loss as possible to increase the overall system efficiency. For instance, choose a PIMB103E-1R0MS-39 manufactured by CYNTEC. The inductance of this part is 1µH and has 2.7mΩ DCR. Ripple current needs to be recalculated using the chosen inductor. 2 Current Transient Step Size = 5A RFF IR3476 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 12A Highly Integrated SupIRBuckTM IR3476 STABILITY CONSIDERATIONS LAYOUT RECOMMENDATIONS Constant-on-time control is a fast, ripple based control scheme. Unstable operation can occur if certain conditions are not met. The system instability is usually caused by: Bypass Capacitor: A 1µF high quality ceramic capacitor should be placed on the same side as the IR3476 and connected to VCC and PGND pins directly. Switching noise coupled to FB input: This causes the PWM comparator to trigger prematurely after the 500ns minimum on-time for lower MOSFET. It will result in double or multiple pulses every switching cycle instead of the expected single pulse. Double pulsing can causes higher output voltage ripple, but in most application it will not affect operation. This can usually be prevented by careful layout of the ground plane and the FB sensing trace. Steady state ripple on FB pin being too small: The PWM comparator in IR3476 requires minimum 7mVp-p ripple voltage to operate stably. Not enough ripple will result in similar double pulsing issue described above. Solving this may require using output capacitors with higher ESR. ESR loop instability: The stability criteria of constant on-time is: ESR COUT TON 2 If ESR is too small that this criteria is violated then subharmonic oscillation will occur. This is similar to the instability problem of peak-current-mode control with D>0.5. Increasing ESR is the most effective way to stabilize the system, but the tradeoff is the larger output voltage ripple. Boot Circuit: CBOOT should be placed near the BOOT and PHASE pins to reduce the impedance when the upper MOSFET turns on. Power Stage: Figure 30 shows the current paths and their directions for the on and off periods. The on time path has low average DC current and high AC current. Therefore, it is recommended to place the input ceramic capacitor, upper, and lower MOSFET in a tight loop as shown in Figure 30. The purpose of the tight loop from the input ceramic capacitor is to suppress the high frequency (10MHz range) switching noise and reduce Electromagnetic Interference (EMI). If this path has high inductance, the circuit will cause voltage spikes and ringing, and increase the switching loss. The off time path has low AC and high average DC current. Therefore, it should be laid out with a tight loop and wide trace at both ends of the inductor. Lowering the loop resistance reduces the power loss. The typical resistance value of 1-ounce copper thickness is 0.5mΩ per square inch. Q1 System with all ceramic output capacitors: For applications with all ceramic output capacitors, the ESR is usually too small to meet the stability criteria. In these applications, external slope compensation is necessary to make the loop stable. The ramp injection circuit, composed of R6, C13, and C14, shown in Figure 4 is required. The inductor current ripple sensed by R6 and C13 is AC coupled to the FB pin through C14. C14 is usually chosen between 1 to 10nF, and C13 between 10 to 100nF. R6 should then be chosen such that L/DCR = C13*R6. 17 Q2 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 Figure 30: Current Path of Power Stage 12A Highly Integrated SupIRBuckTM IR3476 PCB METAL AND COMPONENT PLACEMENT Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large toe fillet that can be easily inspected. Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than; 0.17mm for 2 oz. Copper or no less than 0.1mm for 1 oz. Copper or no less than 0.23mm for 3 oz. Copper. Figure 31: Metal and Component Placement * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 18 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 12A Highly Integrated SupIRBuckTM IR3476 SOLDER RESIST It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignment. Figure 32: Solder Resist * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 19 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 12A Highly Integrated SupIRBuckTM IR3476 STENCIL DESIGN The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part is pushed into the solder paste. Figure 33: Stencil Design * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 20 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603 12A Highly Integrated SupIRBuckTM IR3476 PACKAGE INFORMATION Figure 34: Package Dimensions Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial Market (Note2). Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information www.irf.com 21 August 8, 2012 | ADVANCED DATASHEET | V2.1 | PD97603