3A Highly Integrated SupIRBuck® Single-Input Voltage, Synchronous Buck Regulator FEATURES IR3823 DESCRIPTION Single input voltage range from 5V to 21V Wide Input voltage range from 1.0V to 21V with external VCC bias voltage Output voltage from 0.6V to 0.86% of PVin Enhanced line/load regulation with feedforward Programmable switching frequency up to 1.5MHz Three user selectable soft-start time options Thermally compensated current limit with robust hiccup mode over current protection Synchronization to an external clock Precise reference voltage (0.6V+/-0.6%) Open-drain PGood indication Output over voltage protection The IR3823 SupIRBuck® is a 3A easy-to-use, fully integrated and highly efficient synchronous Buck regulator intended for Point-Of-Load (POL) applications. The IR3823 features programmable switching frequency from 300kHz to 1.5MHz, three selectable soft-start time options, and smooth synchronization to an external clock. The IR3823 uses voltage mode control employing a proprietary PWM modulator, allowing high control bandwidth and fast loop response with less output capacitors. The other important functions include thermally compensated over current protection, output over voltage protection and thermal shut-down, etc. The IR3823 is offered in a small 3.5mm x 3.5mm PQFN package with excellent thermal performance. Enable Input with Under-Voltage Lockout (UVLO) APPLICATIONS VCC Under-Voltage Lockout (UVLO) Enhanced Pre-bias start-up Computing Applications Integrated MOSFET drivers and Bootstrap Diode Set Top Box Applications Storage Applications Thermal shut-down -40°C to 125°C operating junction temperature 3.5mm x 3.5mm PQFN package Lead-free, Halogen-free and RoHS6 Compliant Data Center Applications Telecom Applications Distributed Point of Load Power Architectures ORDERING INFORMATION Base Part Number Package Type IR3823 IR3823 PQFN 3.5 mm x 3.5 mm PQFN 3.5 mm x 3.5 mm Standard Pack Form Quantity Tape and Reel 750 Tape and Reel 4000 Orderable Part Number IR3823MTR1PBF IR3823MTRPBF IR3823 PBF – Lead Free TR/TR1 – Tape and Reel M – PQFN Package 1 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 BASIC APPLICATION Figure 1: IR3823 Basic Application Circuit Figure 2: IR3823 Efficiency PINOUT DIAGRAM IR3823 SW PVin 12 11 10 PGnd Gnd 13 9 Gnd GND Boot 14 8 Vcc/LDO_Out 16 Enable 15 7 Gn d m 5 6 Rt /S yn c PG oo d 4 p 3 Co t 2 SS _S el ec Fb 1 Vin Figure 3: 3.5mm x 3.5mm PQFN (Top View) 2 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 BLOCK DIAGRAM 5.1V Internal LDO Vin VCC Vcc/ LDO_Out THERMAL TSD SHUT DOWN OC FAULT POR CONTROL UVcc Gnd UVcc Boot OV Comp + VREF + 0.6V - + E/A FAULT POR VCC PVin - 0.15V Vin Fb Fb HDrv POR INTL_SS VREF OV OVER VOLTAGE HDin SW GATE DRIVE LDin SS_Select SSOK SOFT START POR LDrv CONTROL VREF FAULT PGnd SEQ Enable UVEN LOGIC UVEN OC Over Current Protection POR UVcc POR Rt/Sync PGood Figure 4: Simplified Block Diagram 3 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 PIN DESCRIPTIONS PIN # PIN NAME 1 Fb 2 SS_Select 3 Comp 4,9,13, 16 Gnd 5 Rt/Sync Multi-function pin to set the switching frequency. The internal oscillator frequency is set with a resistor between this pin and Gnd. Or synchronization to an external clock by connecting this pin to the external clock signal through a diode. 6 PGood Open-drain power good indication pin. Connect a pull-up resistor from this pin to Vcc. 7 Vin 8 Vcc/LDO_Out 10 PGnd 11 SW Switch node. Connect this pin to the output inductor. 12 PVin Power stage input. 14 Boot 15 Enable 4 www.irf.com PIN DESCRIPTION Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Soft start selection pin. Three user selectable soft start time is available: 1.5ms (SS_Select=Vcc), 3ms (SS_Select=Float), 6ms (SS_Select=Gnd) Output of the error amplifier. The loop compensation network should be connected between Comp and Fb pin. Analog ground for the internal reference and the control circuitry. Input of the Internal LDO. A 1.0µFceramic capacitor should be connected between this pin and PGnd. If an external Vcc voltage is used, this pin should be shorted to Vcc pin. Output of the internal LDO and optional input of an external biased supply voltage. A minimum 2.2µF ceramic capacitor is recommended between this pin and PGnd. Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system power ground plane. Supply voltage for the high-side driver. A 100nF ceramic capacitor should be connected between this pin and SW pin. Enable pin to turn on/off the device. Connect this pin to PVin pin through a resistor divider to implement the input voltage UVLO. © 2012 International Rectifier August 1, 2013 IR3823 ABSOLUTE MAXIMUM RATINGS Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PVin, Vin to PGnd (Note 3) -0.3V to 25V Vcc/LDO_Out to PGnd (Note 3) -0.3V to 8V (Note 1) Boot to PGnd (Note 3) -0.3V to 33V SW to PGnd (Note 3) -0.3V to 25V (DC), -4V to 25V (AC, 100ns) Boot to SW -0.3V to VCC + 0.3V (Note 2) PGood, SS_Select to Gnd (Note 3) -0.3V to VCC + 0.3V (Note 2) Other Input/Output Pins to Gnd (Note 3) -0.3V to +3.9V PGnd to Gnd -0.3V to +0.3V THERMAL INFORMATION Junction to Ambient Thermal Resistance ƟjA 37.4 °C/W (Note 4) Junction to PCB Thermal Resistance Ɵj-PCB 10.1 °C/W Junction to Case Top Thermal Resistance Ɵj-CTop 120 °C/W Storage Temperature Range -55°C to 150°C Junction Temperature Range -40°C to 150°C Note 1: Vcc must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C Note 2: Must not exceed 8V Note 3: PGnd pin and Gnd pin are connected together. Note 4: ƟjA is for the test in still air with IRDC3823 evaluation board. The IRDC3823 uses a 4‐layer 2.6” x 2.2” FR4 PCB board. Each layer uses 2 oz. copper. 5 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS SYMBOL MIN MAX UNITS Input Voltage Range with External Vcc (Note 5, Note 7) PVin 1.0 21 Input Voltage Range with Internal LDO (Note 6, Note 7) Vin, PVin 5.5 21 Supply Voltage Range (Note 6) VCC 4.5 7.5 Supply Voltage Range (Note 6) Boot to SW 4.5 7.5 Output Voltage Range V0 0.6 0.86 x PVin Output Current Range I0 0 3 A Switching Frequency FS 300 1500 kHz Operating Junction Temperature TJ -40 125 °C V Note 5: Vin is connected to Vcc to bypass the internal LDO. Note 6: Vin is connected to PVin. For single‐rail applications with PVin=Vin= 4.5V‐5.5V, please refer to the application information in the section of Internal LDO and the section of Over Current Protection. Note 7: Maximum SW node voltage should not exceed 25V. ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power Stage Power Losses PLOSS PVin= Vin = 12V, Vo = 1.2V, Io = 3A, Fs = 1000kHz, L = 1.0uH, Note 8 0.6 W Top Switch RDS(ON) RDS(on)-T VBOOT -Vsw=5.1V,Io = 3A, Tj = 25°C 40 52 Bottom Switch RDS(ON) RDS(on)-B Vcc = 5.1V, Io = 3A, Tj = 25°C 26 34 260 470 mV 1 µA 1 µA Bootstrap Diode Forward Voltage SW Leakage Current Dead Band Time VD I(Boot) = 10mA ISW VSW = 0V, Enable = 0V, VFB=1V VSW = 0V, Enable = High, VFB=1V TD Note 8 180 12.5 mΩ ns Supply Current Vin Supply Current (standby) Vin Supply Current (dynamic) 6 www.irf.com Iin(Standby) Iin(Dyn) EN = Low, No Switching Vin=21V, PVin=0V EN = High, FSW =1000kHz, Vin = PVin = 16V © 2012 International Rectifier 200 10 12.5 µA mA August 1, 2013 IR3823 ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Vcc Vin(min) = 5.5V, Io = 0-25mA CLOAD = 2.2uF 4.75 5.1 5.4 V 0.4 V VCC/LDO_Out Output Voltage LDO Dropout Voltage Vcc_drop Short Circuit Current Ishort Vin=4.7V, Io=15mA, CLOAD=2.2uF Vin=7.3V, PVin=Float, Vcc=0V 70 mA 1.0 V Oscillator Rt Voltage Frequency Range Ramp Amplitude VRt Fs Vramp Ramp Offset Minimum Pulse Width Tmin(ctrl) Maximum Duty Cycle Dmax Fixed Off Time Toff Rt = 80.6kΩ 270 300 330 Rt = 23.2kΩ 900 1000 1100 Rt = 15kΩ 1350 1500 1650 Vin = 5.5V, Vin slew rate max = 1V/µs, Note 8 0.825 Vin = 12V, Vin slew rate max = 1V/µs, Note 8 1.80 Vin = 21V, Vin slew rate max = 1V/µs, Note 8 3.15 Vin=Vcc=5V, For external Vcc operation, Note 8 0.75 Note 8 0.16 Note 8 Fs = 300kHz, Vin =PVin= 12V V 86 Fsync 270 Sync Pulse Duration Tsync 100 High 3.0 ns % 200 Sync Frequency Range Sync Level Threshold Vp-p 60 Note 8 kHz 250 ns 1650 kHz 200 ns V Low 0.6 V +1 µA Error Amplifier Input Bias Current (VFB) IFB(E/A) -1 Output Sink Current Isink(E/A) 0.4 0.85 1.2 mA Isource(E/A) 4 7.5 11 mA Output Source Current Slew Rate Gain-Bandwidth Product 7 www.irf.com SR Note 8 7 12 20 V/µs GBWP Note 8 20 30 40 MHz © 2012 International Rectifier August 1, 2013 IR3823 ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 100 110 120 dB 1.7 2.0 2.3 V 100 mV Error Amplifier (Continued) DC Gain Gain Maximum Output Voltage Vmax(E/A) Minimum Output Voltage Vmin(E/A) Note 8 Reference Voltage (VREF) Feedback Voltage VFB Accuracy 0.6 V 0°C < Tj < 70°C -0.6 +0.6 -40°C < Tj < 125°C ; Note 9 -1.2 +1.2 SS_Select=VCC 0.34 0.4 0.46 SS_Select=Float 0.16 0.2 0.24 SS_Select=Gnd 0.085 0.1 0.115 40 80 uA % Soft Start Soft Start Ramp Rate SS_Select Input Bias Current SS_Select=Gnd mV/µs Power Good Power Good Turn on Threshold VPG (on) VFB rising 85 90 95 % VREF Power Good Lower Turn off Threshold VPG(lower) VFB falling 80 85 90 % VREF Power Good Turn on Delay TPG(ON)_D VFB rising, see VPG(on) Power Good Upper Turn off Threshold VPG(upper) VFB rising PGood Comparator Delay PGood Voltage Low VFB < VPG(lower) or VFB > VPG(upper) PG(voltage) 2.56 ms 115 120 125 % VREF 1 2 3.5 µs 0.5 V IPGood = -5mA Under-Voltage Lockout Vcc-Start Threshold VCC UVLO Start Vcc rising trip Level 3.9 4.1 4.3 V Vcc-Stop Threshold VCC UVLO Stop Vcc falling trip Level 3.6 3.8 4.0 V Enable-Start-Threshold Enable UVLO Start ramping up 1.14 1.2 1.26 V Enable-Stop-Threshold Enable UVLO Stop ramping down 0.95 1 1.05 Enable Leakage Current IEN_LK Enable = 3.3V 8 www.irf.com © 2012 International Rectifier 1 µA August 1, 2013 IR3823 ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 115 120 125 % VREF 1 2 3.5 µs 3.6 4.5 5.4 A Over-Voltage Protection OVP Trip Threshold OVP_Vth OVP Comparator Delay VFB rising TOVP_D Over-Current Protection Current Limit ILIMIT Hiccup Blanking Time TBLK_Hiccup Tj = 25°C, VCC=5.1V SS_Select = Vcc, Note 8 10 SS_Select = Float, Note 8 20 SS_Select = Gnd, Note 8 40 ms Over-Temperature Protection Thermal Shutdown Threshold Hysteresis Note 8 Note 8 145 °C 20 Note 8: Guaranteed by design, but not tested in production. Note 9: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. 9 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin=12V, VCC= Internal LDO, IO = 0A-3A, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3823, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. VOUT (V) FS (kHz) LOUT (µH) P/N 1.0 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.2 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.8 1000 1.2 PIMB053T-1R2MS-39 (Cyntec) 15 4.9x5.2x3.0 3.3 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1 5 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1 10 www.irf.com © 2012 International Rectifier DCR (mΩ) SIZE (mm) August 1, 2013 IR3823 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vin=VCC= External 5V, IO = 0A-3A, FS = 1000 kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3823, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. VOUT (V) FS (kHz) LOUT (µH) P/N 1.0 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.2 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.8 1000 1.2 PIMB053T-1R2MS-39 (Cyntec) 15 4.9x5.2x3.0 3.3 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1 5 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1 11 www.irf.com © 2012 International Rectifier DCR (mΩ) SIZE (mm) August 1, 2013 IR3823 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin = VCC = 5V, IO = 0A-3A, FS = 1000 kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3823, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. VOUT (V) FS (kHz) LOUT (µH) P/N 1.0 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.2 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.8 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 3.3 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 12 www.irf.com © 2012 International Rectifier DCR (mΩ) SIZE (mm) August 1, 2013 IR3823 RDS(ON) OF MOSFETS OVER TEMPERATURE AT VCC=5.1V 13 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C) 14 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C) 15 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 THEORY OF OPERATION DESCRIPTION The IR3823 SupIRBuck® is a 3A easy-to-use, fully integrated and highly efficient synchronous Buck regulator intended for Point-Of-Load (POL) applications. It includes two IR HEXFETs with low RDS(on). The bottom FET has an integrated monolithic schottky diode in place of a conventional body diode. The IR3823 provides precisely regulated output voltage programmed via two external resistors from 0.6V to 0.86×Vin. It uses voltage mode control employing a proprietary PWM modulator with input voltage feedforward. That provides excellent noise immunity, easy loop compensation design, and good line transient response. The IR3823 has an internal Low Dropout (LDO) Regulator, allowing single supply operation without resorting to an external bias supply voltage. To further improve the light load efficiency, the internal LDO can be bypassed by using an external bias supply. This mode allows the input bus voltage range extended down to 1.0V. A RC network has to be connected between the FB pin and the COMP pin to form a feedback compensator. The goal of the compensator design is to achieve a high control bandwidth with a phase margin of 45° or above. The high control bandwidth is beneficial for the loop dynamic response, which helps to reduce the number of output capacitors, the PCB size and the cost. A phase margin of 45° or higher is desired to ensure the system stability. For most applications, a gain margin of -10dB or higher is preferred to accommodate component variations and to eliminate jittering/noise. The proprietary PWM modulator in IR3823 significantly reduces the PWM jittering, allowing the control bandwidth in the range of 1/10th to 1/5th of the switching frequency. Two types of compensators are commonly used: Type II (PI) and Type III (PID), as shown in Figure 5. The selection of the compensation type is dependent on the ESR of the output capacitors. Electrolytic capacitors have relatively higher ESR. If the ESR pole is located at the frequency lower than the cross-over frequency, FC, the ESR pole will help to boost the phase margin. Thus a type II compensator can be used. For the output capacitors with lower ESR such as ceramic capacitors, type III compensation is often desired. The IR3823 features programmable switching frequency from 300kHz to 1.5MHz, three selectable soft-start time, and smooth synchronization to an external clock. The other important functions include thermally compensated over current protection, output over voltage protection, pre-bias start-up, enable with input voltage monitoring, PGood output and thermal shut-down. VOLTAGE LOOP COMPESNATION DESIGN (a) The IR3823 uses PWM voltage mode control. The output voltage of the POL, sensed by a resistor divider, is fed into an internal Error Amplifier (E/A). The output of the E/R is then compared to an internal ramp voltage to determine the pulse width of the gate signal for the control FET. The amplitude of the ramp voltage is proportional to Vin so that the bandwidth of the voltage loop remains almost constant for different input voltages. This feature is called input voltage feedfoward. It allows the feedback loop design independent of the input voltage. Please refer to the next section for more information. (b) Figure 5: Loop Compensator (a) Type II, (b) Type III 16 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 Table 1 lists the compensation selection for different types of output capacitors. For more detailed design guideline of voltage loop compensation, please refer to the application note AN-1162, “Compensation Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier”. SupBuck design tool is also available at www.irf.com providing the reference design based on user’s design requirements. function can also minimize impact on output voltage from fast Vin change. The maximum Vin slew rate is within 1V/µs. If an external bias voltage is used as Vcc, Vin pin should be connected to Vcc/LDO_out pin instead of PVin pin. Then the feedforward function is disabled. The control loop compensation might need to be adjusted. TABLE 1 RECOMMENDED COMPENSATION TYPE LOCATION OF CROSS-OVER FREQUENCY TYPE OF OUTPUT CAPACITORS Type II (PI) FLC<FESR<F0<FS/2 Type III-A (PID) FLC<F0<FESR<FS/2 Type III-B (PID) FLC<F0<FS/2<FESR Electrolytic, POS-CAP, SPCAP POS-CAP, SPCAP Ceramic COMPENSATOR Figure 6: Timing Diagram for Input Feedforward FLC is the resonant frequency of the output LC filter. It is often referred to as double pole. FLC 1 2 Lo Co FESR is the ESR zero of the output capacitor. FESR 1 2 ESR Co F0 is the cross-over frequency of the closed voltage loop and FS is the switching frequency. INPUT VOLTAGE FEEDFORWARD Input voltage feedforward is an important feature, because it can keep the converter stable and preserve its load transient performance when Vin varies in a large range. In IR3823, feedforward function is enabled when Vin pin is connected to PVin pin and Vin>5.5V. In this case, the internal low dropout (LDO) regulator is used. The PWM ramp amplitude (Vramp) is proportionally changed with Vin to maintain the ratio Vin/Vramp almost constant throughout Vin variation range (as shown in Figure 6). Thus, the control loop bandwidth and phase margin can be maintained constant. Feed-forward 17 www.irf.com © 2012 International Rectifier UNDER-VOLTAGE LOCKOUT AND POR The Under-Voltage Lockout (UVLO) circuit monitors the voltage of VCC/LDO_Output pin and the Enable pin. It assures that the MOSFET driver outputs remain off whenever either of these two signals is below the set thresholds. Normal operation resumes once both VCC/LDO_Output and En voltages rise above their thresholds. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted, the soft start sequence starts (see soft start section). ENABLE/EXTERNAL PVIN MONITOR The IR3823 has an Enable function providing another level of flexibility for start-up. The Enable pin has a precise threshold, which is internally monitored by Under-Voltage Lockout (UVLO) circuit. If the voltage at Enable pin is below its UVLO threshold, both high-side and low-side FETs are off. When Enable pin is below its UVLO, Over-Voltage Protection (OVP) is disabled, and PGood stays low. August 1, 2013 IR3823 The Enable pin should not be left floating. A pulldown resistor in the range of several kilo ohms is recommended to connect between the Enable Pin and Gnd. In addition to logical inputs, the Enable pin can be used to implement precise input voltage UVLO. As shown in Figure 7, the input of the Enable pin is derived from the PVin voltage by a set of resistive divider, R1 and R2. By selecting different divider ratios, users can program the UVLO threshold voltage. The bus voltage UVLO is a very desirable feature. It prevents the IR3823 from regulating at PVin lower than the desired voltage level. Figure 8 shows the start-up waveform with the input UVLO voltage set at 10V. INTERNAL LOW DROPOUT REGULATOR The IR3823 has an internal Low Dropout Regulator (LDO), offering a VCC voltage of 5.1V. The internal LDO is beneficial for single rail (supply) applications, where no external bias supplies will be needed. For these applications, Vin pin should be connected to PVin and VCC/LDO_Out pin is left floating as shown in Figure 9. 1.0μF and 2.2μF ceramic bypass capacitors should be placed close to Vin pin and VCC/LDO_Out pin respectively. Figure 9: Internally Biased Single-Rail Configuration When Vin drops below 5.5V, the internal LDO enters the dropout mode. Figure 10 shows the VCC/LDO_Out voltage for Vin=PVin=5V with switching frequency of 600kHz and 1500kHz respectively. Alternatively, if the input bus voltage, PVin, is in the range of 4.5V to 7.5V, VCC/LDO_Out pin can be directly connected to PVin pin to bypass the internal LDO and therefore to avoid the voltage drop on the internal LDO. This configuration is illustrated in Figure 11. Figure 7: Implementation of Input Under-Voltage Lockout (UVLO) using Enable Pin Figure 12 shows the configuration using an external VCC voltage. With this configuration, the input voltage range can be extended down to 1.0V. Please note that the input feedforward function is disabled for this configuration. The feedback compensation needs to be adjusted accordingly. Figure 8: Illustration of start-up with PVin UVLO threshold voltage of 10V. The internal soft-start is used in this case. 18 www.irf.com © 2012 International Rectifier It should be noted as the VCC voltage decreases, the efficiency and the over current limit will decrease due to the increase of RDS(ON). Please refer to the section of the over current protection for more information. August 1, 2013 IR3823 and generate the Power On Ready (POR) signal. The slew rate of the internal soft-start can be adjusted externally with SS_Select pin, as shown in Table 2. Table 2 User Selectable Soft-Start Time SS_Select Slew Rate (mV/ µs) Soft-Start Time ( ms ) Vcc Float Gnd 0.4 0.2 0.1 1.5 3 6 Figure 13 shows the waveforms during soft start. The corresponding soft-start time can be calculated as follows. Figure 10: LDO Dropout Voltage at Vin=PVin=5V Tss 0.75V 0.15V SlewRate POR 3.0V 1.5V 0.75V Figure 11: Single-Rail Configuration for 4.5V-7V inputs 0.15V Intl_SS Vout t1 t 2 t3 Figure 13: Theoretical start-up waveforms using internal soft-start Figure 12: Use External Bias Voltage . SOFT-START The IR3823 has an internal digital soft-start circuit to control the output voltage rise time, and to limit the current surge at the start-up. To ensure correct startup, the soft-start sequence initiates when the Enable and Vcc voltages rise above their UVLO thresholds 19 www.irf.com © 2012 International Rectifier It should be noted that during the soft-start, the overcurrent protection (OCP) and over-voltage protection (OVP) is enabled to protect the device for any short circuit or over voltage condition. PRE-BIAS START-UP IR3823 is able to start up into a pre-charged output smoothly, which prevents oscillations and disturbances of the output voltage. August 1, 2013 IR3823 The output starts in an asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for control MOSFET (Ctrl FET) is generated. Figure 14 shows a typical PreBias condition at start up. The gate signal of the control FET is determined by the loop compensator. The sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value. The number of these startup pulses for each step is 16 and it’s internally programmed. Figure 15 shows the series of 16x8 startup pulses. It should be noted that during pre-bias start up, PGood is not active until the first gate signal for control FET is generated. Please refer to Power Good Section for more information. Fs 19954 Rt 0.953 Where FS is in kHz, and Rt is in kΩ. Table 3 shows the different oscillator frequency and its corresponding Rt for easy reference. Table 3 Switching Frequency vs. Rt Rt (kΩ) FS (kHz) 80.6 60.4 48.7 39.2 34 29.4 26.1 23.2 21 19.1 300 400 500 600 700 800 900 1000 1100 1200 17.4 16.2 15 1300 1400 1500 OVER CURRENT PROTECTION HDRv ... 12.5% ... LDRv ... ... 25% ... 16 The over current (OC) protection is performed by sensing current through the RDS(on) of the Synchronous MOSFET. This method enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. The current limit is pre-set internally and is compensated according to the IC temperature. So at different ambient temperature, the over-current trip threshold remains almost constant. Figure 14: Pre-Bias start-up ... 87.5% ... ... 16 ... ... End of PB Figure 15: Pre-Bias startup pulses SHUTDOWN IR3823 can be shut down by pulling the Enable pin below its 1.0V threshold. Both the high side and the low side drivers will be pulled low. OPERATING FREQUENCY The switching frequency can be programmed between 300kHz – 1200kHz by connecting an external resistor from Rt pin to Gnd. Rt can be calculated as follows. 20 www.irf.com © 2012 International Rectifier Detailed operation of OCP is explained as follows. Over Current Protection circuit senses the inductor current flowing through the Synchronous MOSFET closer to the valley point. OCP circuit samples this current for 40nsec typically after the rising edge of the PWM set pulse, which has a width of 12.5% of the switching period. The PWM pulse starts at the falling edge of the PWM set pulse. This makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise are lower and helps to prevent false tripping due to noise and transient. An OC condition is detected if the load current exceeds the threshold, the converter enters August 1, 2013 IR3823 into hiccup mode. PGood will go low and the internal soft start signal will be pulled low. The converter goes into hiccup mode with some hiccup blanking time as shown in Figure 16. The convertor stays in this mode until the over load or short circuit is removed. With different SS_Select configurations, the hiccup blanking time is different. Please refer to the electrical table for details. The actual DC output current limit point will be greater than the valley point by an amount equal to approximately half of peak to peak inductor ripple current. I OCP I LIMIT i 2 IOCP= DC current limit hiccup point ILIMIT= Over current limit (Valley of Inductor Current) ∆i= Peak-to-peak inductor ripple current Figure 16: Timing Diagram for Hiccup OCP Over current limit is affected by the VCC voltage. For some single rail operations where Vin is 5V or less, the OCP limit will de-rated due to the drop of VCC voltage. Figure 17 and Figure 18 show the over current limit for two single rail applications with Vin=PVin=5V and Vin=PVin=VCC=4.5V respectively. Figure 18: OCP Limit at Vin=PVin=VCC=4.5V OVER-VOLTAGE PROTECTION (OVP) Over-voltage protection in IR3823 is achieved by comparing FB pin voltage to a pre-set threshold. OVP threshold is set at 1.2×Vref. When FB pin voltage exceeds the over voltage threshold, an over voltage trip signal asserts after 2us (typ.) delay. Then the high side drive signal HDrv is turned off immediately, PGood flags low. The sync FET remains on to discharge the output capacitor. When the VFB voltage drops below the threshold, the sync FET turns off to prevent the complete depletion of the output capacitor. After that, HDrv remains off until a reset is performed by cycling either Vcc or Enable. Figure 19 shows the timing diagram for over voltage protection. Please note that OVP comparator becomes active only when the IR3823 is enabled. Figure 19: Timing Diagram for Over Voltage Protection Figure 17:OCP Limit at Vin=PVin=5V using Internal LDO 21 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 POWER GOOD OUTPUT IR3823 continually monitors the output voltage via FB voltage. The FB voltage is an input to the window comparator with upper and lower threshold of 120% and 85% of the reference voltage respectively. PGood signal is high whenever FB voltage is within the PGood comparator window thresholds. For prebiased start-up, PGood is not active until the first gate signal of the control FET is generated. The PGood pin is open drain and it needs to be externally pulled high. High state indicates that output is in regulation. In addition, PGood is also gated by other faults including over current and over temperature. When either of the faults occurs, PGood pin will be pulled low. THERMAL SHUTDOWN Temperature sensing is provided inside IR3823. The trip threshold is typically set to 145ºC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs and resets the internal soft start. When an external clock is applied to Rt/Sync pin after the converter runs in steady state with its freerunning frequency, a transition from the free-running frequency to the external clock frequency will happen. This transition is to gradually make the actual switching frequency equal to the external clock frequency, no matter which one is higher. On the contrary, when the external clock signal is removed from Rt/Sync pin, the switching frequency is also changed to free-running gradually. In order to minimize the impact from these transitions to output voltage, a diode is recommended to add between the external clock and Rt/Sync pin, as shown in Figure 20. Figure 21 shows the timing diagram of these transitions. An internal compensation circuit is used to change the PWM ramp slope according to the clock frequency applied on Rt/Sync pin. Thus, the effective amplitude of the PWM ramp (Vramp), which is used in compensation loop calculation, has minor impact from the variation of the external synchronization signal. Automatic restart is initiated when the sensed temperature drops within the operating range. There is a 20°C hysteresis in the thermal shutdown threshold. EXTERNAL SYNCHRONIZATION IR3823 incorporates an internal phase lock loop (PLL) circuit which enables synchronization of the internal oscillator to an external clock. This function is important to avoid sub-harmonic oscillations due to beat frequency for embedded systems when multiple point-of-load (POL) regulators are used. A multi-function pin, Rt/Sync, is used to connect the external clock. If the external clock is present before the converter turns on, Rt/Sync pin can be connected to the external clock signal solely and no other resistor is needed. If the external clock is applied after the converter turns on, or the converter switching frequency needs to toggle between the external clock frequency and the internal freerunning frequency, an external resistor from Rt/Sync pin to Gnd is required to set the free-running frequency. 22 www.irf.com © 2012 International Rectifier Figure 20: Configuration of External Synchronization Synchronize to the external clock Free Running Frequency Return to freerunning freq ... SW Gradually change Gradually change ... Fs1 SYNC Fs1 Fs2 Figure 21: Timing Diagram for Synchronization to the External Clock (Fs1<Fs2 or Fs1>Fs2) August 1, 2013 IR3823 MINIMUM ON TIME CONSIDERATIONS The minimum ON time is the shortest amount of time for which Ctrl FET may be reliably turned on, and this depends on the internal timing delays. For IR3823, the worst case minimum on-time is specified as 60ns. and mid frequency range, while in high frequency range this ratio increases, thus the lower the maximum duty ratio at which IR3823 can operate. Figure 22 shows a plot of the maximum duty ratio vs. the switching frequency. Any design or application using IR3823 must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 60ns. This is necessary for the circuit to operate without jitter and pulse-skipping, which can cause high inductor current ripple and high output voltage ripple. t on Vout D Fs Vin Fs In any application that uses IR3823, the following condition must be satisfied: Figure 22: Maximum duty cycle vs. switching frequency. t on (min) t on t on(min) Vout Vin Fs , therefore, Vin Fs Vout t on (min) The minimum output voltage is limited by the reference voltage and hence Vout(min) = 0.6V. Therefore, Vin Fs Vout (min) ton (min) 0.6V 10V / s 60ns Therefore, at the maximum recommended input voltage 21V and minimum output voltage, the converter should be designed at a switching frequency that does not exceed 476 kHz. Conversely, for operation at the maximum recommended operating frequency (1.65 MHz) and minimum output voltage (0.6V). The input voltage (PVin) should not exceed 6V, otherwise pulse skipping will happen. MAXIMUM DUTY RATIO A certain off-time is specified for IR3823. This provides an upper limit on the operating duty ratio at any given switching frequency. The off-time remains at a relatively fixed ratio to switching period in low 23 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 DESIGN EXAMPLE The following example is a typical application for IR3823. The application circuit is shown in Figure 26. PVin = Vin = 12V (±10%) Vo VREF (1 RF 1 ) RF 2 RF1 and RF2 are the feedback resistor divider, as shown in Figure 23. For the selection of RF1 and RF2, please see feedback compensation section. Vo = 1.2V Io = 3A Peak-to-Peak Ripple Voltage = ±1% of Vo ∆Vo = ± 4% of Vo (for 30% Load Transient) Fs = 1MHz EXTERNAL PVIN MONITOR (INPUT UVLO) As explained in the section of Enable/External PVin monitor, the input voltage, PVin, can be monitored by connecting the Enable pin to PVin through a set of resistor divider. When PVin exceeds the desired voltage level such that the voltage at the Enable pin exceeds the Enable threshold, 1.2V, the IR3823 is turned on. The implementation of this function is shown in Figure 7. For a typical Enable threshold of VEN = 1.2 V PVin (min) R2 VEN 1.2 R1 R2 R2 R1 VEN PVin(min) VEN For the minimum input voltage PVin (min) = 9.2V, select R1=49.9kΩ, and R2=7.5kΩ. SWITCHING FREQUENCY For FS = 1MHz, select Rt = 23.2 kΩ, from Table 3. OUTPUT VOLTAGE SETTING Output voltage is set by the reference voltage and the external voltage divider connected to the FB pin. The FB pin is the inverting input of the error amplifier, which is internally referenced to 0.6V. The divider ratio is set to provide 0.6V at the FB pin when the output is at its desired value. The output voltage is defined by using the following equation: 24 www.irf.com © 2012 International Rectifier Figure 23: The output voltage is programmed through a set of feedback resistor divider BOOTSTRAP CAPACITOR SELECTION To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor, C1, as shown in Figure 24. The operation of the circuit is as follows: When the sync FET is turned on, the capacitor node connected to SW is pulled low. VCC starts to charge C1 through the internal bootstrap didoe. The voltage, Vc, across the bootstrap capacitor C1 can be calculated as VC VCC VD where VD is the forward voltage drop of the bootstrap diode. When the control FET turns on in the next cycle, the SW node voltage rises to the bus voltage, PVin. The voltage at the Boot pin becomes: VBOOT PVin VCC VD August 1, 2013 IR3823 A good quality ceramic capacitor of 0.1μF with voltage rating of at least 25V is recommended for most applications. Panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. INDUCTOR SELECTION The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor (∆i). The optimum point is usually found between 20% and 50% ripple of the output current. Figure 24: Bootstrap circuit to generate the supply voltage for the high-side driver voltage INPUT CAPACITOR SELECTION Good quality input capacitors are necessary to minimize the input ripple voltage and to supply the switch current during the on-time. The input capacitors should be selected based on the RMS value of the input ripple current and requirement of the input ripple voltage. The RMS value of the input ripple current can be calculated as follows: I RMS I o D (1 D) Where D is the duty cycle and Io is the output current. For Io=6A and D=0.1, IRMS= 0.9A The input voltage ripple is the result of the charging of the input capacitors and the voltage induced by ESR and ESL of the input capacitors. Ceramic capacitors are recommended due to their high ripple current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is suggested to use two 10μF/25V ceramic capacitors, C3216X5R1E106M, from TDK. In addition, although not mandatory, a 1x100uF, 25V SMD capacitor EEE-1EA101XP from 25 www.irf.com © 2012 International Rectifier The saturation current of the inductor is desired to be higher than the over current limit plus the inductor ripple current. An inductor with soft-saturation characteristic is recommended. For the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: PVin max Vo L iL max D ; t Fs t L ( PVin max Vo ) Vo Vin iL max Fs Where: PVinmax = Maximum input voltage V0 = Output Voltage ∆iLmax = Maximum Inductor Peak-to-Peak Ripple Current Fs = Switching Frequency ∆t = On time D = Duty Cycle Select ∆iLmax ≈ 36%×Io, then the output inductor is calculated to be 1.0μH. Select L=1.0μH, XFL4020102ME, from Coilcraft which provides a compact, low profile inductor suitable for this application. OUTPUT CAPACITOR SELECTION Output capacitors are usually selected to meet two specific requirements: (1) Output ripple voltage and August 1, 2013 IR3823 (2) load transient response. The load transient response is also greatly affected by the control bandwidth. So it is common practice to select the output capacitors to meet the requirements of the output ripple voltage first, and then design the control bandwidth to meet the transient load response. For some cases, even with the highest allowable control bandwidth, the resulting load transient response still cannot meet the requirement. The number of output capacitors then need to be increased. The voltage ripple is attributed by the ripple current charging the output capacitors, and the voltage drop due to the Equivalent Series Resistance (ESR) and the Equivalent Series Inductance (ESL). Following lists the respective peak-to-peak ripple voltages: Vo (C ) iL max 8 Co Fs Vo ( ESR ) iL max ESR Vo ( ESL ) ( PVin Vo ) ESL L FLC 1 2 Lo Co 1 2 1.0 10 6 1 18 10 6 37.5kHz The equivalent ESR zero of the output capacitors, FESR, is. FESR 1 2 ESR 1 Co 1 2 3 10 18 10 6 2.9 10 3 kHz 3 Designing crossover frequency at 1/5th of switching frequency gives F0=200 kHz. According to Table 1, Type III B compensation is selected for FLC<F0<FS/2<FESR. Type III compensator is shown below for easy reference. Where ∆iLmax is maximum inductor peak-to-peak ripple current. Good quality ceramic capacitors are recommended due to their low ESR, ESL and the small package size. It should be noted that the capacitance of ceramic capacitors are usually de-rated with the DC and AC biased voltage. It is important to use the derated capacitance value for the calculation of output ripple voltage as well as the voltage loop compensation design. The de-rated capacitance value may be obtained from the manufacturer’s datasheets. In this case, one 22uF ceramic capacitors, C2012X5R0J226M, from TDK are used to achieve ±12mV peak-to-peak ripple voltage requirement. The de-rated capacitance value with 1.2VDC bias and 10mVAC voltage is around 18uF each. FEEDBACK COMPENSATION For this design, the resonant frequency of the output LC filter, FLC, is 26 www.irf.com © 2012 International Rectifier Figure 25: Type III compensation and its asymptotic gain plot August 1, 2013 IR3823 As can be seen from Figure 25, Type III compensator contains two zeros and three poles. They can be calculated as follows. The zeros are: FZ 1 1 2 RC1 CC1 FZ 2 1 2 CF 3 ( RF 3 RF 1 ) The poles are: 1 2 RF 3 CF 3 FP 3 1 2 RC1 CC 2 1 sin 1 sin 70 200 103 35kHz 1 sin 1 sin 70 FP F0 1 sin 1 sin 70 200 103 1134kHz 1 sin 1 sin 70 To compensate the phase lag of the pole at the origin and to provide extra phase boost, the other zero can be placed at one half of the first zero, i.e. 1/FZ = 17.5 kHz. The third pole is usually placed at one half of the switching frequency to damp the switching noise. The selected compensation parameters are: RF1=4.02kΩ, RF2=4.02kΩ, RF3=127Ω, CF3=2200pF, RC1=1.0kΩ, CC1=4.7nF, CC2=56pF. The resulting zeros and poles are listed in Table 4. Please note that one of high-frequency poles has been moved to 2843 kHz to increase the phase margin. FP1 0 FP 2 FZ F0 Table 4 Zeros and Poles of the Voltage Loop Compensator Zeros 34 kHz 17 kHz Please note that the order of the zeros and poles do not necessarily follow the location shown in Figure 25. It can vary with the design preference. 0 Poles 570 kHz 2843 kHz To archive the sufficient phase boost near the crossover frequency, it is desired to place one zero and one pole as follows: 27 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 APPLICATION DIAGRAM Figure 26: Single Rail 3A POL Application Circuit: PVin=Vin=12V, Vo=1.2V, Io=3A, fsw=1MHz SUGGESTED BILL OF MATERIALS QTY PART REFERENCE VALUE DESCRIPTION MANUFACTURER PART NUMBER 2 3 1 1 1 1 1 1 1 2 1 1 Cin C7, C12, C24 C11 Cout C8 C23 C26 C32 R1 R2, R3 R4 R9 10uF 0.1uF 56pF 22uF 2200pF 2.2uF 4700pF 1.0uF 1.0k 4.02k 127 23.2k 1206, 25V, X5R, 20% 0603, 25V, X7R, 10% 0603, 50V, NP0, 5% 0805, 6.3V, X5R, 20% 0603,50V,X7R 0603, 16V, X5R, 20% 0603, 50V 10% X7R 0603, 25V, X5R, 10% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W TDK Murata TDK TDK Murata TDK Murata Murata Panasonic Panasonic Panasonic Panasonic C3216X5R1E106M GRM188R71E104KA01B C1608C0G1H560J080AA C2012X5R0J226M GRM188R71H222KA01B C1608X5R1C225M GRM188R71H472KA01D GRM188R61E105KA12D ERJ-3EKF1001V ERJ-3EKF4021V ERJ-3EKF1270V ERJ-3EKF2322V 2 R17, R18 49.9k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V 1 R19 7.5k Panasonic ERJ-3EKF7501V 1 L 1.0uH Coilcraft XFL4020-102ME 1 U1 IR3823 Thick Film, 0603,1/10W,1% SMD, 4.0mmx4.0mmx2.1mm, 10.8mΩ 3A POL, PQFN 3.5mm x3.5mm IR IR3823 28 www.irf.com © 2012 International Rectifier July 18, 2013 IR3823 APPLICATION DIAGRAM 12V R18 49.9k C7 0.1uF C32 1.0uF Cin 2x10uF R19 7.5k Vin Enable PGood PGood PVin Boot R17 49.9k Ext Vcc=5V L1 SW Vcc/LDO_out C23 2.2uF C24 0.1uF 1.0uH R2 4.02k IR3823 SS_Select R9 23.2k Fb Comp Rt/Sync Gnd PGnd R1 C26 475Ω 1.2V 15nF C8 2200pF R4 127Ω Cout 22uF C12 0.1uF R3 4.02k C11 220pF Figure 27: 3A POL Application Circuit with external 5V VCC: PVin=Vin=12V, Vo=1.2V, Io=3A, fsw=1MHz. Please note that loop compensation is adjusted to consider the absence of the input voltage feedforward. 5V Enable Enable PGood C7 0.1uF C32 1.0uF Vin PGood PVin Boot R17 49.9k C24 0.1uF 1.0uH L1 SW Vcc/LDO_out C23 2.2uF Cin 3x10uF IR3823 SS_Select R9 23.2k Rt/Sync Fb Comp Gnd PGnd R1 C26 1k 4.7nF 1V R2 4.02k C8 2200pF R4 127Ω Cout 22uF C12 0.1uF R3 6.04k C11 100pF Figure 28: Single Rail 3A POL Application Circuit: PVin=Vin=5V, Vo=1.0V, Io=3A, fsw=1MHz 29 www.irf.com © 2012 International Rectifier July 18, 2013 IR3823 TYPICAL OPERATING WAVEFORMS Vin = 12V, V0 = 1.2V, I0 = 0-3A, Unless otherwise Specified, SS_Select = Float. Room Temperature, No Air Flow Figure 29: Start up at 3A Load with SS_Select pin floating. Ch1:Vin, Ch2: PGood, Ch3:Vo ,Ch4: Enable Figure 30: Start up at 3A Load with SS_Select pin floating. Ch1:Vin, Ch2: Vcc, Ch3:Vo ,Ch4: Enable Figure 31: Start up with 1.06V Pre Bias, 0A Load Ch3:Vo, Ch2:PGood Figure 32: Output Voltage Ripple, 3A load Ch3: Vout Figure 33: Inductor node at 3A load, Ch3: SW node Figure 34: Short circuit (Hiccup) Recovery, Ch3:Vout , Ch4:Iout 30 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 TYPICAL OPERATING WAVEFORMS Vin = 12V, V0 = 1.2V, I0 = 0-3A, Unless otherwise Specified, SS_Select = Float. Room Temperature, No Air Flow Figure 35: Transient Response, 2A to 3A Step load Ch3:Vout Ch4-Iout Figure 36: Feed Forward for Vin change from 7 to 14V and back to 7V. Ch3-Vout, Ch4-Vin Figure 37: Bode Plot at 6A load, bandwidth = 188 kHz, and phase margin = 53 degrees and gain margin = -10dB 31 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 TYPICAL OPERATING WAVEFORMS Vin = 12V, V0 = 1.2V, I0 = 0-3A, Unless otherwise Specified, SS_Select = Float. Room Temperature, No Air Flow Figure 38: Efficiency vs. Load Current Figure 39: Power Loss vs. Load Current 32 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 TYPICAL OPERATING WAVEFORMS Vin = 12V, V0 = 1.2V, I0 = 0-3A, Unless otherwise Specified, SS_Select = Float. Room Temperature, No Air Flow Figure 40: Thermal Image of the board at 3A load, IR3823=45°C, Inductor=41.3°C 33 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 LAYOUT RECOMMENDATIONS The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with worse than expected results. Make the connections for the power components in the top layer with wide, copper filled areas or polygons. In general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. The inductor, output capacitors and the IR3823 should be as close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place the input capacitor directly at the PVin pin of IR3823. The feedback part of the system should be kept away from the inductor and other noise sources. pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. In a multilayer PCB use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. It is recommended to place all the compensation parts over the analog ground plane in top layer. The Power QFN is a thermally enhanced package. Based on thermal performance it is recommended to use at least a 4-layers PCB. To effectively remove heat from the device the exposed pad should be connected to the ground plane using via holes. Figure 41-Figure 44 illustrates the implementation of the layout guidelines outlined above, on the IRDC3823 4-layer demo board. The critical bypass components such as capacitors for Vin and VCC should be close to their respective PGnd Vout PVin Compensation parts should be placed as close as possible to the Comp pin Resistor Rt should be placed as close as possible to their pins Single point connection between AGND & PGND, should be close to the SupIRBuck and kept away from noise AGnd Allow enough copper & minimum ground length path between Input and Output SW node copper is kept only at the top layer to minimize the switching noise All bypass caps should be placed as close as possible to their connecting pins Figure 41: IRDC3823 Demo Board – Top Layer 34 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 PVin PGnd Vout Figure 42: IRDC3823 Demo Board – Bottom Layer PGnd AGnd Figure 43: IRDC3823 Demo Board – Middle Layer 1 35 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 PGnd Feedback and Vsns trace routing should be kept away from noise sources Figure 44: IRDC3827 Demo Board – Middle Layer 2 36 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 PCB METAL AND COMPONENT PLACEMENT dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly For further information, please refer to “SupIRBuck® Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132) Figure 45: PCB Metal Pad Spacing (all dimensions in mm) * Contact International Rectifier to receive an electronic PCB Library file in your preferred format 37 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 SOLDER RESIST IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) are Non Solder Mask Defined (NSMD) or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. However, for the smaller Signal type leads around the edge of the device, IR recommends that these Figure 46: Solder Resist 38 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 STENCIL DESIGN Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Figure 47: Stencil Pad Spacing (all dimensions in mm) 39 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 MARKING INFORMATION PACKAGE INFORMATION 40 www.irf.com © 2012 International Rectifier August 1, 2013 IR3823 ENVIRONMENTAL QUALIFICATIONS Industrial Qualification Level Moisture Sensitivity Level 3.5mm x 3.5mm PQFN Machine Model (JESD22-A115A) ESD Human Body Model (JESD22-A114F) Charged Device Model (JESD22-C101D) JEDEC Level 2 @ 260°C Class B 200V to <400V Class 2 2000V to <4000V Class III 500V to ≤1000V RoHS6 Compliant Yes † Qualification standards can be found at International Rectifier web site: http://www.irf.com †† Exceptions to AEC-Q101 requirements are noted in the qualification report. Data and specifications subject to change without notice. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com 41 www.irf.com © 2012 International Rectifier August 1, 2013