IRF IR3863MPBF

PD-97605
IR3863MPBF
SupIRBuck
TM
6A HIGHLY INTEGRATED
WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
Features
Description
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The IR3863 SupIRBuckTM is an easy-to-use, fully
integrated and highly efficient DC/DC voltage
regulator. The onboard constant on-time
hysteretic controller and MOSFETs make IR3863
a space-efficient solution that delivers up to 6A of
precisely controlled output voltage.
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Input Voltage Range: 3V to 21V
Output Voltage Range: 0.5V to 12V
Continuous 6A Load Capability
Constant On-Time Control
Compensation Loop not Required
Excellent Efficiency at Very Low Output Currents
Programmable Switching Frequency and Soft
Start
Thermally Compensated Over Current
Protection
Power Good Output
Precision Voltage Reference (0.5V, +/-1%)
Enable Input with Voltage Monitoring Capability
Pre-bias Start Up
Thermal Shut Down
Under/Over Voltage Fault Protection
Forced Continuous Conduction Mode Option
Very Small, Low Profile 4mm x 5mm QFN
Package
Programmable switching frequency, soft start,
and thermally compensated over current
protection allows for a very flexible solution
suitable for many different applications and an
ideal choice for battery powered applications.
Additional features include pre-bias startup, very
precise 0.5V reference, over/under voltage shut
down, power good output, and enable input with
voltage monitoring capability.
Applications
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Notebook and Desktop Computers
Game Consoles
Consumer Electronics – STB, LCD, TV, Printers
General Purpose POL DC-DC Converters
8/8/2012 Rev3.2
1
IR3863MPBF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND unless otherwise specified)
•
VIN, FF …………………………………………………. -0.3V to 25V
•
VCC, PGOOD, EN …………………………………..... -0.3V to 8.0V
•
BOOT …………………………………………………… -0.3V to 33V
•
PHASE …………………………………………………. -0.3V to 25V(DC), -5V(100ns)
•
BOOT to PHASE ………………………………………. -0.3V to 8V
•
ISET …………………………………………………….. -0.3V to 25V, 30mA
•
PGND to GND …………………………………………. -0.3V to +0.3V
•
All other pins …………………………………………… -0.3V to 3.9V
•
Storage Temperature Range ………………………… -65°C To 150°C
•
Junction Temperature Range ………………………… -40°C To 150°C
•
ESD Classification …………………………………….. JEDEC Class 1C
•
Moisture Sensitivity Level ……………………..……… JEDEC Level 2 @ 260°C (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications are not implied.
PACKAGE INFORMATION
4mm x 5mm POWER QFN
 JA  32o C / W
 J - PCB  2o C / W
ORDERING INFORMATION
PKG DESIG
PACKAGE
DESCRIPTION
PIN COUNT
PARTS PER
REEL
M
IR3863MTRPbF
17
4000
M
IR3863MTR1PbF
17
750
8/8/2012 Rev3.2
2
IR3863MPBF
Simplified Block Diagram
8/8/2012 Rev3.2
3
IR3863MPBF
Pin Description
NAME
NUMBER
FCCM
1
ISET
2
PGOOD
3
GND
4,17
I/O
LEVEL
3.3V
DESCRIPTION
Forced Continuous Conduction Mode (CCM). Ground this pin
to enable diode emulation mode or discontinuous conduction
mode (DCM). Pull this pin to 3.3V to operate in CCM under all
load conditions.
Connecting resistor to PHASE pin sets over current trip point.
5V
Power good open drain output – pull up with a resistor to 3.3V
Reference
Bias return and signal reference.
FB
5
3.3V
Inverting input to PWM comparator, OVP / PGOOD sense.
SS
6
3.3V
Soft start/shutdown. This pin provides user programmable softstart function. Connect an external capacitor from this pin to
GND to set the startup time of the output voltage. The converter
can be shutdown by pulling this pin below 0.3V.
NC
7
-
-
3VCBP
8
3.3V
For internal LDO. Bypass with a 1.0µF capacitor to AGND. A
resistor in series with the bypass capacitor may be required in
single-ground plane designs. Refer to Layout
Recommendations for details.
NC
9
-
-
VCC
10
5V
VCC input. Gate drive supply. A minimum of 1.0µF ceramic
capacitor is required.
PGND
11
Reference
Power return.
PHASE
12
VIN
Phase node (or switching node) of MOSFET half bridge.
VIN
13
VIN
Input voltage for the system.
BOOT
14
VIN +VCC
Bootstrapped gate drive supply – connect a capacitor to
PHASE.
FF
15
VIN
Input voltage feed forward – sets on-time with a resistor to VIN.
EN
16
5V
Enable pin to turn on and off the device. Use two external
resistors to set the turn on threshold (see Electrical
Specifications) for input voltage monitoring.
8/8/2012 Rev3.2
4
IR3863MPBF
Recommended Operating Conditions
Symbol
Definition
Min
Max
Unit
V
VIN
VCC
Input Voltage
Supply Voltage
3
4.5
21*
5.5
VOUT
Output Voltage
0.5
12
IOUT
Output Current
0
6
A
Fs
Switching Frequency
N/A
750
kHz
TJ
Junction Temperature
-40
125
oC
* PHASE pin must not exceed 25V.
Electrical Specifications
Unless otherwise specified, these specification apply over VIN = 12V, 4.5V<VCC<5.5V, 0oC ≤ TJ ≤ 125oC.
PARAMETER
CONTROL LOOP
Reference Accuracy, VREF
NOTE
TEST CONDITION
VFB = 0.5V
MIN
TYP
MAX
UNIT
0.495
0.5
0.505
V
On-Time Accuracy
RFF = 180K, TJ = 65oC
280
300
320
ns
Min Off Time
Soft-Start Current
DCM Comparator Offset
EN = High
Measure at VPHASE
8
-4.5
500
10
-2.5
12
0
ns
µA
mV
SUPPLY CURRENT
VCC Supply Current
(standby)
VCC Supply Current
(dynamic)
FF Shutdown Current
EN = Low, No Switching
23
µA
EN = High, Fs = 300kHz
6
mA
EN = Low
2
µA
FORCED CONTINUOUS CONDUCTION MODE (FCCM)
FCCM Start Threshold
FCCM Stop Threshold
8/8/2012 Rev3.2
2
V
0.6
V
5
IR3863MPBF
Electrical Specifications (continued)
Unless otherwise specified, these specification apply over VIN = 12V, 4.5V<VCC<5.5V, 0oC ≤ TJ ≤ 125oC.
PARAMETER
GATE DRIVE
Deadtime
NOTE
1
BOOTSTRAP PFET
Forward Voltage
UPPER MOSFET
Static Drain-to-Source OnResistance
LOWER MOSFET
Static Drain-to-Source OnResistance
FAULT PROTECTION
ISET Pin Output Current
ISET Pin Output Current
Temperature Coefficient
1
Under Voltage Threshold
Under Voltage Hysteresis
Monitor body diode conduction
on PHASE pin
1
5
MAX
UNIT
30
ns
VCC = 5V, ID = 5A, TJ = 25oC
21.1
26
mΩ
VCC = 5V, ID = 5A, TJ = 25oC
20.1
25
mΩ
17
19
4400
21
0.37
0.4
0.43
µA
ppm/
oC
V
On the basis of 25oC
On the basis of 25oC
Rising VFB
VCC Turn-off Threshold
mV
7.5
mV
0.586 0.625 0.655
V
7.5
mV
Falling VFB
-40oC to 125oC
VCC Turn-on Threshold
TYP
300
Rising VFB & Monitor PGOOD
1
MIN
I(BOOT) = 10mA
Falling VFB & Monitor PGOOD
Over Voltage Threshold
Over Voltage Hysteresis
TEST CONDITION
3.9
4.2
4.5
V
3.6
3.9
4.2
V
VCC Threshold Hysteresis
300
-40oC
EN Rising Threshold
to
125oC
1.1
EN Hysteresis
1.25
mV
1.45
400
EN Input Current
EN = 3.3V
V
mV
15
µA
50
Ω
PGOOD Pull Down
Resistance
25
PGOOD Delay Threshold
(VSS)
1
V
140
oC
20
oC
Thermal Shutdown
Threshold
1
Thermal Shutdown
Threshold Hysteresis
1
125
Note 1: Guaranteed by design, not tested in production
Note 2: Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on
application note AN1132 page 2). Products with prior date code of 1227 are qualified with MSL3
for Consumer Market.
8/8/2012 Rev3.2
6
IR3863MPBF
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, T A = 25oC, no
airflow, unless otherwise specified
95%
95%
90%
85%
90%
12VIN
16VIN
85%
Efficiency
Efficiency
80%
7VIN
75%
70%
65%
60%
80%
50%
55%
1
VOUT = 1.05V; L = 2.2uH, 11.2mΩ
65%
60%
0.1
VOUT = 1.5V; L = 3.3uH, 19.9mΩ
70%
55%
45%
0.01
VOUT = 3.3V; L = 4.7uH, 23mΩ
75%
50%
0.01
10
0.1
Load Current (A)
Figure 1. Efficiency vs. Load Current for
VOUT = 1.05V
10
Figure 2. Efficiency vs. Load Current for
VIN = 12V
350
1400
300
1200
250
1000
RFF (kOhm)
Switching Frequency (kHz)
1
Load Current (A)
200
150
100
5.0 Vout
4.0
3.0
2.0
1.0
4.5
3.5
2.5
1.5
0.5
800
600
400
50
200
0
0
1
2
3
4
5
0
200 250 300 350 400 450 500 550 600 650 700 750
Switching Frequency (kHz)
6
Load Current (A)
Figure 4. RFF vs. Switching Frequency
1.080
1.080
1.075
1.075
Output Voltage (V)
Output Voltage (V)
Figure 3. Switching Frequency vs.
Load Current
16VIN
12VIN
7VIN
1.070
1.065
1.060
1.055
1.050
1.070
1.065
1.060
1.055
1.050
1.045
1.045
0
1
2
3
4
5
Load Current (A)
Figure 5. Output Voltage Regulation
8/8/2012 Rev3.2
6
7
8
9
10
11
12
13
14
15
Input Voltage (V)
Figure 6. Line Regulation at IOUT = 6A
7
16
IR3863MPBF
TYPICAL APPLICATION CIRCUIT
+3 .3V
V CC
T P1
V INS
R1
10 K
V IN
R2
10 K
T P2
V IN
C1
1u F
EN
T P4
EN
C2
22 uF
+ C3
68 uF
4
3
FCCM
R3
20 0K
T P5
P GND
C4
0.22u F
R4
10 K
5
FB
T P13
SS
SS
6
7
T P14
+3 .3V
13
V IN
14
15
B OOT
16
P GOOD
IR3863
GND1
P HA SE
C7
op en
C8
op en
C9
15 0uF
C10
47 uF
C11
op en
C12
0.1uF
R13
op en
12
FB
T P10
P GND
C24
op en
T P24
P GNDS
SS
NC1
8
C20
0.1uF
C6
op en
C15
op en
C16
op en
C17
op en
C18
op en
C19
op en
C26
op en
C27
op en
P GND
4
T P7
V OUT
C13
op en
11
3
V OUT
R6
op en
ISE T
V CC
P GOOD
T P11
P GOOD
V SW
U1
IR3 863
FCCM
10
2
3V CBP
1
FF
GND
EN
17
L1
2.2uH
+3 .3V
R5
10 K
T P23
V OUTS
T P6
P GNDS
ISE T
NC2
V SW
9
1
2
S W1
E N / FCCM
+3 .3V
2
T P28
V ID
C22
op en
9
8
10
+V out2s -Vo ut2 s
5
+V out1s -Vo ut1 s
4
7
R8
2.55K
Q1
op en
1
3
R10
op en
T P18
V OLT A GE S E NS E
V OUT
R9
op en
3
R11
20
+3 .3 V
T P25
B
2
T P27
A
1
C23
op en
+V i ns
V CC
+V dd2 s -Vd d2s
-Vi ns
R7
2.80K
+V dd1 s -Vd d1s
C14
op en
V CC
T P17
P GND
C25
1u F
V IN
T P16
V CC
R12
4.99
6
C21
1u F
T P26
A GND
Figure 7. Typical Application Circuit for VOUT = 1.05V, Fs = 300kHz
Demoboard Bill of Materials
QTY REF DESIGNATOR VALUE
3
C1, C21, C25
1.00uF
1
C10
47uF
2
C12, C20
0.100uF
1
C2
22.0uF
1
C3
68uF
1
C4
0.22uF
1
C9
150uF
1
L1
2.2uH
4
R1, R2, R4, R5
10.0K
1
R11
20
1
R12
4.99
1
R3
200K
1
R7
2.80K
1
R8
2.55K
1
SW1
SPST
1
U1
IR3863
8/8/2012 Rev3.2
DESCRIPTION
capacitor, X7R, 1.00uF, 25V, 0.1, 0603
capacitor, 47uF, 6.3V, 805
capacitor, X7R, 0.100uF, 25V, 0.1, 603
capacitor, X5R, 22.0uF, 16V, 20%, 1206
capacitor, electrolytic, 68uF, 25V, 0.2, SMD
capacitor, X5R, 0.22uF, 10V, 0.1, 0603
capacitor, tantalum polymer, 150uF, 6.3V, 20%, 7343
inductor, ferrite, 2.2uH, 8.0A, 11.2mOhm, SMT
resistor, thick film, 10.0K, 1/10W, 0.01, 0603
resistor, thick film, 20, 1/10W, 0.01, 603
resistor, thick film, 4.99, 1/8W, 0.01, 603
resistor, thick film, 200K, 1/10W, 0.01, 603
resistor, thick film, 2.80K, 1/10W, 0.01, 603
resistor, thick film, 2.55K, 1/10W, 0.01, 0603
switch, DIP, SPST, 2 position, SMT
4mm X 5mm QFN
MANUFACTURER
PART NUMBER
Murata
GRM188R71E105KA12D
TDK
C2012X5R0J476M
TDK
C1608X7R1E104K
Taiyo Yuden
EMK316BJ226ML-T
Panasonic
EEV-FK1E680P
TDK
C1608X5R1A224K
Sanyo
6TPC150M
Cyntec
PCMB065T-2R2MS
KOA
RK73H1J1002F
KOA
RK73H1JLTD20R0F
KOA
RK73H1J4R99F
KOA
RK73H1JLTD2003F
KOA
RK73H1JLTD2801F
KOA
RK73H1JLTD2551F
C&K Components
SD02H0SK
IRF
IR3863MTRPBF
8
IR3863MPBF
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, T A = 25oC, no
airflow, unless otherwise specified
EN
EN
PGOOD
PGOOD
SS
SS
VOUT
VOUT
5V/div 5V/div 1V/div 500mV/div
5ms/div
5V/div 5V/div 1V/div 500mV/div
1ms/div
Figure 9: Shutdown
Figure 8: Startup
VOUT
VOUT
PHASE
PHASE
iL
iL
20mV/div 10V/div 500mA/div
5µs/div
Figure 10: DCM (IOUT = 0.1A)
20mV/div 10V/div 2A/div
2µs/div
Figure 11: CCM (IOUT = 5A)
PGOOD
PGOOD
VOUT
FB
SS
VOUT
iL
IOUT
5V/div 1V/div 1V/div 5A/div
500us/div
Figure 12: Over Current Protection
(tested by shorting VOUT to PGND)
8/8/2012 Rev3.2
5V/div 1V/div 500mV/div 2A/div
50µs/div
Figure 13: Over Voltage Protection
(tested by shorting FB to VOUT)
9
IR3863MPBF
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, T A = 25oC, no
airflow, unless otherwise specified
VOUT
VOUT
PHASE
PHASE
iL
iL
50mV/div 10V/div 2A/div
50µs/div
Figure 14: Load Transient 0-2A
50mV/div 10V/div 2A/div
50µs/div
Figure 15: Load Transient 3-5A
FCCM
FCCM
PHASE
PHASE
VOUT
VOUT
iL
iL
5V/div 10V/div 500mV/div 5A/div
10µs/div
2V/div 10V/div 500mV/div 5A/div
5µs/div
Figure 16: DCM/FCCM Transition
Figure 17: FCCM/DCM Transition
Figure 18: Thermal Image at VIN = 12V, IOUT =
6A (IR3863: 60oC, Inductor: 45oC, PCB: 32oC)
Figure 19: Thermal Image at VIN = 16V, IOUT =
6A (IR3863: 61oC, Inductor: 46oC, PCB: 33oC)
8/8/2012 Rev3.2
10
IR3863MPBF
CIRCUIT DESCRIPTION
PWM COMPARATOR
The PWM comparator initiates a SET signal
(PWM pulse) when the FB pin falls below the
reference (VREF) or the soft start (SS) voltage.
ON-TIME GENERATOR
The PWM on-time duration is programmed with
an external resistor (RFF) from the input supply
(VIN) to the FF pin. The simplified equation for
RFF is shown in equation 1. The FF pin is held
to an internal reference after EN goes HIGH. A
copy of the current in RFF charges a timing
capacitor, which sets the on-time duration, as
shown in equation 2.
RFF 
VOUT
1V  20 pF  FSW
(1)
TON 
RFF 1V  20 pF
VIN
(2)
CONTROL LOGIC
The control logic monitors input power sources,
sequences the converter through the soft-start
and protective modes, and initiates an internal
RUN signal when all conditions are met.
PGOOD
The PGOOD pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation. The PGOOD logic monitors
EN_DELAY, SS_DELAY, and under/over voltage
fault signals. PGOOD is released only when
EN_DELAY and SS_DELAY = HIGH and output
voltage is within the OV and UV thresholds.
PRE-BIAS STARTUP
IR3863 is able to start up into pre-charged output,
which prevents oscillation and disturbances of the
output voltage.
With constant on-time control, the output voltage
is compared with the soft start voltage (SS) or
Vref, depending on which one is lower, and will
not start switching unless the output voltage drops
below the reference. This scheme prevents
discharge of a pre-biased output voltage.
SHUTDOWN
The IR3863 will shutdown if VCC is below its
UVLO limit. The IR3863 can be shutdown by
pulling the EN pin below its lower threshold.
Alternatively, the output can be shutdown by
pulling the soft start pin below 0.3V.
VCC and 3VCBP pins are continuously
monitored, and the IR3863 will be disabled if the
voltage of either pin drops below the falling
thresholds. EN_DELAY will become HIGH when
VCC and 3VCBP are in the normal operating
range and the EN pin = HIGH.
SOFT START
With EN = HIGH, an internal 10µA current
source charges the external capacitor (CSS) on
the SS pin to set the output voltage slew rate
during the soft start interval. The soft start time
(tSS) can be calculated from equation 3.
t SS 
CSS  0.5V
10A
(3)
The feedback voltage tracks the SS pin until SS
reaches the 0.5V reference voltage (Vref), then
feedback is regulated to Vref. CSS will continue
to be charged, and when SS pin reaches VSS
(see Electrical Specification), SS_DELAY goes
HIGH. With EN_DELAY = LOW, the capacitor
voltage and SS pin is held to the FB pin voltage.
A normal startup sequence is shown in Figure
20.
8/8/2012 Rev3.2
Figure 20. Normal Startup
11
IR3863MPBF
CIRCUIT DESCRIPTION
UNDER/OVER VOLTAGE MONITOR
The IR3863 monitors the voltage at the FB node
through a 350ns filter. If the FB voltage is below
the under voltage threshold, UV# is set to LOW
holding PGOOD to be LOW. If the FB voltage is
above the over voltage threshold, OV# is set to
LOW, the shutdown signal (SD) is set to HIGH,
MOSFET gates are turned off, and PGOOD
signal is pulled low. Toggling VCC or EN will
allow the next start up. Figure 21 and 22 show
PGOOD status change when UV/OV is
detected. The over voltage and under voltage
thresholds can be found in the Electrical
Specification section.
OVER CURRENT MONITOR
The over-current circuitry monitors the output
current during each switching cycle. The voltage
across the lower MOSFET, VPHASE, is
monitored for over current and zero crossing. The
OCP circuit evaluates VPHASE for an over
current condition typically 270ns after the lower
MOSFET is gated on. This delay functions to filter
out switching noise. The minimum lower gate
interval allows time to sample VPHASE.
The over current trip point is programmed with a
resistor from the ISET pin to PHASE pin, as
shown in equation 4. When over current is
detected, the MOSFET gates are tri-state and SS
voltage is pulled to 0V. This initiates a new soft
start cycle. If there is a total of four OC events, the
IR3863 will disable switching. Toggling VCC or
EN will allow the next start up.
RSET 
RDSON  IOC
19 A
(4)
* typical filter delay
Figure 21. Under/Over Voltage Monitor
Figure 23. Over Current Protection
* typical filter delay
UNDER VOLTAGE LOCK-OUT
The IR3863 has VCC and EN under voltage lockout (UVLO) protection. When either VCC or EN is
below their UVLO threshold, IR3863 is disabled.
IR3863 will restart when both VCC and EN are
above their UVLO thresholds.
Figure 22. Over Voltage Protection
8/8/2012 Rev3.2
12
IR3863MPBF
CIRCUIT DESCRIPTION
OVER TEMPERATURE PROTECTION
When the IR3863 exceeds its over temperature
threshold, the MOSFET gates are tri-state and
PGOOD is pulled low. Switching resumes once
temperature drops below the over temperature
hysteresis level.
GATE DRIVE LOGIC
The gate drive logic features adaptive dead
time, diode emulation, and a minimum lower
gate interval.
An adaptive dead time prevents the
simultaneous conduction of the upper and lower
MOSFETs. The lower gate voltage must be
below approximately 1V after PWM goes HIGH
before the upper MOSFET can be gated on.
Also, the differential voltage between the upper
gate and PHASE must be below approximately
1V after PWM goes LOW before the lower
MOSFET can be gated on.
The upper MOSFET is gated on after the
adaptive delay for PWM = HIGH and the lower
MOSFET is gated on after the adaptive delay
for PWM = LOW.
When FCCM = LOW, the lower MOSFET is
driven ‘off’ when the ZCROSS signal indicates
that the inductor current is about to reverse
direction. The ZCROSS comparator monitors
the PHASE voltage to determine when to turn
off the lower MOSFET. The lower MOSFET
stays ‘off’ until the next PWM falling edge.
When the lower peak of the inductor current is
above zero, IR3863 operates in continuous
conduction mode. The continuous conduction
mode can also be selected for all load current
levels by pulling FCCM to HIGH.
Whenever the upper MOSFET is turned ‘off’, it
stays ‘off’ for the Min Off Time denoted in the
Electrical Specifications. This minimum
duration allows time to recharge the bootstrap
capacitor and allows the over current monitor
to sample the PHASE voltage.
COMPONENT SELECTION
Selection of components for the converter is an
iterative process which involves meeting the
specifications
and
tradeoffs
between
performance and cost. The following sections
will guide one through the process.
Inductor Selection
Inductor selection involves meeting the steady
state output ripple requirement, minimizing the
switching loss of the upper MOSFET, meeting
transient
response
specifications
and
minimizing the output capacitance. The output
voltage includes a DC voltage and a small AC
ripple component due to the low pass filter
which has incomplete attenuation of the
switching harmonics. Neglecting the inductance
in series with the output capacitor, the
magnitude of the AC voltage ripple is
determined by the total inductor ripple current
flowing through the total equivalent series
resistance (ESR) of the output capacitor bank.
ΔI 
One can use equation 5 to find the required
inductance. ΔI is defined as shown in Figure 24.
The main advantage of small inductance is
increased inductor current slew rate during a
load transient, which leads to a smaller output
capacitance requirement as discussed in the
Output Capacitor Selection section. The draw
back of using smaller inductances is increased
switching power loss in the upper MOSFET,
which reduces the system efficiency and
increases the thermal dissipation.
Input Current
IOUT
ΔI
TS
Figure 24. Typical Input Current Waveform
TON  VIN  VOUT 
(5)
2L
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COMPONENT SELECTION
Input Capacitor Selection
The main function of the input capacitor bank is
to provide the input ripple current and fast slew
rate current during the load current step up. The
input capacitor bank must have adequate ripple
current carrying capability to handle the total
RMS current. Figure 24 shows a typical input
current. Equation 6 shows the RMS input
current. The RMS input current contains the DC
load current and the inductor ripple current. As
shown in equation 5, the inductor ripple current
is unrelated to the load current. The maximum
RMS input current occurs at the maximum
output current. The maximum power dissipation
in the input capacitor equals the square of the
maximum RMS input current times the input
capacitor’s total ESR.
Ts
1
IIN_RMS 
  f 2 t   dt
Ts 0
2
1  ΔI 
 IOUT  TON  Fs  1   
 (6)
3  IOUT 
The voltage rating of the input capacitor needs
to be greater than the maximum input voltage
because of high frequency ringing at the phase
node. The typical percentage is 25%.
Output Capacitor Selection
Selection of the output capacitor requires
meeting voltage overshoot requirements during
load removal, and meeting steady state output
ripple voltage requirements.
The output
capacitor is the most expensive converter
component and increases the overall system
cost. The output capacitor decoupling in the
converter typically includes the low frequency
capacitor, such as Specialty Polymer Aluminum,
and mid frequency ceramic capacitors.
The first purpose of output capacitors is to
provide current when the load demand exceeds
the inductor current, as shown in Figure 25.
Equation 7 shows the charge requirement for a
certain load step. The advantage provided by
the IR3863 at a load step is the reduced delay
compared to a fixed frequency control method.
If the load increases right after the PWM signal
goes low, the longest delay will be equal to the
minimum lower gate on-time as shown in the
Electrical Specification table. The IR3863 also
reduces the inductor current slew time, the time
it takes for the inductor current to reach equality
with the output current, by increasing the
switching frequency up to 1/(TON + Min Off
Time). This results in reduced recovery time.
Load
Current
I STEP
Output
Charge
Inductor
Slew
Rate
t
Δt
Figure 25. Charge Requirement during Load Step
Q  C  V  0.5  ISTEP  t
(7a)
 1 L  ISTEP 2 
COUT 
 
 (7b)
VDROP  2 VIN  VOUT 
1
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COMPONENT SELECTION
The output voltage drop, VDROP, initially depends
on the characteristic of the output capacitor.
VDROP is the sum of the equivalent series
inductance (ESL) of the output capacitor times
the rate of change of the output current and the
ESR times the change of the output current.
VESR is usually much greater than VESL. The
IR3863 requires a total ESR such that the ripple
voltage at the FB pin is greater than 7mV. The
second purpose of the output capacitor is to
minimize the overshoot of the output voltage
when the load decreases as shown in Figure
26. By using the law of energy before and after
the load removal, equation 8 shows the output
capacitance requirement for a load step down.
COUT 
L  ISTEP 2
(8)
VOS 2  VOUT 2
VOS
VOUT
VL
VDROP
VESR
IOUT
Boot Capacitor Selection
The boot capacitor starts the cycle fully charged
to a voltage of VB(0). Cg equals 0.6nF in
IR3863. Choose a sufficiently small ΔV such that
VB(0)-ΔV exceeds the maximum gate threshold
voltage to turn on the upper MOSFET.
 V (0) 
CBOOT  Cg   B  1 (9)
 ΔV

Choose a boot capacitor value larger than the
calculated CBOOT in equation 9. Equation 9 is
based on charge balance at CCM operation.
Usually the boot capacitor will be discharged to a
much lower voltage when the circuit is operating
in DCM mode at light load, due to much longer
lower MOSFET off time and the bias current
drawn by the IC. Boot capacitance needs to be
increased if insufficient turn-on of the upper
MOSFET is observed at light load, typically
larger than 0.1µF is needed. The voltage rating
of this part needs to be larger than VB(0) plus
the desired derating voltage. Its ESR and ESL
needs to be low in order to allow it to deliver the
large current and di/dt’s which drive MOSFETs
most efficiently. In support of these requirements
a ceramic capacitor should be chosen.
ISTEP
Figure 26. Typical Output Voltage Response
Waveform
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IR3863MPBF
However, if space allows, PIMB104T-3R3MS39 (11mm x 10mm) with 10.8mΩ DCR will
provide higher efficiency. Ripple current needs
to be recalculated using the chosen inductor.
DESIGN EXAMPLE
Design Criteria:
Input Voltage, VIN, = 7V to 16V
Output Voltage, VOUT = 1.5V
Switching Frequency, Fs = 300kHz
Inductor Ripple Current, 2ΔI = 1.5A
Maximum Output Current, IOUT = 6A
Over Current Trip, IOC = 9A
Overshoot Allowance for 3A Load Step Down,
VOS = VOUT + 50mV
Undershoot Allowance for 3A Load Step Up,
VDROP = 50mV
Find RFF :
RFF 
1.5V
 250 k
1V  20 pF  300kHz
Pick a standard value 255 kΩ, 1% resistor.
Find RSET :
RSET 
20.1m  9 A
19A
 9.5k
2ΔI 
1.5V  16V - 1.5V 
 1.37 A
16V  3.3H  300kHz
Choose an input capacitor:
2
1.5V
1  1.37 A / 2 
IIN_RMS  6 A 
 1  
  1.8 A
16V
3  6A 
A
Panasonic
10µF
(ECJ3YB1E106M)
accommodates 6 Arms of ripple current at
300kHz. Due to the chemistry of multilayer
ceramic capacitors, the capacitance varies over
temperature and operating voltage, both AC and
DC. One 10µF capacitor is recommended. In a
practical solution, one 1µF capacitor is required
along with 10µF. The purpose of the 1µF
capacitor is to suppress the switching noise and
deliver high frequency current.
Pick a 9.53kΩ, 1% standard resistor.
Choose an output capacitor:
Find a resistive voltage divider for VOUT = 1.5V:
To meet the undershoot and overshoot
specification, equation 7b and 8 will be used to
calculate the minimum output capacitance. As a
result, 130µF will be needed for 3A load
removal. To meet the stability requirement,
choose an output capacitors with ESR larger
than 16mΩ. Combine those two requirements,
one can choose a set of output capacitors from
manufactures such as SP-Cap (Specialty
Polymer Capacitor) from Panasonic or POSCAP
from Sanyo. A 150µF (4TPE150M) from Sanyo
with 25mΩ ESR will meet both requirements.
VFB 
R2
 VOUT  0.5V
R2  R1
R2 = 1.40kΩ, R1 = 2.80 kΩ, both 1% standard
resistors.
Choose the soft start capacitor:
Once the soft start time has chosen, such as
1000us to reach to the reference voltage, a
22nF for CSS is used to meet 1000µs.
Choose an inductor to meet the design
specification:
VOUT  VIN  VOUT 
VIN  2ΔI  Fs
1.5V  16V - 1.5V 

16V 1.5 A  300kHz
 3.0H
L
Choose an inductor with low DCR and AC
power loss to increase the overall system
efficiency based on allowed physical size
requirement. For instance, PCMB065T-3R3MS
from CYNTEC is a 7mm x 6.6mm inductor with
19.9mΩ DCR.
If an all ceramic output capacitor solution is
desired, the external slope injection circuit
composed of R6, C13, and C14 is required as
explained in the Stability Consideration Section.
In this design example, we can choose C14 =
1nF and C13 = 100nF. To calculate the value of
R6 with PCMB065T-3R3MS as our inductor:
R6 
L
DCR  C13
3.3H
19.9m 100nF
 1.66k

Pick a standard value for R6 = 1.65kΩ.
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STABILITY CONSIDERATIONS
LAYOUT RECOMMENDATIONS
Constant-on-time control is a fast , ripple based
control scheme. Unstable operation can occur
if certain conditions are not met. The system
instability is usually caused by:
Bypass Capacitor:
As VCC bypass capacitor, a 1µF high quality
ceramic capacitor should be placed on the same
side as the IR3863 and connected to VCC and
PGND pins directly. A 1µF ceramic capacitor
should be connected from 3VCBP to AGND to
avoid noise coupling into controller circuits. For
single-ground designs, a resistor (R12) in the
range of 5 to 10Ω in series with the 1µF
capacitor as shown in Figure 7 is recommended.
• Switching noise coupled to FB input:
This causes the PWM comparator to trigger
prematurely after the 400ns minimum on-time
for lower MOSFET. It will result in double or
multiple pulses every switching cycle instead
of the expected single pulse. Double pulsing
can causes higher output voltage ripple, but in
most application it will not affect operation.
This can usually be prevented by careful
layout of the ground plane and the FB sensing
trace.
• Steady state ripple on FB pin being too small:
The PWM comparator in IR3863 requires
minimum 7mVp-p ripple voltage to operate
stably. Not enough ripple will result in similar
double pulsing issue described above. Solving
this may require using output capacitors with
higher ESR.
• ESR loop instability:
The stability criteria of constant on-time is:
ESR*Cout>Ton/2. If ESR is too small that this
criteria is violated then sub-harmonic
oscillation will occur. This is similar to the
instability problem of peak-current-mode
control with D>0.5. Increasing ESR is the
most effective way to stabilize the system, but
the tradeoff is the larger output voltage ripple.
• System with all ceramic output capacitors:
For applications with all ceramic output
capacitors, the ESR is usually too small to
meet the stability criteria. In these
applications, external slope compensation is
necessary to make the loop stable. The ramp
injection circuit, composed of R6, C13, and
C14, shown in Figure 7 is required. The
inductor current ripple sensed by R6 and C13
is AC coupled to the FB pin through C14. C14
is usually chosen between 1 to 10nF, and C13
between 10 to 100nF. R6 should then be
chosen such that L/DCR = C13*R6.
Boot Circuit:
CBOOT should be placed near the BOOT and
PHASE pins to reduce the impedance when the
upper MOSFET turns on.
Power Stage:
Figure 27 shows the current paths and their
directions for the on and off periods. The on time
path has low average DC current and high AC
current. Therefore, it is recommended to place
the input ceramic capacitor, upper, and lower
MOSFET in a tight loop as shown in Figure 27.
The purpose of the tight loop from the input
ceramic capacitor is to suppress the high
frequency (10MHz range) switching noise and
reduce Electromagnetic Interference (EMI). If
this path has high inductance, the circuit will
cause voltage spikes and ringing, and increase
the switching loss. The off time path has low AC
and high average DC current. Therefore, it
should be laid out with a tight loop and wide
trace at both ends of the inductor. Lowering the
loop resistance reduces the power loss. The
typical resistance value of 1-ounce copper
thickness is 0.5mΩ per square inch.
Q1
Q2
Figure 27. Current Path of Power Stage
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PCB Metal and Components Placement
Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to
lead spacing should be ≥ 0.2mm to minimize shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The
outboard extension ensures a large toe fillet that can be easily inspected.
Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width.
However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper, or
no less than 0.1mm for 1 oz. Copper, or no less than 0.23mm for 3 oz. Copper.
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Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist
should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist
onto the copper of 0.05mm to accommodate solder resist misalignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the
high aspect ratio of the solder resist strip separating the lead lands from the pad land.
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Stencil Design
The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads.
Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much
solder is deposited on the center pad the part will float and the lead lands will open.
The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land
to the lead lands when the part is pushed into the solder paste.
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IR3863MPBF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial Market (Note 2)
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 03/12
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