Cypress CY7C1381D-133AXI 18 mbit (512 k ã 36/1 m ã 18) flow through sram Datasheet

CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
18 Mbit (512 K × 36/1 M × 18)
Flow Through SRAM
18 Mbit (512 K × 36/1 M × 18) Flow Through SRAM
Features
Functional Description
■
Supports 133 MHz bus operations
■
512 K × 36 and 1 M × 18 common I/O
■
3.3 V core power supply (VDD)
■
2.5 V or 3.3 V I/O supply (VDDQ)
■
Fast clock-to-output time
❐ 6.5 ns (133 MHz version)
■
Provides high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed write
■
Asynchronous output enable
■
CY7C1381D/CY7C1381F available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball
FPBGA package. CY7C1381F/CY7C1383F available in
Pb-free and non Pb-free 119-ball BGA package
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
ZZ sleep mode option
The CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F is a
3.3 V, 512 K × 36 and 1 M × 18 synchronous flow through
SRAMs, designed to interface with high speed microprocessors
with minimum glue logic[1]. Maximum access delay from clock
rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures
the first address in a burst and increments the address
automatically for the rest of the burst access. All synchronous
inputs are gated by registers controlled by a positive edge
triggered clock input (CLK). The synchronous inputs include all
addresses, all data inputs, address pipelining chip enable (CE1),
depth-expansion chip enables (CE2 and CE3 [2]), burst control
inputs (ADSC, ADSP, and ADV), write enables (BWx, and BWE),
and global write (GW). Asynchronous inputs include the output
enable (OE) and the ZZ pin.
The CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F allows
interleaved or linear burst sequences, selected by the MODE
input pin. A HIGH selects an interleaved burst sequence, while
a LOW selects a linear burst sequence. Burst accesses can be
initiated with the processor address strobe (ADSP) or the cache
controller address strobe (ADSC) inputs. Address advancement
is controlled by the address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F operates
from a +3.3 V core power supply while all outputs operate with a
+2.5 V or +3.3 V supply. All inputs and outputs are
JEDEC-standard and JESD8-5-compatible.
Notes
1. For best practices or recommendations, refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
Cypress Semiconductor Corporation
Document Number: 38-05544 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 3, 2011
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Logic Block Diagram – CY7C1381D/CY7C1381F [3] (512 K × 36)
ADDRESS
REGISTER
A0, A1, A
A [1:0]
MODE
Q1
ADV
BURST
COUNTER
AND LOGIC
Q0
CLR
CLK
ADSC
ADSP
DQ D , DQP D
DQ D , DQP D
BW D
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
DQ C , DQP C
DQ C , DQP C
BW C
WRITE REGISTER
WRITE REGISTER
MEMORY
ARRAY
DQ B , DQP B
DQ B , DQP B
BW B
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQP C
WRITE REGISTER
DQP D
WRITE REGISTER
DQ A , DQP
DQ A , DQP
BW A
BYTE
A
WRITE REGISTER
BYTE
BWE
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
Logic Block Diagram – CY7C1383D/CY7C1383F [3] (1 M × 18)
A0,A1,A
ADDRESS
REGISTER
A[1:0]
MODE
BURST Q1
COUNTER AND
ADV
Q0
DQ B ,DQP B
BW B
DQ A ,DQP A
BW A
DQ B ,DQP B
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQ A ,DQP A
WRITE DRIVER
BWE
GW
CE 1
CE 2
CE 3
ENABLE
INPUT
REGISTERS
OE
SLEEP
CONTROL
Note
3. CY7C1381F and CY7C1383F have only 1 chip enable (CE1).
Document Number: 38-05544 Rev. *I
Page 2 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Contents
Selection Guide ................................................................ 4
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses .............................................. 10
Single Write Accesses Initiated by ADSP ................. 10
Single Write Accesses Initiated by ADSC ................. 10
Burst Sequences ............................................................ 10
Sleep Mode ............................................................... 10
ZZ Mode Electrical Characteristics ............................... 11
Truth Table ...................................................................... 12
Truth Table for Read/Write ............................................ 13
Truth Table for Read/Write ............................................ 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
TAP Controller State Diagram ....................................... 14
Test Access Port (TAP) ............................................. 14
TAP Controller Block Diagram ...................................... 14
PERFORMING A TAP RESET .................................. 14
TAP REGISTERS ...................................................... 14
TAP Instruction Set ................................................... 15
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 17
3.3 V TAP AC Output Load Equivalent ......................... 17
Document Number: 38-05544 Rev. *I
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
119-ball BGA Boundary Scan Order ............................. 19
165-ball BGA Boundary Scan Order ............................. 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
Switching Characteristics .............................................. 23
Timing Diagrams ............................................................ 24
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagrams .......................................................... 29
Acronyms ........................................................................ 32
Document Conventions ................................................. 32
Units of Measure ....................................................... 32
Document History Page ................................................. 33
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC Solutions ......................................................... 34
Page 3 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Selection Guide
Description
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
210
175
mA
Maximum CMOS Standby Current
70
70
mA
Document Number: 38-05544 Rev. *I
Page 4 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Pin Configurations
NC
NC
NC
CY7C1383D
(1 M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document Number: 38-05544 Rev. *I
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1381D
(512 K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
VSS/DNU
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP Pinout (3 Chip Enable)
Page 5 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Pin Configurations (continued)
Figure 2. 119-ball BGA Pinout
CY7C1381F (512 K × 36)
A
1
VDDQ
2
A
3
A
ADSP
4
5
A
6
A
7
VDDQ
B
C
NC/288M
NC/144M
A
A
A
A
ADSC
VDD
A
A
A
A
NC/576M
NC/1G
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
NC
CE1
VSS
VSS
DQPB
DQB
DQB
DQB
F
VDDQ
DQC
VSS
OE
VSS
DQB
VDDQ
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
ADV
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
BWA
VSS
DQA
DQA
DQA
VDDQ
GW
VDD
CLK
L
DQD
DQD
M
VDDQ
DQD
BWD
VSS
N
DQD
DQD
VSS
BWE
A1
NC
VSS
DQA
DQA
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC
A
MODE
VDD
NC
A
NC
T
U
NC
VDDQ
NC/72M
TMS
A
TDI
A
TCK
A
TDO
NC/36M
NC
ZZ
VDDQ
5
6
7
CY7C1383F (1 M × 18)
A
1
2
3
4
VDDQ
A
A
ADSP
A
A
VDDQ
ADSC
VDD
A
A
A
NC/576M
A
B
NC/288M
A
A
C
NC/144M
A
A
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
NC
DQB
VSS
CE1
VSS
NC
DQA
F
VDDQ
NC
VSS
VSS
DQA
VDDQ
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
OE
ADV
NC
VSS
NC
DQA
VDD
DQA
NC
VDDQ
K
NC
DQB
VSS
NC
DQA
L
M
DQB
VDDQ
NC
DQB
NC
VSS
BWA
VSS
DQA
NC
NC
VDDQ
N
DQB
NC
VSS
BWE
A1
VSS
DQA
NC
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
U
NC
NC/72M
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC/36M
TCK
NC
A
TDO
A
A
NC
NC
ZZ
VDDQ
Document Number: 38-05544 Rev. *I
GW
VDD
CLK
NC
NC
VSS
NC/1G
Page 6 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Pin Configurations (continued)
Figure 3. 165-ball FBGA Pinout (3 Chip Enable)
CY7C1381D (512 K × 36)
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
1
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A
A1
VSS
NC
TDO
A
A
A
A
R
MODE
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
CY7C1383D (1 M × 18)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
BWB
NC
CE3
BWE
ADSC
ADV
A
A
NC/144M
A
CE2
NC
BWA
CLK
GW
OE
ADSP
A
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC/1G
NC
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
VSS
DQB
DQB
VDD
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
DQB
NC
NC
VDDQ
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
R
MODE
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
Document Number: 38-05544 Rev. *I
NC/576M
DQPA
DQA
Page 7 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Pin Definitions
Name
I/O
Description
A0, A1, A
Input
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [4] are sampled active.
A[1:0] feed the 2-bit counter.
BWA, BWB
BWC, BWD
Input
Synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input
Synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).
CLK
Input
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 [4] to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
CE2
Input
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 [4] to select or deselect the device. CE2 is sampled only when a new external
address is loaded.
CE3 [4]
Input
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external
address is loaded.
OE
Input
Asynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
Input
Synchronous
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP
Input
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
Input
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized.
BWE
Input
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
ZZ
Input
Asynchronous
ZZ sleep input. This active HIGH input places the device in a non time critical sleep condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
Note
4. CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
Document Number: 38-05544 Rev. *I
Page 8 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Pin Definitions (continued)
Name
I/O
Description
DQs
I/O
Synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQPX are placed in a tristate condition.The outputs are
automatically tristated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state
of OE.
DQPX
I/O
Synchronous
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During
write sequences, DQPX is controlled by BWX correspondingly.
MODE
Input Static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull-up.
VDD
VDDQ
VSS
VSSQ
Power Supply
Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
I/O Ground
Ground for the core of the device.
Ground for the I/O circuitry.
TDO
JTAG Serial Output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
Synchronous
feature is not being used, this pin can be left unconnected. This pin is not available on TQFP
packages.
TDI
JTAG Serial Input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being used, this pin can be left floating or connected to VDD through a pull-up resistor.
This pin is not available on TQFP packages.
TMS
JTAG Serial Input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being used, this pin can be disconnected or connected to VDD. This pin is not available
on TQFP packages.
TCK
JTAG
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be
connected to VSS. This pin is not available on TQFP packages.
NC
–
No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G are
address expansion pins and are not internally connected to the die.
VSS/DNU
Ground/DNU
This pin can be connected to ground or can be left floating.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133 MHz device).
CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F supports
secondary cache in systems using a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486 processors. The linear burst sequence is suited for
processors that use a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE input.
Document Number: 38-05544 Rev. *I
Accesses can be initiated with the processor address strobe
(ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Page 9 of 34
[+] Feedback
CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Three synchronous chip selects (CE1, CE2, CE3 [5]) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 [5] are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deasserted
during this first cycle). The address presented to the address
inputs is latched into the address register and the burst counter
and/or control logic, and later presented to the memory core. If
the OE input is asserted LOW, the requested data is available at
the data outputs with a maximum to tCDV after clock rise. ADSP
is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 [5] are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX) are ignored during this first clock
cycle. If the write inputs are asserted active (see Truth Table for
Read/Write on page 13 for appropriate states that indicate a
write) on the next clock rise, the appropriate data is latched and
written into the device. Byte writes are allowed. All I/O are
tristated during a byte write. As this is a common I/O device, the
asynchronous OE input signal must be deasserted and the I/O
must be tristated prior to the presentation of data to DQs. As a
safety precaution, the data lines are tristated when a write cycle
is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 [5] are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered to
the memory core The information presented to DQ[A:D] is written
into the specified address location. Byte writes are allowed. All
I/O are tristated when a write is detected, even a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/O must be tristated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tristated when a write cycle is detected,
regardless of the state of OE.
Burst Sequences
CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F provides
an on-chip two-bit wraparound burst counter inside the SRAM.
The burst counter is fed by A[1:0], and can follow either a linear
or interleaved burst order. The burst order is determined by the
state of the MODE input. A LOW on MODE selects a linear burst
sequence. A HIGH on MODE selects an interleaved burst order.
Leaving MODE unconnected causes the device to default to a
interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, CE3 [5],
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Table 1. Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Table 2. Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Note
5. CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
Document Number: 38-05544 Rev. *I
Page 10 of 34
[+] Feedback
CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
Document Number: 38-05544 Rev. *I
Test Conditions
ZZ > VDD– 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Min
Max
Unit
–
–
80
2tCYC
–
2tCYC
–
mA
ns
ns
ns
ns
2tCYC
–
0
Page 11 of 34
[+] Feedback
CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Truth Table
The truth table for CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F follows.[6, 7, 8, 9, 10]
Cycle Description
ADDRESS
Used
CE1 CE2 CE3
ZZ
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
Deselected Cycle, Power
Down
None
H
X
X
L
X
L
X
X
X
L–H Tri-State
Deselected Cycle, Power
Down
None
L
L
X
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power
Down
None
L
X
H
L
L
X
X
X
X
L–H Tri-State
Deselected Cycle, Power
Down
None
L
L
X
L
H
L
X
X
X
L–H Tri-State
Deselected Cycle, Power
Down
None
X
X
X
L
H
L
X
X
X
L–H Tri-State
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H Tri-State
X
Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H D
Notes
6. X=Don't Care, H = Logic HIGH, L = Logic LOW.
7. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
9. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for the
remainder of the write cycle.
10. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05544 Rev. *I
Page 12 of 34
[+] Feedback
CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Truth Table for Read/Write
The truth table for CY7C1381D/CY7C1381F read/write follows[11, 12].
Function (CY7C1381D/CY7C1381F)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B(DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC,
DQPB, DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD,
DQPC, DQPA)
H
L
L
L
H
L
Truth Table for Read/Write
The truth table for CY7C1383D/CY7C1383F read/write follows[11, 12].
Function (CY7C1383D/CY7C1383F)
GW
BWE
BWB
BWA
Write Bytes D, C, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
H
L
H
L
Write Byte B – (DQB and DQPB)
H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Notes
11. X=Don't Care, H = Logic HIGH, L = Logic LOW.
12. The table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
Document Number: 38-05544 Rev. *I
Page 13 of 34
[+] Feedback
CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Data-In (TDI)
The
CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F
incorporates a serial boundary scan test access port (TAP).This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3 V or 2.5 V I/O logic levels.
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register. (See TAP Controller Block Diagram.)
CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F contains a
TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Test Data-Out (TDO)
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
may be left unconnected. At power up, the device comes up in a
reset state, which does not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
0
TAP Controller State Diagram
Bypass Register
2 1 0
1
TEST-LOGIC
RESET
TDI
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
CAPTURE-DR
31 30 29 . . . 2 1 0
1
S
election
Circuitr
TDO
y
Identification Register
x . . . . . 2 1 0
CAPTURE-IR
0
Boundary Scan Register
0
0
SHIFT-IR
1
0
1
EXIT1-DR
1
EXIT1-IR
0
1
0
PAUSE-IR
1
TCK
TMS
0
PAUSE-DR
TAP CONTROLLER
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
Instruction Register
0
SHIFT-DR
0
Selection
Circuitry
0
UPDATE-IR
1
0
The 0 or 1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Document Number: 38-05544 Rev. *I
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI ball on
the rising edge of TCK. Data is output on the TDO ball on the
falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram.
Upon power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Page 14 of 34
[+] Feedback
CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The boundary scan order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 18.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification
Codes on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state, when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction when it is shifted in, the TAP controller needs to
be moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
Document Number: 38-05544 Rev. *I
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a high Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST Output Bus Tri-State
IEEE standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-FBGA package).
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
Page 15 of 34
[+] Feedback
CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
high Z condition.
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
Test Clock
(TCK)
3
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range [13, 14]
Parameter
Clock
tTCYC
tTF
tTH
tTL
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
tCS
Hold Times
tTMSH
tTDIH
tCH
Description
Min
Max
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH Time
TCK Clock LOW Time
50
–
20
20
–
20
–
–
ns
MHz
ns
ns
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
Notes
13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 38-05544 Rev. *I
Page 16 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
3.3 V TAP AC Test Conditions
3.3 V TAP AC Output Load Equivalent
Input pulse levels................................................VSS to 3.3 V
1.5V
Input rise and fall times....................................................1 ns
50Ω
Input timing reference levels.......................................... 1.5 V
Output reference levels ................................................. 1.5 V
TDO
Test load termination supply voltage ............................. 1.5 V
Z O= 50 Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted) [15]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
VIL
IX
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Min
Max
Unit
IOH = –4.0 mA
VDDQ = 3.3 V
2.4
–
V
IOH = –1.0 mA
VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 8.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Conditions
GND < VIN < VDDQ
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
–5
5
µA
Note
15. All voltages referenced to VSS (GND).
Document Number: 38-05544 Rev. *I
Page 17 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Identification Register Definitions
CY7C1381D/CY7C1381F
(512 K × 36)
Instruction Field
CY7C1383D/CY7C1383F
(1 M × 18)
Description
Revision Number (31:29)
000
000
Device Depth (28:24) [16]
01011
01011
Device Width (23:18) 119-BGA
101001
101001
Defines the memory type and
architecture.
Device Width (23:18) 165-FBGA
000001
000001
Defines the memory type and
architecture.
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
Describes the version number.
100101
010101
00000110100
00000110100
1
1
ID Register Presence Indicator (0)
Reserved for internal use.
Defines the width and density.
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (×36)
Bit Size (×18)
Instruction Bypass
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-ball BGA package)
85
85
Boundary Scan Order (165-ball FBGA package)
89
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use. This instruction is reserved for future use.
RESERVED
110
Do Not Use. This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
16. Bit #24 is “1” in the register definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05544 Rev. *I
Page 18 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
119-ball BGA Boundary Scan Order [17, 18]
Bit #
Ball ID
Bit #
1
H4
T4
23
24
2
Ball ID
Bit #
Ball ID
Bit #
Ball ID
F6
45
G4
67
L1
E7
46
A4
68
M2
3
T5
25
D7
47
G3
69
N1
4
T6
26
H7
48
C3
70
P1
5
R5
27
G6
49
B2
71
K1
6
L5
28
E6
50
B3
72
L2
7
R6
29
D6
51
A3
73
8
U6
30
C7
52
C2
74
N2
P2
9
R7
31
B7
53
A2
75
R3
10
T7
32
C6
54
B1
76
T1
11
P6
33
A6
55
C1
77
R1
12
N7
34
C5
56
D2
78
T2
13
M6
35
B5
57
E1
79
L3
14
L7
36
G5
58
F2
80
R2
15
K6
37
B6
59
G1
81
T3
16
P7
38
D4
60
H2
82
L4
17
N6
39
B4
61
D1
83
N4
18
L6
40
F4
62
E2
84
P4
19
K7
41
M4
63
G2
85
Internal
20
J5
42
A5
64
H1
21
H6
43
K4
65
J3
22
G7
44
E4
66
2K
Notes
17. Balls which are NC (No Connect) are pre-set LOW.
18. Bit# 85 is pre-set HIGH.
Document Number: 38-05544 Rev. *I
Page 19 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
165-ball BGA Boundary Scan Order [17, 19]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
31
D10
61
G1
2
N7
32
C11
62
D2
3
N10
33
A11
63
E2
4
P11
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
89
Internal
29
F10
59
E1
30
E10
60
F1
Note
19. Bit# 89 is pre-set HIGH.
Document Number: 38-05544 Rev. *I
Page 20 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Storage Temperature ............................... –65 °C to +150 °C
DC Voltage Applied to Outputs
in Tri-State .........................................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................. –0.5 V to VDD + 0.5 V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied .......................................... –55 °C to +125 °C
Latch-up Current..................................................... > 200 mA
Supply Voltage on VDD Relative to GND ......–0.3 V to +4.6 V
Operating Range
Supply Voltage on VDDQ Relative to GND ..... –0.3 V to +VDD
Range
Commercial
Industrial
Ambient
Temperature
0 °C to +70 °C
–40 °C to +85 °C
VDD
VDDQ
3.3 V–5%/+10% 2.5 V – 5%
to VDD
Neutron Soft Error Immunity
Description
Test Conditions
Typ
Max[20]
Unit
LSBU
Logical Single-Bit Upsets
25 °C
361
394
FIT/Mb
LMBU
Logical Multi-Bit Upsets
25 °C
0
0.01
FIT/Mb
SEL
Single Event Latch Up
85 °C
0
0.1
FIT/Dev
Parameter
Electrical Characteristics
Over the Operating Range [21, 22]
Parameter
Description
VDD
VDDQ
Power Supply Voltage
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage [21]
VIL
Input LOW Voltage [21]
IX
Input Leakage Current
except ZZ and MODE
Input Current of MODE
Input Current of ZZ
Test Conditions
Min
Max
Unit
3.135
3.135
2.375
2.4
2.0
–
–
2.0
1.7
–0.3
–0.3
–5
3.6
VDD
2.625
–
–
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
0.7
5
V
V
V
V
V
V
V
V
V
V
V
A
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
for 3.3 V I/O
for 2.5 V I/O
for 3.3 V I/O, IOH = –4.0 mA
for 2.5 V I/O, IOH = –1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
for 2.5 V I/O
for 3.3 V I/O
for 2.5 V I/O
GND  VI  VDDQ
Input = VDD
–
30
A
IOZ
Output Leakage Current
GND  VI  VDD, Output Disabled
–5
5
A
IDD
VDD Operating Supply
Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns cycle, 133 MHz
–
210
mA
10 ns cycle, 100 MHz
–
175
mA
Notes
20. No LMBU or SEL events occurred during testing; this column represents a statistical c2, 95% confidence limit calculation. For more details refer to Application Note
AN54908, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates.
21. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
22. Tpower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05544 Rev. *I
Page 21 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Electrical Characteristics
Over the Operating Range (continued)[21, 22]
Parameter
ISB1
Description
Test Conditions
Min
Max
Unit
7.5 ns cycle, 133 MHz
–
140
mA
10 ns cycle, 100 MHz
–
120
Max VDD, Device Deselected,
All speeds
VIN  VDD – 0.3 V or VIN  0.3 V,
f = 0, inputs static
–
70
mA
Automatic CE
Power Down
Current—CMOS Inputs
7.5 ns cycle, 133 MHz
Max VDD, Device Deselected,
VIN  VDDQ – 0.3 V or VIN  0.3 V,
10 ns cycle, 100 MHz
f = fMAX, inputs switching
–
130
mA
–
110
mA
Automatic CE
Power Down
Current—TTL Inputs
Max VDD, Device Deselected,
VIN  VDD – 0.3 V or VIN  0.3 V,
f = 0, inputs static
–
80
mA
Automatic CE
Power Down
Current—TTL Inputs
Max VDD, Device Deselected,
VIN  VIH or VIN  VIL, f = fMAX,
inputs switching
ISB2
Automatic CE
Power Down
Current—CMOS Inputs
ISB3
ISB4
All Speeds
Capacitance [23]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CIO
Input/Output Capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V.
VDDQ = 2.5 V
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Unit
5
8
9
pF
5
8
9
pF
5
8
9
pF
Test Conditions
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Unit
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
in accordance with EIA/JESD51.
28.66
23.8
20.7
°C/W
4.08
6.2
4.0
°C/W
Thermal Resistance [23]
Parameter
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
VT = 1.5 V
(a)
INCLUDING
JIG AND
SCOPE
Z0 = 50 
VT = 1.25 V
(a)
R = 351 
10%
(c)
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
 1 ns
(b)
GND
5 pF
90%
10%
90%
 1 ns
R = 1667 
2.5 V
OUTPUT
RL = 50 
GND
5 pF
2.5 V I/O Test Load
OUTPUT
ALL INPUT PULSES
VDDQ
R = 1538 
(b)
10%
90%
10%
90%
 1 ns
 1 ns
(c)
Note
23. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05544 Rev. *I
Page 22 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Switching Characteristics
Over the Operating Range [24, 25]
Parameter
tPOWER
Description
VDD(Typical) to the First Access [26]
133 MHz
100 MHz
Unit
Min
Max
Min
Max
1
–
1
–
ms
7.5
–
10
–
ns
Clock
tCYC
Clock Cycle Time
tCH
Clock HIGH
2.1
–
2.5
–
ns
tCL
Clock LOW
2.1
–
2.5
–
ns
Output Times
tCDV
Data Output Valid After CLK Rise
–
6.5
–
8.5
ns
tDOH
Data Output Hold After CLK Rise
2.0
–
2.0
–
ns
tCLZ
Clock to low Z [27, 28, 29]
2.0
–
2.0
–
ns
0
4.0
0
5.0
ns
–
3.2
–
3.8
ns
0
–
0
–
ns
–
4.0
–
5.0
ns
[27, 28, 29]
tCHZ
Clock to high Z
tOEV
OE LOW to Output Valid
[27, 28, 29]
tOELZ
OE LOW to Output low Z
tOEHZ
OE HIGH to Output high Z [27, 28, 29]
Setup Times
tAS
Address Setup Before CLK Rise
1.5
–
1.5
–
ns
tADS
ADSP, ADSC Setup Before CLK Rise
1.5
–
1.5
–
ns
tADVS
ADV Setup Before CLK Rise
1.5
–
1.5
–
ns
tWES
GW, BWE, BW[A:D] Setup Before CLK Rise
1.5
–
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.5
–
1.5
–
ns
tCES
Chip Enable Setup
1.5
–
1.5
–
ns
tAH
Address Hold After CLK Rise
0.5
–
0.5
–
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
–
0.5
–
ns
tWEH
GW, BWE, BW[A:D] Hold After CLK Rise
0.5
–
0.5
–
ns
tADVH
ADV Hold After CLK Rise
0.5
–
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.5
–
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
–
0.5
–
ns
Hold Times
Notes
24. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
25. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
26. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can
be initiated.
27. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 22. Transition is measured ± 200 mV
from steady-state voltage.
28. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system condition.
29. This parameter is sampled and not 100% tested.
Document Number: 38-05544 Rev. *I
Page 23 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Timing Diagrams
Figure 5. Read Cycle Timing [30]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
WES
t
WEH
X
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
30. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05544 Rev. *I
Page 24 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Timing Diagrams
(continued)
Figure 6. Write Cycle Timing [31, 32]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
31. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
32. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 38-05544 Rev. *I
Page 25 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Timing Diagrams
(continued)
Figure 7. Read/Write Cycle Timing [33, 34, 35]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
A1
ADDRESS
tAH
A2
A3
A4
t
BWE, BW
WES
t
A5
A6
D(A5)
D(A6)
WEH
X
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
tCDV
Q(A4)
Q(A2)
Back-to-Back READs
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
33. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
34. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
35. GW is HIGH.
Document Number: 38-05544 Rev. *I
Page 26 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Timing Diagrams
(continued)
Figure 8. ZZ Mode Timing [36, 37]
CLK
t
ZZ
I
t ZZREC
ZZ
t ZZI
SUPPLY
I
DDZZ
t RZZI
ALL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
36. Device must be deselected when entering ZZ mode. See “Truth Table” on page 12 for all possible signal conditions to deselect the device.
37. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05544 Rev. *I
Page 27 of 34
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CY7C1381D/CY7C1381F
CY7C1383D/CY7C1383F
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a
worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit
us at t http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
133
100
Ordering Code
Package
Diagram
Part and Package Type
Operating
Range
CY7C1381D-133AXC
51-85050
100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free
CY7C1381F-133BGC
51-85115
119-ball Ball Grid Array (14 × 22 × 2.4 mm)
CY7C1381D-133AXI
51-85050
100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free
lndustrial
CY7C1381D-100AXC
51-85050
100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1381D-100BZI
51-85180
CY7C1381D-100BZXI
165-ball Fine-Pitch Ball Grid Array (13 × 15 × 1.4 mm)
Commercial
lndustrial
165-ball Fine-Pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free
Ordering Code Definitions
CY 7C 1381
X - XXX
XXX
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Package Type: XXX = AX or BG or BZ or BZX
AX = 100-pin TQFP (Pb-free)
BG = 119-ball BGA
BZ = 165-ball FPBGA
BZX = 165-ball FPBGA (Pb-free)
Frequency Range: XXX = 133 MHz or 100 MHz
Die Revision: X = D or F
D  90 nm
F  errata fix PCN084636
1381 = FT, 512 Kb × 36 (18 Mb)
Marketing Code: 7C = SRAM
Company ID: CY = Cypress
Document Number: 38-05544 Rev. *I
Page 28 of 34
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Package Diagrams
Figure 9. 100-pin Thin Plastic Quad Flat pack (14 × 20 × 1.4 mm), 51-85050
51-85050 *D
Document Number: 38-05544 Rev. *I
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Package Diagrams
(continued)
Figure 10. 119-ball BGA (14 × 22 × 2.4 mm), 51-85115
51-85115 *C
Document Number: 38-05544 Rev. *I
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CY7C1383D/CY7C1383F
Package Diagrams
(continued)
Figure 11. 165-ball FBGA (13 × 15 × 1.4 mm), 51-85180
51-85180 *C
Document Number: 38-05544 Rev. *I
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Acronyms
Acronym
Description
BGA
ball grid array
CE
chip enable
CMOS
complementary metal oxide semiconductor
DDR
double data rate
FPBGA
fine-pitch ball grid array
I/O
input/output
JTAG
Joint Test Action Group
LSB
least significant bit
MSB
most significant bit
OE
output enable
SRAM
static random access memory
TAP
test access port
TCK
test clock
TMS
test mode select
TDI
test data-in
TDO
test data-out
TQFP
thin quad flat pack
Document Conventions
Units of Measure
Symbol
Unit of Measure
ns
nano seconds
V
Volts
µA
micro Amperes
mA
milli Amperes
mm
milli meter
ms
milli seconds
MHz
Mega Hertz
pF
pico Farad
W
Watts
°C
degree Celcius

ohms
%
percent
Document Number: 38-05544 Rev. *I
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Document History Page
Document Title: CY7C1381D/CY7C1381F/CY7C1383D/CY7C1383F 18 Mbit (512 K × 36/1 M × 18) Flow Through SRAM
Document Number: 38-05544
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
254518
RKF
See ECN
New data sheet
*A
288531
SYT
See ECN
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 117-MHz Speed Bin
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA package
Added comment of ‘Pb-free BG packages availability’ below the Ordering Information
*B
326078
PCI
See ECN
Address expansion pins/balls in the pinouts for all packages are modified as per
JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000001 to 101001
Added separate row for 165 -FBGA Device Width (23:18)
Changed JA and JC for TQFP Package from 31 and 6 C/W to 28.66 and 4.08
C/W respectively
Changed JA and JC for BGA Package from 45 and 7 C/W to 23.8 and 6.2 C/W
respectively
Changed JA and JC for FBGA Package from 46 and 3 C/W to 20.7 and 4.0
C/W respectively
Modified VOL, VOH test conditions
Removed comment of ‘Pb-free BG packages availability’ below the Ordering
Information
Updated Ordering Information Table
Changed from Preliminary to Final
*C
351895
PCI
See ECN
Updated Ordering Information Table
*D
416321
NXR
See ECN
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage Current
on page# 18
Changed the IX current values of MODE on page # 18 from –5 A and 30 A
to –30 A and 5 A
Changed the IX current values of ZZ on page # 18 from –30 A and 5 A
to –5 A and 30 A
Changed VIH < VDD to VIH < VDDon page # 18
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*E
475009
VKN
See ECN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
*F
776456
VKN
See ECN
Added Part numbers CY7C1381F and CY7C1383F and its related information
Added footnote# 3 regarding Chip Enable
Updated Ordering Information table
*G
2752731
VKN/PYRS
08/17/09
Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
Modified the disclaimer for the Ordering information.
*H
2897182
NJY
03/22/2010
Removed inactive parts from Ordering Information table; Updated package
diagrams.
*I
3159479
NJY
02/01/2011
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
Document Number: 38-05544 Rev. *I
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05544 Rev. *I
Revised February 3, 2011
Page 34 of 34
All products and company names mentioned in this document may be the trademarks of their respective holders.
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