Elantec EL5283CY-T13 Dual and window 8ns high-speed comparator Datasheet

Dual and Window 8ns High-Speed Comparators
Features
General Description
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•
•
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The EL5283C comparator is designed for operation in single supply
and dual supply applications with 5V to 12V between VS+ and VS-.
For single supplies, the inputs can operate from 0.1V below ground for
use in ground-sensing applications.
8ns typ. propagation delay
5V to 12V input supply
+2.7V to +5V output supply
True-to-ground input
Rail-to-rail outputs
Active low latch
Single available (EL5181C)
Quad available (EL5481C &
EL5482C)
• Pin-compatible 4ns family
available (EL5x85C, EL5287C &
EL5486C)
Applications
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•
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The output side of the comparators can be supplied from a single supply of 2.7V to 5V. The rail-to-rail output swing enables direct
connection of the comparator to both CMOS and TTL logic circuits.
The latch input of the EL5283C can be used to hold the comparator
output value by applying a low logic level to the pin.
The EL5283C contains two comparators set up as a window comparator. A single input is compared with a high and low reference. When
the output goes beyond one of these reference signals, the relevant output goes high.
The EL5283C in the 10-pin MSOP package and is specified for operation over the full -40°C to +85°C temperature range. Also available
are a single (EL5181C) and quad versions (EL5481C and EL5482C).
Threshold detection
High speed sampling circuits
High speed triggers
Line receivers
PWM circuits
High speed V/F converters
Pin Configurations
Ordering Information
Part No.
Package
Tape & Reel
Outline #
EL5283CY
10-Pin MSOP
-
MDP0043
EL5283CY-T13
10-Pin MSOP
13”
MDP0043
VS+ 1
VREFH 2
10 VSD
+
-
IN 3
VREFL 4
9 OUTH
8 LATCH
+
-
7 OUTL
6 GND
EL5283C
(10-Pin MSOP)
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
September 6, 2001
VS- 5
© 2001 Elantec Semiconductor, Inc.
EL5283C - Preliminary
EL5283C - Preliminary
EL5283C - Preliminary
EL5283C - Preliminary
Dual and Window 8ns High-Speed Comparators
Absolute Maximum Ratings (T
A
= 25°C)
Absolute maximum ratings are those values beyond which the device
could be permanently damaged. Absolute maximum ratings are stress
ratings only and functional device operation is not implied.
Analog Supply Voltage (VS+ to VS-)
+13.2V
Digital Supply Voltage (VSD to GND)
+7V
Differential Input Voltage
[(VS-) -0.2V] to [(VS+) +0.2V]
Common-mode Input Voltage
Latch Input Voltage
Storage Temperature Range
Ambient Operating Temperature
Operating Junction Temperature
Power Dissipation
[(VS-) -0.2V] to [(VS+) +0.2V]
-0.2V to [(VSD) +0.2V]
-65°C to +150°C
-40°C to +85°C
125°C
See Curves
Important Note:
All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the
specified temperature and are pulsed tests, therefore: TJ = TC = TA.
Electrical Characteristics
VS = ±5V, VSD = 5V, RL = 2.3kΩ, CL = 15pF, TA = 25°C, unless otherwise specified.
Parameter
Description
Condition
Min
Typ
Max
Unit
1
4
mV
-6
-3.5
Input
VOS
Input Offset Voltage
IB
Input Bias Current
CIN
Input Capacitance
IOS
Input Offset Current
VCM = 0V, VO = 2.5V
µA
5
VCM = 0V, VO = 2.5V
VCM
Input Voltage Range
CMRR
Common-mode Rejection Ratio
-5.1V < VCM < +2.75V
VOH
Output High Voltage
VIN > 250mV
VOL
Output Low Voltage
VIN > 250mV
-2.5
0.5
(VS-) - 0.1
65
pF
2.5
(VS+) - 2.25
90
µA
V
dB
Output
VSD - 0.6
VSD - 0.4
V
GND + 0.25
GND + 0.5
V
Dynamic Performance
tpd+
Positive Going Delay Time
VIN = 1VP-P, VOD = 50mV
8
12
ns
tpd-
Negative Going Delay Time
VIN = 1VP-P, VOD = 50mV
8
12
ns
Supply
IS +
Positive Analog Supply Current
(per comparator)
7
8.2
mA
IS -
Negative Analog Supply Current
(per comparator)
5
6.5
mA
ISD
Digital Supply Current
(per comparator) All inputs high
4
5
mA
(per comparator) All inputs low
0.75
1
mA
PSRR
Power Supply Rejection Ratio
60
2
80
dB
Typical Performance Curves
6.15
Positive Supply Current vs Temperature
(per comparator)
-4.4
6.1
-4.5
6.05
-4.6
-4.7
IS- (mA)
IS+ (mA)
6
Negative Supply Current vs Temperature
(per comparator)
5.95
5.9
5.85
-4.8
-4.9
-5
5.8
-5.1
5.75
5.7
-50
-30
-10
10
30
50
70
-5.2
-50
90
-30
-10
7
Positive Supply Current vs Supply Voltage
(per comparator)
5.5
6
IS- (mA)
IS+ (mA)
4
3
VS=±5V
VSD=5V
VIN=50mV
TA=25°C
2
1
1
2
3
4
90
5
6
4
3.5
3
7
0
1
2
3
4
5
6
7
30
50
70
90
VS- (V)
Input Bias Current vs Temperature
Offset Voltage vs Temperature
6
0.7
0.6
5
0.5
0.4
VOS (mV)
4
IB (µA)
70
4.5
VS+ (V)
3
2
0.3
0.2
0.1
0
-0.1
1
0
-50
50
VS=±5V
VSD=5V
VIN=50mV
TA=25°C
5
0
30
Negative Supply Current vs Negative Supply Voltage
(per comparator)
5
0
10
Temperature (°C)
Temperature (°C)
-0.2
-30
-10
10
30
50
70
-0.3
-50
90
Temperature (°C)
-30
-10
10
Temperature (°C)
3
EL5283C - Preliminary
EL5283C - Preliminary
Dual and Window 8ns High-Speed Comparators
Dual and Window 8ns High-Speed Comparators
Typical Performance Curves
9
8.5
Delay Time (ns)
12
VS=±5V
VSD=5V
VIN=1V Step
RL=2.2kΩ
Propagation Delay vs Load Capacitance
VIN=1V Step
VS=±5V
VSD=5V
RL=2.2kΩ
VIN=1V Step
VOD=50mV
11
Tpd+
8
Delay Time (ns)
10
Propagation Delay vs Overdrive
VIN=1V Step
9.5
7.5
7
Tpd-
6.5
6
10
Tpd+
9
Tpd-
8
7
5.5
5
0
100
200
300
400
500
6
0
600
20
40
60
VOD (mV)
Propagation Delay vs Supply Voltage
VIN=1V Step
9
8.5
Delay Time (ns)
10
VSD=VS+
VIN=1V Step
VOD=50mV
RL=2.2kΩ
9.5
VS=±5V
VSD=5V
VIN=1V Step
RL=2.2kΩ
9
8
Tpd+
7
Tpd-
6.5
120
Tpd+
8.5
8
7.5
Tpd-
7
6
6.5
5.5
5
4
4.5
5
5.5
6
0
6
0.2
0.4
0.6
0.8
Propagation Delay vs Overdrive
VIN=5VP-P Step
10
20
VS=±5V
VSD=5V
RL=2.2kΩ
VIN=5V Step
16
Tpd+
9.5
9
Tpd-
8.5
14
7.5
6
1
1.5
1.6
1.8
2
2
2.5
4
0
3
VOD (V)
VS=±5V
VSD=5V
RL=2.2kΩ
VIN=1V Step
VOD=50mV
Tpd+
10
8
0.5
1.4
12
8
7
0
1.2
Propagation Delay vs Source Resistance
VIN=1V Step
18
Delay Time (ns)
10.5
1
VOD (mV)
±VS (V)
11
100
Propagation Delay vs Overdrive
VIN=3VP-P Step
9.5
7.5
80
CLOAD (pF)
Delay Time (ns)
10
Delay Time (ns)
EL5283C - Preliminary
EL5283C - Preliminary
Tpd-
0.2
0.4
0.6
0.8
1
Source Resistance (kΩ)
4
1.2
1.4
1.6
Typical Performance Curves
Output Low Voltage vs Load Current
Output High Voltage vs Load Current
0.31
4.75
0.27
4.65
VS=±5V
VSD=5V
VIN=50mV
TA=85°C
TA=25°C
0.23
TA=-40°C
0.19
0.15
Output High Voltage (V)
Output Low Voltage (V)
4.7
0
2
4
VS=±5V
VSD=5V
VIN=-50mV
6
8
TA=-40°C
4.6
TA=25°C
4.55
4.5
TA=85°C
4.45
4.4
4.35
4.3
10
0
2
Load Current (mA)
Digital Supply Current vs Input Switching Frequency (per
comparator)
VS=±5V
T=25°C
ISD (mA)
40
0.6
30
20
VSD=3V
10
0
6
8
10
Package Power Dissipation vs Ambient Temp.
JEDEC JESD51-3 Low Effective Thermal Conductivity Test
486mW
0.5
VSD=5V
Power Dissipation (W)
50
4
Load Current (mA)
0.4
20
0.3
MS
OP
10
C/
W
6°
0.2
0.1
0
5
10
15
20
Frequency (MHz)
25
0
30
0
25
50
75 85
Ambient Temperature (°C)
Output with 30MHz Input
VIN=3VP-P
Output with 30MHz Input
VIN=1VP-P
VIN=1VP-P VS=±5V
FIN=30MHz VSD=5V
VIN=3VP-P VS=±5V
FIN=30MHz VSD=5V
VO
VO
VIN
VIN
1V
2V
100
2V
20ns
5
2V
20ns
125
EL5283C - Preliminary
EL5283C - Preliminary
Dual and Window 8ns High-Speed Comparators
EL5283C - Preliminary
EL5283C - Preliminary
Dual and Window 8ns High-Speed Comparators
Timing Diagram
Compare
Compare
Latch
Enable
Input
1.4V
Latch
Latch
Differential
Input
Voltage
ts
Latch
th
tpw(D)
VIN
VOS
VDD
tpd-
td+(D)
Comparator
Output
2.4V
Definition of Terms
Terms
Definition
VOS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
VIN
Input Voltage Pulse Amplitude - Usually set to 100mV for comparator specifications
VOD
Input Voltage Overdrive - Usually set to 5mV and in opposite polarity to VIN for comparator specifications
tpd+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output low to high transition
tpd-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output high to low transition
td+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a low to high transition
td-
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a high to low transition
ts
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in
order to be acquired and held at the outputs
th
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in
order to be acquired and held at the output
tpw (D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
change
6
Pin Descriptions
Pin Number
Pin Name
1
VS+
Positive supply voltage
Function
2
VREFH
Upper voltage reference
Equivalent Circuit
VS+
VREF
IN
VSCircuit 4
3
IN
Input
(Reference Circuit 4)
4
VREFL
Lower voltage reference
(Reference Circuit 4)
5
VS-
Negative supply voltage
Digital ground
6
GDN
7
OUTL
Low output
(Reference Circuit 2)
8
LATCH
Latch
(Reference Circuit 3)
9
OUTH
High output
(Reference Circuit 2)
10
VSD
Digital supply voltage
Applications Information
Power Supplies and Circuit Layout
Input Voltage Considerations
The EL5283C comparator operates with single and dual
supply with 5V to 12V between VS+ and VS-. The output side of the comparators is supplied by a single
supply from 2.7V to 5V. The rail to rail output swing
enables direct connection of the comparator to both
CMOS and TTL logic circuits. As with many high speed
devices, the supplies must be well bypassed. Elantec recommends a 4.7µF tantalum in parallel with a 0.1µF
ceramic. These should be placed as close as possible to
the supply pins. Keep all leads short to reduce stray
capacitance and lead inductance. This will also minimize unwanted parasitic feedback around the
comparator. The device should be soldered directly to
the PC board instead of using a socket. Use a PC board
with a good, unbroken low inductance ground plane.
Good ground plane construction techniques enhance stability of the comparators.
The EL5283C input range is specified from 0.1V below
VS - to 2.25V below VS +. The criterion for the input
limit is that the output still responds correctly to a small
differential input signal. The differential input stage is a
pair of PNP transistors, therefore, the input bias current
flows out of the device. When either input signal falls
below the negative input voltage limit, the parasitic PN
junction formed by the substrate and the base of the PNP
will turn on, resulting in a significant increase of input
bias current. If one of the inputs goes above the positive
input voltage limit, the output will still maintain the correct logic level as long as the other input stays within the
input range. However, the propagation delay will
increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differential voltages greater than the supply voltage should be
avoided to prevent damages to the input stage. Inputs of
unused channels should not be left floating. They should
be driven to a known state. For example, one input can
7
EL5283C - Preliminary
EL5283C - Preliminary
Dual and Window 8ns High-Speed Comparators
EL5283C - Preliminary
EL5283C - Preliminary
Dual and Window 8ns High-Speed Comparators
be tied to ground and the other input can be connected to
some voltage reference (like ±100mV) to avoid oscillation in the output due to unwanted output to input
feedback.
An approximate equation for the device power dissipation is as follows. Assume the power dissipation in the
load is very small:
P DISS = ( V S × I S + V SD × I SD ) × N
Input Slew Rate
Most high speed comparators oscillate when the voltage
of one of the inputs is close to or equal to the voltage on
the other input due to noise or undesirable feedback. For
clean output waveform, the input must meet certain minimum slew rate requirements. In some applications, it
may be helpful to apply some positive feedback (hysteresis) between the output and the positive input. The
hysteresis effectively causes one comparator's input
voltage to move quickly past the other, thus taking the
input out of the region where oscillation occurs. For the
EL5283C, the propagation delay increases when the
input slew rate increases for low overdrive voltages.
With high overdrive voltages, the propagation delay
does not change much with the input slew rate.
where:
VS is the analog supply voltage from VS+ to VSIS is the analog quiescent supply current per comparator
VSD is the digital supply voltage from VSD to ground
ISD is the digital supply current per comparator
N is the number of comparators in the package
ISD strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipation, the maximum junction temperature can be
determined as follows:
Latch Pin Dynamics
T JMAX = T MAX + Θ JA × P DISS
The EL5283C contains a “transparent” latch for each
channel. The latch pin is designed to be driven with
either a TTL or CMOS output. When the latch is connected to a logic high level or left floating, the
comparator is transparent and immediately responds to
the changes at the input terminals. When the latch is
switched to a logic low level, the comparator output
latches remains latched to its value just before the latch
high-to-low transition. To guarantee data retention, the
input signal must remain the same state at least 1ns (hold
time) after the latch goes low and at least 2ns (setup
time) before the latch goes low. When the latch goes
high, the new data will appear at the output in approximately 8ns (latch propagation delay).
where:
TMAX is the maximum ambient temperature
θJA is the thermal resistance of the package
Window Detector
If VIN is in the range of VREFL < VIN < V REFH, both outputs go high and the input in range is high. If VIN is out
of the range set by VREFH and VREFL, the input in range
is low.
VREFH
Power Dissipation
+
-
Input In
Range
VIN
When switching at high speeds, the comparator's drive
capability is limited by the rise in junction temperature
caused by the internal power dissipation. For reliable
operation, the junction temperature must be kept below
TJMAX (125°C).
VREFL
8
OUTH
+
-
OUTL
EL5283C - Preliminary
EL5283C - Preliminary
Dual and Window 8ns High-Speed Comparators
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
September 6, 2001
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.
Elantec Semiconductor, Inc.
675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: (408) 945-1323
(888) ELANTEC
Fax:
(408) 945-9305
European Office: +44-118-977-6020
Japan Technical Center: +81-45-682-5820
9
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