TI CD74HC161 High speed cmos logic presettable counter Datasheet

[ /Title
(CD74
HC161
,
CD74
HCT16
1,
CD74
HC163
,
CD74
HCT16
3)
/Subject
(High
Speed
CMOS
Logic
Presettable
Counte
rs)
/Autho
r ()
/Keywords
(High
Speed
CMOS
Logic
Presettable
Counte
rs,
High
Speed
Data sheet acquired from Harris Semiconductor
SCHS154
CD74HC161, CD74HCT161,
CD74HC163, CD74HCT163
High Speed CMOS Logic
Presettable Counters
February 1998
Features
Description
• CD74HC161, CD74HCT161 4-Bit Binary Counter,
Asynchronous Reset
The Harris CD74HC161, CD74HCT161, CD74HC163 and
CD74HCT163 are presettable synchronous counters that
feature look-ahead carry logic for use in high-speed
counting applications. The CD74HC161 and CD74HCT161
are asynchronous reset decade and binary counters,
respectively; the CD74HC163 and CD74HCT163 devices
decade and binary counters, respectively and are reset
synchronously with the clock. Counting and parallel
presetting are both accomplished synchronously with the
negative-to-positive transition of the clock.
• CD74HC163, CD74HCT163 4-Bit Binary Counter,
Synchronous Reset
• Synchronous Counting and Loading
• Two Count Enable Inputs for n-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
A low level on the synchronous parallel enable input, SPE,
disables counting operation and allows data at the P0 to P3
inputs to be loaded into the counter (provided that the
setup and hold requirements for SPE are met).
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
All counters are reset with a low level on the Master Reset
input, MR. In the CD74HC163 and CD74HCT163 counters
(synchronous reset types), the requirements for setup and
hold time with respect to the clock must be met.
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
Two count enables, PE and TE, in each counter are
provided for n-bit cascading. In all counters reset action
occurs regardless of the level of the SPE, PE and TE inputs
(and the clock input, CP, in the CD74HC161 and
CD74HCT161 types).
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
If a decade counter is preset to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
The look-ahead carry feature simplifies serial cascading of
the counters. Both count enable inputs (PE and TE) must
be high to count. The TE input is gated with the Q outputs
of all four stages so that at the maximum count the terminal
count (TC) output goes high for one clock period. This TC
pulse is used to enable the next cascaded stage.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
PKG.
NO.
CD74HC161E
-55 to 125
16 Ld PDIP
E16.3
CD74HC161M
-55 to 125
16 Ld SOIC
M16.15
CD74HC163E
-55 to 125
16 Ld PDIP
E16.3
CD74HC163M
-55 to 125
16 Ld SOIC
M16.15
CD74HCT161E
-55 to 125
16 Ld PDIP
E16.3
CD74HCT161M
-55 to 125
16 Ld SOIC
M16.15
MR 1
16 VCC
CP 2
15 TC
P0 3
14 Q0
P1 4
13 Q1
CD74HCT163E
-55 to 125
16 Ld PDIP
E16.3
CD74HCT163M
-55 to 125
16 Ld SOIC
M16.15
Pinout
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
(PDIP, SOIC)
TOP VIEW
NOTES:
P2 5
12 Q2
1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
P3 6
11 Q3
2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris
customer service for ordering information.
PE 7
10 TE
GND 8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
9 SPE
File Number
1550.1
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Functional Diagram
P0
3
SPE
CP
MR
PE
TE
P1
4
P2
5
P3
6
9
14
2
13
1
12
7
11
10
15
Q0
Q1
Q2
Q3
TC
MODE SELECT - FUNCTION TABLE FOR CD74HC/HCT161
INPUTS
OPERATING MODE
OUTPUTS
MR
CP
PE
TE
SPE
Pn
Qn
TC
Reset (Clear)
L
X
X
X
X
X
L
L
Parallel Load
H
↑
X
X
l
l
L
L
H
↑
X
X
l
h
H
(Note 3)
Count
H
↑
h
h
h (Note 5)
X
Count
(Note 3)
Inhibit
H
X
I (Note 4)
X
h (Note 5)
X
qn
(Note 3)
H
X
X
I (Note 4)
h (Note 5)
X
qn
L
MODE SELECT - FUNCTION TABLE FOR CD74HC/HCT163
INPUTS
OPERATING MODE
OUTPUTS
MR
CP
PE
TE
SPE
Pn
Qn
TC
Reset (Clear)
l
↑
X
X
X
X
L
L
Parallel Load
h (Note 5)
↑
X
X
l
l
L
L
h (Note 5)
↑
X
X
l
h
H
(Note 3)
Count
h (Note 5)
↑
h
h
h (Note 5)
X
Count
(Note 3)
Inhibit
h (Note 5)
X
I (Note 4)
X
h (Note 5)
X
qn
(Note 3)
h (Note 5)
X
X
I (Note 4)
h (Note 5)
X
qn
L
NOTE: H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High
clock transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don’t Care; q = Lower case letters indicate
the state of the referenced output prior to the Low-to-High clock transition; ↑ = Low-to-High clock transition.
3. The TC output is High when TE is High and the counter is at Terminal Count (HHHH for CD74HC/HCT161 and CD74HC/HCT163).
4. The High-to-Low transition of PE or TE on the CD74HC/HCT161 and the CD74HC/HCT163 should only occur while CP is HIGH for conventional operation.
5. The Low-to-High transition of SPE on the CD74HC/HCT161 and SPE or MR on the CD74HC/HCT163 should only occur while CP is HIGH
for conventional operation.
2
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 6)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
6. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
VIH
-
-
2
1.5
-
-
1.5
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
-
1.5
-
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC or
GND
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
-
6
-
-
±0.1
-
±1
-
±1
µA
3
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
High Level Input
Voltage
VIH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
VIL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
VOH
VIH or VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
PARAMETER
Quiescent Device
Current
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC and
GND
0
5.5
-
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
∆ICC
(Note)
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
P0 - P3
0.25
PE
0.65
CP
1.05
MR
0.8
SPE
0.5
TE
1.05
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
fMAX
-
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
24
-
20
-
MHz
6
35
-
-
28
-
24
-
MHz
HC TYPES
Maximum CP Frequency
(Note7)
4
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Prerequisite For Switching Specifications
PARAMETER
CP Width (Low)
MR Pulse Width (161)
Setup Time, Pn to CP
Setup Time, PE or TE to CP
Setup Time, SPE to CP
Setup Time, MR to CP (163)
Hold Time, PN to CP
Hold Time, TE or PE to CP
Hold Time, SPE to CP
Recovery Time, MR to CP (161)
(Continued)
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tW(L)
-
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
100
-
-
125
-
150
-
ns
4.5
20
-
-
25
-
30
-
ns
6
17
-
-
21
-
26
-
ns
2
60
-
-
75
-
90
-
ns
4.5
12
-
-
15
-
18
-
ns
6
10
-
-
13
-
15
-
ns
2
50
-
-
65
-
75
-
ns
4.5
10
-
-
13
-
15
-
ns
6
9
-
-
11
-
13
-
ns
2
60
-
-
75
-
90
-
ns
tW
tSU
tSU
tSU
tSU
tH
tH
tH
tREC
-
-
-
-
-
-
-
-
-
4.5
12
-
-
15
-
18
-
ns
6
10
-
-
13
-
15
-
ns
2
65
-
-
80
-
100
-
ns
4.5
13
-
-
16
-
20
-
ns
6
11
-
-
14
-
17
-
ns
2
3
-
-
3
-
3
-
ns
4.5
3
-
-
3
-
3
-
ns
6
3
-
-
3
-
3
-
ns
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
6
0
-
-
0
-
0
-
ns
2
0
-
-
0
-
0
-
ns
4.5
0
-
-
0
-
0
-
ns
6
0
-
-
0
-
0
-
ns
2
75
-
-
95
-
110
-
ns
4.5
15
-
-
19
-
22
-
ns
6
13
-
-
16
-
19
-
ns
HCT TYPES
Maximum CP Frequency
fMAX
-
4.5
30
-
-
24
-
20
-
MHz
CP Width (Low) (Note 7)
tW(L)
-
4.5
16
-
-
20
-
24
-
ns
MR Pulse Width (161)
tW
-
4.5
20
-
-
25
-
30
-
ns
Setup Time, Pn to CP
tSU
-
4.5
10
-
-
13
-
15
-
ns
Setup Time, PE or TE to CP
tSU
-
4.5
13
-
-
16
-
20
-
ns
Setup Time, SPE to CP
tSU
-
4.5
12
-
-
15
-
18
-
ns
Setup Time, MR to CP (163)
tSU
-
4.5
13
-
-
16
-
20
-
ns
Hold Time, PN to CP
tH
-
4.5
5
-
-
5
-
5
-
ns
Hold Time, TE or PE to CP
tH
-
4.5
3
-
-
3
-
3
-
ns
5
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Prerequisite For Switching Specifications
PARAMETER
Hold Time, SPE to CP
Recovery Time, MR to CP (161)
(Continued)
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
tH
-
4.5
3
-
-
3
-
3
-
ns
tREC
-
4.5
15
-
-
19
-
22
-
ns
NOTE:
7. Applies to non-cascaded operation only. With cascaded counters clock to terminal count propagation delays, count enables (PE or TE)to-clock setup times, and count enables (PE or TE)-to-clock hold times determine maximum clock frequency. For example with these HC
devices:
1
1
f MAX (CP) = ----------------------------------------------------------------------------------------------------------------------------------------------------- = ----------------------------- ≈ 21MHz ( min )
CP-to-TC prop. delay + TE-to-CP setup + TE-to-CP Hold 37 + 10 + 0
Switching Specifications
CL = 50pF, Input tr, tf = 6ns
-40oC TO
85oC
25oC
PARAMETER
SYMBOL
TEST
CONDITIONS
tPHL, tPLH
CL = 50pF
-55oC TO
125oC
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
185
-
230
-
280
ns
4.5
-
-
37
-
46
-
56
ns
CL = 15pF
5
-
15
-
-
-
-
-
ns
CL = 50pF
6
-
-
31
-
39
-
48
ns
CL = 50pF
2
-
-
185
-
230
-
280
ns
4.5
-
-
37
-
46
-
56
ns
CL = 15pF
5
-
15
-
-
-
-
-
ns
CL = 50pF
6
-
-
31
-
39
-
48
ns
CL = 50pF
2
-
-
120
-
150
-
180
ns
4.5
-
-
24
-
30
-
36
ns
CL = 15pF
5
-
9
-
-
-
-
-
ns
CL = 50pF
6
-
-
20
-
26
-
31
ns
CL = 50pF
2
-
-
210
-
265
-
315
ns
4.5
-
-
42
-
53
-
63
ns
CL = 15pF
5
-
18
-
-
-
-
-
ns
CL = 50pF
6
-
-
36
-
45
-
54
ns
CL = 50pF
2
-
-
210
-
265
-
315
ns
4.5
-
-
42
-
53
-
63
ns
CL = 50pF
6
-
-
36
-
45
-
54
ns
CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
5
-
60
-
-
-
-
-
pF
HC TYPES
Propagation Delay
CP to TC
CP to Qn
TE to TC
MR to Qn (161)
MR to TC (161)
Output Transition Time
Power Dissipation Capacitance
(Notes 8, 9)
tPHL, tPLH
tPHL, tPLH
tPHL
tPHL
tTHL, tTLH
CPD
-
6
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Switching Specifications
CL = 50pF, Input tr, tf = 6ns (Continued)
-40oC TO
85oC
25oC
PARAMETER
Input Capacitance
-55oC TO
125oC
SYMBOL
TEST
CONDITIONS
VCC (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
CIN
CL = 50pF
-
10
-
10
-
10
-
10
pF
tPHL, tPLH
CL = 50pF
4.5
-
-
42
-
53
-
63
ns
CL = 15pF
5
-
18
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
39
-
49
-
59
ns
CL = 15pF
5
-
16
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
32
-
40
-
48
ns
CL = 15pF
5
-
13
-
-
-
-
-
ns
CL = 50pF
4.5
-
-
50
-
63
-
75
ns
CL = 15pF
5
-
21
-
-
-
-
-
ns
HCT TYPES
Propagation Delay
CP to TC
CP to Qn
TE to TC
MR to Qn (161)
tPHL, tPLH
tPHL, tPLH
tPHL
MR to TC (161)
tPHL
CL = 50pF
4.5
-
-
50
-
63
-
75
ns
Output Transition Time
tTHL, tTLH
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Power Dissipation Capacitance
(Notes 6, 7)
CPD
-
5
-
63
-
-
-
-
-
pF
Input Capacitance
CIN
CL = 50pF
-
10
-
10
-
10
-
10
pF
NOTES:
8. CPD is used to determine the dynamic power consumption, per package.
9. PD = CPD VCC2 fi + ∑(CL VCC2 fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
7
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Timing Diagram
MASTER RESET (161)
(ASYNCHRONOUS)
MASTER RESET (163)
(SYNCHRONOUS)
SPE
P0
PRESET
DATA
INPUTS
P1
P2
P3
CP (161)
CP (163)
COUNT
ENABLES
PE
TE
Q0
Q1
OUTPUTS
Q2
Q3
TC
12
RESET
13
14
15
0
COUNT
PRESET
Sequence illustrated on waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit.
8
1
2
INHIBIT
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Test Circuits and Waveforms
tWL + tWH =
tfCL
trCL
50%
10%
10%
tf = 6ns
tr = 6ns
tTLH
90%
INVERTING
OUTPUT
tPHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
trCL
tfCL
VCC
tfCL
GND
1.3V
0.3V
GND
tH(H)
tH(L)
VCC
DATA
INPUT
3V
2.7V
CLOCK
INPUT
50%
tH(H)
tTLH
1.3V
10%
tPLH
10%
GND
tTHL
90%
50%
10%
90%
3V
2.7V
1.3V
0.3V
GND
tTHL
trCL
tWH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
INPUT
INVERTING
OUTPUT
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
VCC
90%
50%
10%
1.3V
1.3V
tWL
tf = 6ns
tPHL
1.3V
0.3V
tWH
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
INPUT
2.7V
0.3V
GND
tr = 6ns
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
I
fCL
3V
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tREM
VCC
SET, RESET
OR PRESET
tfCL = 6ns
CLOCK
50%
50%
tWL
CLOCK
INPUT
tWL + tWH =
trCL = 6ns
VCC
90%
CLOCK
I
fCL
CL
50pF
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
9
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