EMC EM19101M 8-bit 5 msps a/d converter (cmos) Datasheet

EM19101
EM19101
8-BIT 5
8-BIT 5A/D
MSPS
A/D CONVERTER
(CMOS)
MSPS
CONVERTER
(CMOS)
GENERAL DESCRIPTION
EM19101 is a 8-bit CMOS A/D converter for scanner use. The adoption of a 2-step parallel system achieves low
consumption at a maximum conversion speed of 7 MSPS.
FEATURES
•
•
•
•
•
•
•
7MSPS maximum conversion speed
Build-in sampling and hold circuit
Internal self-bias reference voltage
45 mW very low power dissipation at 5MSPS
+5V single power supply
Available in 24 pin SOP
Series
EM19101M for 300 mil SOP
EM19101S for 209 mil SOP
APPLICATION
Scanner and a wide range of fields where high speed A/D conversion is required in the digital communication.
PIN ASSIGNMENT
EM19101
OE
DVSS
D0
D1
D2
D3
D4
D5
D6
D7
DVDD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DVSS
VRB
VRBS
AVSS
AVSS
VIN
AVDD
VRT
VRTS
AVDD
AVDD
DVDD
FUNCTIONAL BLOCK DIAGRAM
24
DV S S
2
23
VRB
3
22
V RBS
21
AVSS
/O E
1
DVS S
D0
D1
Reference voltage
4
Lower data
latches
Lower encoder
(4bit)
Lower
Comparators with
S/ H (4bit)
D2
5
20
AVSS
D3
6
19
VI N
D4
7
18
AV DD
D5
8
17
V RT
D6
9
16
V RT S
D7
10
15
AV DD
14
AV DD
13
DV DD
Upper data
latches
Upper encoder
(4bit)
DV DD 1 1
CL K 1 2
Clock generator
* This specification are subject to be changed without notice.
Upper
Comparators with
S/ H (4bit)
4.23.1997
1
EM19101
8-BIT 5 MSPS A/D CONVERTER (CMOS)
PIN DESCRIPTIONS
Symbol
Function
OE
DVSS
D0
D1
D2
D3
D4
D5
D6
D7
DVDD
CLK
DVDD
AVDD
AVDD
VRTS
VRT
AVDD
VIN
AVSS
AVSS
VRBS
VRB
DVSS
Output enable
Digital ground
Data output bit 0 (LSB)
Data output bit 1
Data output bit 2
Data output bit 3
Data output bit 4
Data output bit 5
Data output bit 6
Data output bit 7 (MSB)
Digital power supply
Clock input
Digital power supply
Analog power supply
Analog power supply
Top internal reference voltage
Top reference voltaget
Analog power supply
Analog input voltage
Analog ground
Analog ground
Bottom internal reference voltage
Bottom reference voltage
Digital ground
TIMING DIAGRAM
Exte rnal
C lo c k
Tra ns f er
Cl o ck
N+2
N
N+1
Analog input
Dat a o u t pu t
N-3
N-2
* This specification are subject to be changed without notice.
N+4
N+3
N-1
N
N+1
N+2
4.23.1997
2
EM19101
8-BIT 5 MSPS A/D CONVERTER (CMOS)
OUTPUT CODING
Step
0
1
2
....
124
125
....
254
255
Analog Input (V)
0.607815
0.607815~0.6156250
0.6156250~0.6234375
....
1.6000000~1.6078125
1.6078125~1.6156250
....
2.5843750~2.5921875
2.5921875~
Digital Output Code
00000000
00000001
00000010
....
10000000
10000001
....
11111110
11111111
Conditions
VRB=0.6V
VRT=2.6V
1LSB=7.8125mV
ABSOLUTE MAXIMUM RATINGS (TA=25°C)
Items
Supply voltage
Operating temperature
Input voltage
Ref, Input voltage
Sym.
VDD
TOPR
VIN
VRT,VRB
Rating
Unit
7
-20 to +65
VSS to VDD
VSS to VDD
V
°C
V
V
Rating
Unit
Recommended Poerating Conditions
Items
Supply voltage
Reference input voltage
Analog input voltage
Sym.
AVDD,AVSS
DVDD,DVSS
|DGND-AGND|
VRB
VRT
VRT - VRB
VIN
4.75 TO 5.25
V
0 to 100
0 and above
VDD and below
1.0 to 3.0
VRB to VRT
mV
V
V
V
V
(FC=5MPS,VDD=5V,VRB=0.5V,VRT=2.5V,Ta=25°C External clock duty=40 to 60%)
Parameter
Sym.
Conditions
Min. Typ. Max.
Maximum Conversion Speed
FC
Vin=0.6V to 2.6V fin=1kHz ramp
5
FC=5MSPS NTSC ramp wave input
10
15
Supply current
IDD
Reference pin current
IREF
5.7
8.0 9.1
Analog input bandwidth
BW
1
VIN=1.5V+0.07Vrms
11
Analog input capacitance
CIN
Reference resistance
RREF
220 250 350
Short VRB and VRBS
0.55 0.6 0.65
Internal bias
VRB
VRT-VRB Short VRT and VRTS
1.9
2.0 2.1
-10
-35 -60
Offset Voltage
EOT
EOB
0
15
45
Digital input voltage
VIH
4.0
1.0
VIL
Digital input current
IIH
VDD=max.
VIH=V DD
5
VIL=0V
5
I IL
* This specification are subject to be changed without notice.
Unit
MSPS
mA
mA
MHz
pF
Ω
V
mV
V
uA
4.23.1997
3
EM19101
8-BIT 5 MSPS A/D CONVERTER (CMOS)
Parameter
Digital output current
Digital output current
Sym.
IOH
IOL
IOZH
Output data delay
Integral nonlinearity
Differential nonlinearity
Differential gain error
TDL
EL
ED
DG
Differential phase error
Aperture jitter
Sampling delay
Conditions
OE=VSS,
VDD=min.
OE=VDD,
VOH=VDD-0.5V
VOL=0.4V
VOH=VDD
VOL=0V
FC=5MSPS VIN=0.6V to 2.6V
FC=5MSPS VIN=0.6V to 2.6V
NTSC 40 IRE mod ramp,
FC=14.3MSPS
DP
tAJ
tDS
Min. Typ. Max. Unit
-1.1
mA
3.7
16
uA
16
25
40
ns
0.5 1.3 LSB
±0.3 ±0.5 LSB
1.0
0.5
30
4
%
°C
ps
ns
Application Note
VDD,VSS
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the
respective GND’s.
Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However
it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When
driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by
inserting a resistance of about 100Ω in series between the amplifier output and A/D input.
Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate
it from other circuits
Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VRT
and VRTS, VRB and VRBS, the self bias function that generates VRT=2.6V and VRB=0.6V, is activated.
Timing
Analog input is sampled with the falling edge of external clock and output as digital data with a delay of 2.5
clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 25ns.
OE pin
By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained.
* This specification are subject to be changed without notice.
4.23.1997
4
EM19101
8-BIT 5 MSPS A/D CONVERTER (CMOS)
About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up
due to the voltage difference between AVDD and DVDD pins when power is ON.
* This specification are subject to be changed without notice.
4.23.1997
5
EM19101
8-BIT 5 MSPS A/D CONVERTER (CMOS)
Application Circuit
U2
U2
U3
* This specification are subject to be changed without notice.
4.23.1997
6
Similar pages