bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 800mA, Single Cell Li-Ion Battery Charger With Automatic Adaptor/USB Detection Check for Samples: bq24050 bq24052 bq24055 FEATURES • 1 • • CHARGING – 1% Charge Voltage Accuracy – 10% Charge Current Accuracy – Pin Selectable USB 100mA and 500mA Maximum Input Current Limit – Programmable Termination and Precharge Threshold PROTECTION – 30V Input Rating; with 6.6V Input Overvoltage Protection – Input Voltage Dynamic Power Management – 125°C Thermal Regulation; 150°C Thermal Shutdown Protection – OUT Short-Circuit Protection and ISET short detection – Operation over JEITA Range via Battery NTC - ½ Fast-Charge-Current at Cold, 4.06V at Hot – Fixed 10 Hour Safety Timer SYSTEM – Auto Input Source Detection (D+,D– Pins) – No Device Transceiver Required – USB Friendly – Automatic Termination and Timer Disable Mode (TTDM) for Absent Battery Pack With Thermistor – Status Indication – Charging/Done – Available in Small 2×2mm2 DFN-10 or 2×3mm2 DFN-12 Packages APPLICATIONS • • • • Smart Phones PDAs MP3 Players Low-Power Handheld Devices DESCRIPTION The bq2405x series of devices are highly integrated Li-ion linear chargers devices targeted at space-limited portable applications. The devices operate from either a USB port or AC adapter. The high input voltage range with input overvoltage protection supports low-cost unregulated adapters. The bq2405x has a single power output that charges the battery. A system load can be placed in parallel with the battery as long as the average system load does not keep the battery from charging fully during the 10 hour safety timer. The battery is charged in three phases: conditioning, constant current and constant voltage. In all charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if an internal temperature threshold is exceeded. (Description continued on next page) bq24050/2 Adaptor DC+ 1 IN OUT System Load 10 1.5kW GND 1mF 2 ISET TS 9 3 VSS CHG 8 4 PRETERM ISET2 7 5 D+ 6 1kW OR D- Battery Pack + 1mF VDD 2kW TTDM USB Port ISET/100/500 mA VBUS GND GND D+ D+ D- D- Host Disconnect after Detection 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The charger power stage and charge current sense functions are fully integrated. The charger function has high accuracy current and voltage regulation loops, charge status display, and charge termination. The precharge current and termination current threshold are programmed via an external resistor. The fast charge current value is also programmable via an external resistor. AVAILABLE OPTIONS VO(REG) VOVP RNTC PG PACKAGE 2 DEVICES MARKING CVC 4.2 V 6.6 V 10 kΩ No 10 PIN 2 × 2mm DFN bq24050 4.2 V 6.6 V 100 kΩ No 10 PIN 2 × 2mm 2 DFN bq24052 CGT 4.2 V 6.6 V 10 kΩ Yes 12 PIN 2 × 3mm 2 DFN bq24055 CGU ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Input Voltage VALUE UNIT IN (with respect to VSS) –0.3 to 30 V OUT (with respect to VSS) –0.3 to 7 V PRE-TERM, ISET, ISET2, TS, CHG, PG, D+, D–, (with respect to VSS) –0.3 to 7 V A Input Current IN 1.25 Output Current (Continuous) OUT 1.25 A Output Sink Current CHG 15 mA 8 contact 15 Air kV 1µF between IN and GND, 1µF between TS and GND, 2µF between OUT and GND, x5R Ceramic or equivalent ESD Electrostatic discharge (IEC61000-4-2) (2) TJ Junction temperature –40 to 150 °C TSTG Storage temperature –65 to 150 °C (1) (2) IN, OUT, TS Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. The test was performed on IC pins that may potentially be exposed to the customer at the product level. The bq2405x IC requires a minimum of the listed capacitance, external to the IC, to pass the ESD test. The D+ D- lines require clamp diodes such as CM1213A-02SR from CMD to protect the IC for this testing. PACKAGE DISSIPATION RATINGS (1) (1) (2) 2 (2) PACKAGE RθJA RθJC TA ≤ 25°C POWER RATING DERATING FACTOR TA > 25°C 2 × 2 mm2 60°C/W 8.8°C/W 1.66W 16.6mW/°C 2 × 3 mm2 58°C/W 5.3°C/W 1.72W 17.2mW/°C For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is connected to the ground plane by a 2×3 via matrix Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 RECOMMENDED OPERATING CONDITIONS (1) IN voltage range VIN IN operating voltage range, Restricted by VDPM and VOVP MIN NOM 3.5 28 UNIT V 4.45 6.45 V 0.8 A IIN Input current, IN pin IOUT Current, OUT pin 0.8 A TJ Junction temperature 0 125 °C RPRE-TERM Programs precharge and termination current thresholds 1 10 kΩ RISET Fast-charge current programming resistor 0.675 49.9 kΩ 1.66 258 kΩ 24 885 kΩ 10k NTC thermistor range without entering TTDM, bq24050/55 RTS (1) 100k NTC thermistor range without entering TTDM, bq24052 Operation with VIN less than 4.5V or in drop-out may result in reduced performance. ELECTRICAL CHARACTERISTICS Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT Undervoltage lock-out Exit VIN: 0V → 4V Update based on sim/char 3.15 3.3 3.45 V VHYS_UVLO Hysteresis on VUVLO_RISE falling VIN: 4V→0V, VUVLO_FALL = VUVLO_RISE –VHYS-UVLO 175 230 280 mV VIN-DT Input power good detection threshold is VOUT + VIN-DT (Input power good if VIN > VOUT + VIN-DT); VOUT = 3.6V, VIN: 3.5V → 4V 30 80 145 mV VHYS-INDT Hysteresis on VIN-DT falling VOUT = 3.6V, VIN: 4V → 3.5V 31 mV tDGL(PG_PWR) Deglitch time on exiting sleep. Time measured from VIN: 0V → 5V 1μs rise-time to PG = low, VOUT = 3.6V 45 μs tDGL(PG_NO- Deglitch time on VHYS-INDT power down. Same as entering sleep. Time measured from VIN: 5V → 3.2V 1μs fall-time to PG = High Z, VOUT = 3.6V 29 ms PWR) VOVP Input over-voltage protection threshold VIN: 5V → 7V (50/52/55) tDGL(OVP-SET) Input over-voltage blanking time VIN: 5V → 12V 113 μs VHYS-OVP Hysteresis on OVP VIN: 11V → 5V 95 mV tDGL(OVP-REC) Deglitch time exiting OVP Time measured from VIN: 12V → 5V 1μs fall-time to PG = LO 30 μs VIN-DPM USB/Adaptor low input voltage protection. Restricts lout at VIN-DPM UVLO IIN-USB-CL 6.5 6.65 6.8 Feature active in USB mode; Limit Input Source Current to 50mA; VOUT=3.5V; RISET = 825Ω 4.34 4.4 4.46 Feature active in Adaptor mode; Limit Input Source Current to 50mA; VOUT=3.5V; RISET = 825Ω 4.24 4.3 4.36 V V USB input I-Limit 100mA ISET2 = Float; RISET = 825Ω 85 92 100 USB input I-Limit 500mA ISET2 = High; RISET = 825Ω 430 462 500 280 mA ISET SHORT CIRCUIT TEST RISET_SHORT Highest Resistor value considered a fault (short). Monitored for Iout>90mA Riset: 600Ω → 250Ω, Iout latches off. Cycle power to Reset. USB100 mode. tDGL_SHORT Deglitch time transition from ISET short to Iout disable Clear fault by cycling IN or TS IOUT_CL Maximum OUT current limit Regulation (Clamp) VIN = 5V, VOUT = 3.6V, VISET2 =Low, Riset: 600Ω → 250Ω, Iout latches off after tDGL-SHORT 1.05 0.75 500 1 Ω ms 1.4 A 0.85 V BATTERY SHORT PROTECTION VOUT(SC) OUT pin short-circuit detection threshold/ precharge threshold VOUT:3V → 0.5V, no deglitch VOUT(SC-HYS) OUT pin Short hysteresis Recovery ≥ VOUT(SC) + VOUT(SC-HYS); Rising, no Deglitch IOUT(SC) Source current to OUT pin during short-circuit detection 0.8 77 10 15 mV 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 mA 3 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT QUIESCENT CURRENT IOUT(PDWN) Battery current into OUT pin VIN = 0V 1 IOUT(DONE) OUT pin current, charging terminated VIN = 6V, VOUT > VOUT(REG) 6 IIN(STDBY) Standby current into IN pin TS = LO, VIN ≤ 6V Active supply current, IN pin TS = open, VIN = 6V, TTDM – no load on OUT pin, VOUT > VOUT(REG), IC enabled ICC μA 125 μA 0.8 1 mA BATTERY CHARGER FAST-CHARGE VOUT(REG) Battery regulation voltage VIN =5.5V, IOUT =25mA, VTS-45°C≤ VTS ≤ VTS-0°C 4.16 4.20 4.23 V VO_HT(REG) Battery hot regulation Voltage VIN =5.5V, IOUT =25mA, VTS-60°C≤ VTS ≤ VTS-45°C 4.02 4.06 4.1 V IOUT(RANGE) Programmed Output “fast charge” current range VOUT(REG) > VOUT > VLOWV, VIN = 5V, ISET2=Lo, RISET = 675 to 10.8kΩ 10 800 mA VDO(IN-OUT) Drop-Out, VIN – VOUT Adjust VIN down until IOUT = 0.5A, VOUT = 4.15V, RISET = 675 , ISET2=Lo (Adaptor Mode); Tj ≤ 100°C 500 mV IOUT Output “fast charge” formula VOUT(REG) > VOUT > VLOWV, VIN = 5V, ISET2=Lo KISET Fast charge current factor 325 KISET/RISET A RISET = KISET /IOUT 50 < IOUT < 800 mA 510 540 570 RISET = KISET /IOUT 25 < IOUT < 50 mA 480 527 600 RISET = KISET /IOUT 10 < IOUT < 25 mA 350 520 680 2.4 2.5 2.6 AΩ PRECHARGE – SET BY PRETERM PIN VLOWV Pre-charge to fast-charge transition threshold tDGL1(LOWV) Deglitch time on pre-charge to fast-charge transition 70 μs tDGL2(LOWV) Deglitch time on fast-charge to pre-charge transition 32 ms IPRE-TERM Refer to the Termination Section %PRECHG Pre-Charge Current Level, Default Setting VOUT < VLOWV; RPRE-TERM = High Z (≥13kΩ); RISET = 1k Pre-charge current formula RPRE-TERM = KPRE-CHG (Ω/%) × %PRE-CHG (%) RPRE-TERM/KPRE-CHG VOUT < VLOWV, VIN = 5V, RPRE-TERM = 2k to 10kΩ; RISET = 1080Ω , RPRE-TERM = KPRE-CHG × %IFAST-CHG, where %IFAST-CHG is 20 to 100% 90 100 110 Ω/% VOUT < VLOWV, VIN = 5V, RPRE-TERM = 1k to 2kΩ; RISET = 1080Ω, RPRE-TERM = KPRE-CHG × %IFAST-CHG, where %IFAST-CHG is 10% to 20% 84 100 117 Ω/% KPRE-CHG % Pre-charge Factor 18 20 22 V %IOUT-CC TERMINATION – SET BY PRE-TERM PIN %TERM KTERM Termination Current Threshold, Default Setting VOUT > VRCH; RPRE-TERM = High Z (≥13kΩ); RISET = 1k Termination Current Threshold Formula RPRE-TERM = KTERM (Ω/%) × %TERM (%) % Term Factor IPRE-TERM Current for programming the term. and pre-chg with resistor. ITerm-Start is the initial PRE-TERM curent. %TERM Termination current formula tDGL(TERM) Deglitch time, termination detected ITerm-Start Elevated PRE-TERM current for, tTerm-Start, during start of charge to prevent recharge of full battery, tTerm-Start Elevated termination threshold initially active for tTerm-Start 4 9 10 11 %IOUT-CC RPRE-TERM/ KTERM VOUT > VRCH, VIN = 5V, RPRE-TERM = 2k to 10kΩ ; RISET = 750Ω; KTERM × %IFAST-CHG, where %IFAST-CHG is 10 to 50% 182 VOUT > VRCH, VIN = 5V, RPRE-TERM = 1k to 2kΩ ; RISET = 750Ω; KTERM × %IFAST-CHG, where %IFAST-CHG is 5 to 10% 174 199 224 71 75 81 RPRE-TERM = 2k, VOUT = 4.15V 200 216 Ω/% RTERM/ KTERM Submit Documentation Feedback % 29 80 85 1.25 μA ms 92 μA min Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS (continued) Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RECHARGE OR REFRESH Recharge detection threshold – Normal Temp VIN = 5V, VTS = 0.5V, VOUT: 4.25V → VRCH VO(REG)0.120 VO(REG -0.095 VO(REG)0.070 V Recharge detection threshold – Hot Temp VIN = 5V, VTS = 0.2V, VOUT: 4.15V → VRCH VO_HT(REG) -0.130 VO_HT(REG) -0.105 VO_HT(REG) -0.080 V tDGL1(RCH) Deglitch time, recharge threshold detected VIN = 5V, VTS = 0.5V, VOUT: 4.25V → 3.5V in 1μs; tDGL1(RCH) is time to ISET ramp 29 ms tDGL2(RCH) Deglitch time, recharge threshold detected in OUT-Detect Mode VIN = 5V, VTS = 0.5V, VOUT = 3.5V inserted; tDGL2(RCH) is time to ISET ramp 3.6 ms VRCH BATTERY DETECT ROUTINE (NOTE: In Hot Mode VO(REG) becomes VO_HT(REG)) VREG-BD VOUT Reduced regulation during battery detect IBD-SINK Sink current during VREG-BD tDGL(HI/LOW REG) VO(REG)0.450 VIN = 5V, VTS = 0.5V, Battery Absent VO(REG -0.400 VO(REG)0.350 7 Regulation time at VREG or VREG-BD 10 25 V mA ms VBD-HI High battery detection threshold VIN = 5V, VTS = 0.5V, Battery Absent VO(REG)0.150 VO(REG)0.100 VO(REG)0.050 V VBD-LO Low battery detection threshold VIN = 5V, VTS = 0.5V, Battery Absent VREG-BD +0.050 VREG-BD +0.100 VREG-BD +0.150 V 1700 1940 2250 s 34000 38800 45000 s BATTERY CHARGING TIMERS AND FAULT TIMERS tPRECHG Pre-charge safety timer value Restarts when entering Pre-charge; Always enabled when in pre-charge. tMAXCH Charge safety timer value Clears fault or resets at UVLO, TS ("CE") disable, OUT Short, exiting LOWV and Refresh BATTERY-PACK NTC MONITOR (Note 1); TS pin: bq24050/5: 10k NTC; bq24052: 100k NTC; See TS section for thermistor information INTC-10k NTC bias current; 10k NTC thermsistor, bq24050/5 VTS = 0.3V 48 50 52 μA INTC-100k NTC bias current; 100k NTC thermsistor, bq24052 VTS = 0.3V 4.8 5 5.2 μA INTC-DIS-10k bq24050/5 bias current when Charging is disabled. VTS = 0V 27 30 34 μA INTC-DIS-100k bq24052 bias current when Charging is disabled. VTS = 0V 4.4 5 5.8 μA INTC-FLDBK-10k INTC is reduced prior to entering TTDM to keep cold thermistor from entering TTDM, bq24050/5 VTS: Set to 1.525V 4 5 6.5 μA INTC-FLDBK-100k INTC is reduced prior to entering TTDM to keep cold thermistor from entering TTDM, bq24052 VTS: Set to 1.525V 1.1 1.5 1.9 μA VTTDM(TS) Termination and timer disable mode Threshold – Enter VTS: 0.5V → 1.7V; Timer Held in Reset 1550 1600 1650 mV VHYS-TTDM(TS) Hysteresis exiting TTDM VTS: 1.7V → 0.5V; Timer Enabled VCLAMP(TS) TS maximum voltage clamp VTS= Open (Float) 1800 1950 tDGL(TTDM) VTS_I-FLDBK Deglitch exit TTDM between states Deglitch enter TTDM between states TS voltage where INTC is reduce to keep thermistor from entering TTDM INTC adjustment (90 to 10%; 45 to 6.6uA) takes place near this spec threshold. VTS: 1.425V → 1.525V 100 mV 2000 ms 8 μs 1475 mV Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 mV 57 5 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS CTS Optional Capacitance – ESD VTS-0°C bq24050/2/5 Low temperature CHG Pending Low Temp Charging to Pending; VTS: 1V → 1.5V VHYS-0°C Hysteresis at 0°C Charge pending to low temp charging; VTS: 1.5V → 1V VTS-10°C Low temperature, half charge Normal charging to low temp charging; VTS: 0.5V → 1V VHYS-10°C Hysteresis at 10°C Low temp charging to normal CHG; VTS: 1V → 0.5V VTS-45°C High temperature at 4.1V Normal charging to high temp CHG; VTS: 0.5V → 0.2V VHYS-45°C Hysteresis at 45°C High temp charging to normal CHG; VTS: 0.2V → 0.5V VTS-60°C High temperature Disable High temp charge to pending; VTS: 0.2V → 0.1V VHYS-60°C Hysteresis at 60°C Charge pending to high temp CHG; VTS: 0.1V → 0.2V tDGL(TS_10C) Deglitch for TS thresholds: 10C. tDGL(TS) Deglitch for TS thresholds: 0/45/60C. Battery charging VTS-EN-10k Charge Enable Threshold, (10k NTC) VTS: 0V → 0.175V; VTS-DIS_HYS-10k HYS below VTS-EN-10k to Disable, (10k NTC) VTS: 0.125V → 0V; VTS-EN-100k Charge Enable Threshold, (100k NTC) VTS: 0V → 0.175V HYS below VTS-EN-100k to Disable, (100k NTC) VTS: 0.125V → 0V; VTS-DIS_HYS100k MIN TYP MAX 1205 1230 1255 86 765 790 278 815 178 293 50 Cold to Normal Operation: VTS: 1.0V → 0.6V 12 186 88 ms ms 96 12 140 150 mV mV 30 80 mV mV 11.5 Normal to Cold Operation: VTS: 0.6V → 1V mV mV 10.7 170 mV mV 35 263 UNIT μF 0.22 mV mV 160 mV 50 mV THERMAL REGULATION TJ(REG) Temperature regulation limit 125 °C TJ(OFF) Thermal shutdown temperature 155 °C TJ(OFF-HYS) Thermal shutdown hysteresis 20 °C LOGIC LEVELS ON ISET2 VIL Logic LOW input voltage Sink more than 8μA VIH Logic HIGH input voltage Source more than 8μA IIL Sink current required for LO IIH Source current required for HI 1.1 VFLT ISET2 Float Voltage 650 6 V 9 μA V 2 Submit Documentation Feedback 0.4 1.4 900 8 μA 1200 mV Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS (continued) Over junction temperature range 0°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT D+/D– DETECTION – bq24050/2/5 tDPDM DetectionTime from start of D+/Ddetection to latched output t=0 at D– pulled-up > 0.5V or D+ pulled up externally, >0.8V VD+ Bias at D+, during detection routine Can source at least 200μA ID+ Current Limit at D+ pin, during detection routine VD+ = 0V ID– Current Sink at D- pin, during detection routine VD- = 0.5V ID+_LEAK D+ leakage when not in detection mode ID–_LEAK D– leakage when not in detection mode VDPDM_0.4V D– Comparator Threshold Rising VDPDM_HYS_0.4 D– Comparator Hysteresis 65 0.475 0.7 V 1.5 mA 150 μA VD+ = 5V 1 μA VD- = 5V 1 μA 0.45 V 50 0.6 ms 100 0.35 42 mV V VDPDM_0.8V D+/D– Comparator Threshold Rising VDPDM_HYS_0.8 D+/D– Comparator Hysteresis 0.75 0.875 42 V mV V LOGIC LEVELS ON CHG AND PG VOL Output LOW voltage ISINK = 5mA Ilkg Leakage current into IC V CHG = 5V, V PG = 5V 0.4 V 1 μA Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 7 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com PIN CONFIGURATION bq24055 bq24050/2 1 IN 1 IN OUT 10 OUT 12 2 ISET TS 9 2 ISET TS 11 3 VSS CHG 8 3 VSS CHG 10 4 PRETERM 4 PRETERM ISET 2 7 5 D+ 5 D+ D- 6 6 PG ISET2 9 D- 8 NC 7 PIN FUNCTIONS NAME bq24050/2 bq24055 I/O DESCRIPTION IN 1 1 I Input power, connected to external DC supply (AC adapter or USB port). Expected range of bypass capacitors 1μF to 10μF, connect from IN to VSS. OUT 10 12 O Battery Connection. System Load may be connected. Average load should not be excessive, allowing battery to charge within the 10 hour safety timer window. Expected range of bypass capacitors 1μF to 10μF. Programs the Current Termination Threshold (5 to 50% of Iout which is set by ISET) and Sets the Pre-Charge Current to twice the Termination Current Level. PRE-TERM 4 4 I ISET 2 2 I Programs the Fast-charge current setting. External resistor from ISET to VSS defines fast charge current value. Range is 10.8k (50mA) to 675 Ω (800mA). ISET2 7 9 I Programming the Input/Output Current Limit for the USB or Adaptor source: High = 500mAmax, Low = ISET, FLOAT = 100mA max. D+D– Detection initially sets the charge threshold and requires ISET2 to change states to take control. 11 I Temperature sense pin connected to ‘50/55 –10k at 25C NTC thermistor, ’52 – 100k NTC at 25°C, in the battery pack. Floating TS Pin or pulling High puts part in TTDM and disable TS monitoring, Timers and Termination. Pulling pin Low disables the IC ( CE function). If NTC sensing is not needed, connect this pin to VSS through an external ‘50/55-10kΩ /’52-100kΩ resistor. A ‘50/55-250kΩ/’52-880kΩ from TS to ground will prevent IC entering TTDM when battery with thermistor is removed. TS 9 (1) Expected range of programming resistor is 1k to 10kΩ (2k: IOUT/10 for term; IOUT/5 for precharge) VSS 3 3 – Ground terminal CHG 8 10 O Low (FET on) indicates charging and Open Drain (FET off) indicates no Charging or Charge complete. PG – 6 O Low (FET on) indicates the input voltage is above UVLO and the OUT (battery) voltage and less than VOVP D+ 5 5 I USB port D+ input connection D– 6 8 I USB port D– input connection NC – 7 NA Pad 2x2mm2 Pad 2x3mm2 – Thermal PAD and Package (1) 8 Do not make connection to this pin (internal use) – Do not route through this pin There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times. Spins have different pin definitions Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Typical Application Circuit: bq24050/2 IOUT_FAST_CHG = 540mA; IOUT_PRE_CHG = 108mA; IOUT_TERM = 54mA bq24050/2 Adaptor 1 IN DC+ OUT 10 System Load 1.5kW GND 2 ISET Battery Pack TS 9 + 1kW 3 CHG 8 VSS 1mF 1mF 4 OR PRETERM ISET 2 7 5 D+ D- 6 VDD 2kW TTDM USB Port ISET/100/500mA VBUS GND GND D+ D+ D- Host DDisconnected after Detection Typical Application Circuit: bq24055 IOUT_FAST_CHG = 540mA; IOUT_PRE_CHG = 108mA; IOUT_TERM = 54mA bq 24055 Adaptor 1 IN DC+ System Load OUT 12 1.5kW GND 2 ISET 1kW Battery Pack TS 11 + 3 VSS 4 PRETERM CHG 10 1mF OR 2kW USB Port 5 D+ 6 PG 1mF ISET2 9 D- 8 NC 7 VBUS GND VDD TTDM ISET/100/500 mA GND D+ D+ D- D- Host Disconnected after Detection Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 9 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com FUNCTIONAL BLOCK DIAGRAM Internal Charge Current Sense w/Multiple Outputs IN OUT OUT IN OUT + _ + _ 80 Input mV Power + Detect _ + - IN-DPMREF IOUT x 1.5 V 540 AW Charge Pump OUTREGREF TJ°C + _ 125°CREF FAST CHARGE Thermal Regulation PRE-CHARGE ISET IN + _ 1.5 V Pre-CHG Reference + _ USB Sense Resistor USB100/500REF TJoC + _ Term Reference + _ 150oCREF Thermal Shutdown Charge Pump X2 Gain (1:2) Term:Pre-CHG 75mA+ PRE-TERM IN Increased from 75mA to 85mA for 1st minute of charge. + _ + OUT CHG OVPREF + _ On During 1st Charge Only + _ VTERM_EN ON: OFF: ISET2 (LOW = ISET, HI = USB500, CHARGE CONTROL 0.9 V Float FLOAT = USB100) PG bq24055 Only VCOLD-10C + _ + _ VHOT-45C HI = Half CHG (JEITA) HI = 4.06Vreg (JEITA) 0.6 V(200 mA) VCOLD-FLT + _ + _ VHOT-FLT D+ LO = TTDM MODE HI = Suspend CHG TS VTTDM VDISABLE + _ 10 D(100 mA) HI = CHIP DISABLE + _ Cold Temperature Sink Current VCLAMP = 1.4 V = 45mA + _ 5m A D+ / DDETECTION CONTROL - On Initial Supply Power Connection Disable Sink Current = 20mA + _ 45mA Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 TYPICAL OPERATIONAL CHARACTERISTICS SETUP: bq24055 typical applications schematic; VIN = 5V, VBAT = 3.6V (unless otherwise indicated) RISET = 1k; IOUT_FAST_CHG = 540mA; RPAC_TERM = 2k; IOUT_PRE_CHG = 108mA; IOUT_TERM = 54mA Power UP, DOWN, OVP, Disable and Enable Waveforms Vin Vin 2V/div D+ 2V/div D+ 1V/div Vd- 1V/div Vd- 1V/div 1V/div Vchg 2V/div 5V/div Viset 2V/div Vchg Viset 2V/div t - time - 100ms/div t - time - 10ms/div Detected D- line pulled to 0.6V and the detection routine is started. No signal detected on D+ or D-. After 500ms, the detection routine is forced to run. Figure 1. D+ D- Detection for Adaptor Hot Plug Figure 2. D+ D- Detection for Unknown Source Hot Plug Vin Vin 2V/div 2V/div D+ 1V/div Vd- 1V/div 5V/div End of Detection Routine D+ 1V/div Detection Routine Started Vd1V/div Vchg 5V/div Viset Vchg 2V/div Viset t - time - 100ms/div 2V/div t - time - 50ms/div (Device transceiver is "dead") After 500ms, the detection routine is forced to run. Figure 3. D+ D- Detection for USB Hot Plug no Pullup Vin USB Communication Between Host and Device Receiver Figure 4. D+ D- Detection for USB Hot Plug with Pullup Vin 5V/div 5V/div Vchg 2V/div Vchg Vpg 2V/div Vpg Viset 2V/div 2V/div Viset 2V/div 2V/div t - time - 20ms/div t - time - 100ms/div Figure 5. OVP 8V Adaptor – Hot Plug Figure 6. OVP from Normal Operation – VIN = 0V→5V→8V→5V Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 11 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com TYPICAL OPERATIONAL CHARACTERISTICS (continued) SETUP: bq24055 typical applications schematic; VIN = 5V, VBAT = 3.6V (unless otherwise indicated) RISET = 1k; IOUT_FAST_CHG = 540mA; RPAC_TERM = 2k; IOUT_PRE_CHG = 108mA; IOUT_TERM = 54mA Vpg Vpg 2V/div 5V/div Vchg Vchg 2V/div 2V/div Vout 500mV/div Vts 2V/div Viset Battery Detect Mode 2V/div Vin t - time - 50ms/div 5V/div 10kΩ resistor from TS to GND. 10kΩ is shorted to disable the IC. t - time - 20ms/div Fixed 10kΩ resistor, between TS and GND. Figure 7. TS Enable and Disable Figure 8. Hot Plug Source w/No Battery – Battery Detection 1 Battery Detect Cycle Vout Vin 2V/div 1V/div Vchg Vout Viset 500mV/div 5V/div 1V/div Viset 1V/div Vts 1V/div Vts 2V/div Entered TTDM t - time - 5ms/div t - time - 10ms/div Figure 9. Battery Removal – GND Removed 1st, 42-Ω Load Vout Figure 10. Battery Removal with OUT and TS Disconnect 1st, With 100–Ω Load 1V/div Vchg Battery Declared Absent 5V/div Viset 1V/div V_0.1 W_OUT 100mV/div t - time - 20ms/div Continuous battery detection when not in TTDM. Figure 11. Battery Removal With Fixed TS = 0.5V 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 TYPICAL OPERATIONAL CHARACTERISTICS (continued) SETUP: bq24055 typical applications schematic; VIN = 5V, VBAT = 3.6V (unless otherwise indicated) RISET = 1k; IOUT_FAST_CHG = 540mA; RPAC_TERM = 2k; IOUT_PRE_CHG = 108mA; IOUT_TERM = 54mA PROTECTION CIRCUITS WAVEFORMS 1V/div Vout Vout 1V/div Vchg 5V/div Viset Battery Threshold Reached Vchg 2V/div 500mV/div 1V/div IOUT Clamped Current Viset V_0.1 W_OUT V_0.1 W_OUT 100mV/div 100mV/div ISET Short Detected and Latched Off t - time - 500ms/div CH4: Iout (1A/Div)Battery voltage swept from 0V to 4.25V to 3.9V. Figure 12. Battery Charge Profile Vchg t - time - 200ms/div CH4: Iout (1A/Div) Figure 13. ISET Shorted During Normal Operation Vin 2V/div 2V/div Vchg Vin 2V/div 2V/div 500mV/div Short Detected in 100mA mode and Latched Off Viset V_0.1 W_OUT t - time - 1ms/div t - time - 5ms/div CH4: Iout (0.2A/Div) CH4: Iout (0.2A/Div) Figure 14. ISET Shorted Prior to USB Power Up Vin 2V/div Vchg V_0.1W_OUT 20mV/div 500mV/div 20mV/div Viset Figure 15. DPM – Adaptor Current Limits – VIN Regulated to 4.3V Vin Vout 2V/div 1V/div 2V/div Enters Thermal Regulation Exits Thermal Regulation Viset 1V/div 500mV/div 20mV/div V_0.1W_OUT Viset 50mV/div V_0.1W_OUT t - time - 500ms/div t - time - 1s/div The IC temperature rises to 125°C and enters thermal regulation. Charge current is reduced to regulate the IC at 125°C. VIN is reduced, the IC temperature drops, the charge current returns to the programmed value. Figure 16. DPM – USB Current Limits – VIN Regulated to 4.4V Figure 17. Thermal Reg. – VIN Increases Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 13 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com TYPICAL OPERATIONAL CHARACTERISTICS (continued) SETUP: bq24055 typical applications schematic; VIN = 5V, VBAT = 3.6V (unless otherwise indicated) RISET = 1k; IOUT_FAST_CHG = 540mA; RPAC_TERM = 2k; IOUT_PRE_CHG = 108mA; IOUT_TERM = 54mA 546 Kiset 544 Vin 1V/div 542 Low to High Currents (may occur in recharge to fast charge transion) Kiset - W 540 Viset 1V/div Vchg 5V/div Vpg 538 High to Low Currents (may occur in Voltage Regulation - Taper Current) 536 5V/div 534 t - time - 20ms/div 532 Vin swept from 5V to 3.9V to 5V, Vbat = 4V 530 528 .15 0 Figure 18. Entering and Exiting Sleep Mode 0.2 0.4 IO - Output Current - A 0.6 0.8 Figure 19. Kiset for Low and High Currents 4.212 4.2 VO @ 0°C ROUT = 100 Ω 4.21 4.199 4.208 4.198 4.206 VOUT - Output Voltage - V VOUT - Output Voltage DC - V Vreg @ 25°C VO @ 25°C 4.204 4.202 VO @ 85°C 4.2 4.196 4.195 Vreg @ 0°C 4.194 4.193 4.198 4.196 4.5 Vreg @ 85°C 4.197 4.192 5 5.5 VI - Input Voltage DC - V 6 6.5 0 Figure 20. Line Regulation 0.2 0.4 0.6 IO - Output current - A 0.8 1 Figure 21. Load Regulation Over Temperature 363.4 363.2 IO - Output Current - mA IO @ 25°C 363 362.8 IO @ 85°C 362.6 362.4 362.2 IO @ 0°C 362 361.8 2.5 3 3.5 VO - Output Voltage - V 4 4.5 Figure 22. Current Regulation Overtemperature 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 FUNCTIONAL GENERAL DESCRIPTION The bq2405x is a highly integrate family of 2×2 or 2×3mm single cell Li-Ion chargers. The charger can be used to charge a battery, power a system or both. The charger has three phases of charging: Pre-charge to recover a fully discharged battery, fast-charge constant current to supply the buck charge safely and voltage regulation to safely reach full capacity. The charger is very flexible, allowing programming of the fast-charge current, pre-charge current and termination. This charger is designed to work with a USB connection or Adaptor (DC out). The charger also checks to see if a battery is present. The charger also comes with a full set of safety features: JEITA Temperature Standard, Over-Voltage Protection, DPM-IN, Safety Timers, and ISET short protection. All of these features and more are described in detail below. The charger is designed for a single power path from the input to the output to charge a single cell Li-Ion battery pack. Upon application of a 5VDC power source the D+/D– detection routine is run to determine if the source is an Adaptor or a USB port. This feature is useful, when the battery is discharged (USB transceiver dead) or there is no transceiver, by early detection of an adaptor, thus allowing initial charging at the adaptor level. ISET and OUT short checks are performed in parallel with the detection routine to assure a proper charge cycle. If the battery voltage is below the LOWV threshold, the battery is considered discharged and a preconditioning cycle begins. The amount of precharge current can be programmed using the PRE-TERM pin which programs a percent of fast charge current (10 to 100%) as the precharge current. This feature is useful when the system load is connected across the battery “stealing” the battery current. The precharge current can be set higher to account for the system loading while allowing the battery to be properly conditioned. The PRE-TERM pin is a dual function pin which sets the precharge current level and the termination threshold level. The termination "current threshold" is always half of the precharge programmed current level. Once the battery voltage has charged to the VLOWV threshold, fast charge is initiated and the fast charge current is applied. The fast charge constant current is programmed using the ISET pin. The constant current provides the bulk of the charge. Power dissipation in the IC is greatest in fast charge with a lower battery voltage. If the IC reaches 125°C the IC enters thermal regulation, slow the timer clock by half and reduce the charge current as needed to keep the temperature from rising any further. Figure 23 shows the charging profile with thermal regulation. Typically under normal operating conditions, the IC’s junction temperature is less than 125°C and thermal regulation is not entered. Once the cell has charged to the regulation voltage the voltage loop takes control and holds the battery at the regulation voltage until the current tapers to the termination threshold. The charge termination can be disabled if desired. The CHG pin is low (LED on) during the first charge cycle only and turns off once the charge termination threshold is reached, regardless if termination is enabled or disabled. The TS pin monitors the voltage across the pack thermistor and implements the JEITA standard. This allows for reduced voltage regulation at hot temperatures and reduced charge currents at low temperatures. The TS pin incorporates a chip disable feature when pulled low and an Termination and Timer Disable Mode (TTDM) feature when left floating or pulled high. Further details are mentioned in the Operating Modes section. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 15 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com VO(REG) PreConditioning Phase Thermal Regulation Phase Current Regulation Phase Voltage Regulation and Charge Termination Phase DONE IO(OUT) FAST-CHARGE CURRENT PRE-CHARGE CURRENT AND TERMINATION THRESHOLD Battery Voltage, V(OUT) Battery Current, I(OUT) Charge Complete Status, Charger Off VO(LOWV) I(TERM) IO(PRECHG) T(THREG) 0A Temperature, Tj T(PRECHG) T(CHG) DONE Figure 23. Charging Profile with Thermal Regulation DETAILED FUNCTIONAL DESCRIPTION Power-Down, or Undervoltage Lockout (UVLO): The bq2405x family is in power down mode if the IN pin voltage is less than UVLO. The part is considered “dead” and all the pins are high impedance. Once the IN voltage rises above the UVLO threshold the IC will enter Sleep Mode or Active mode depending on the OUT pin (battery) voltage. Power-up The IC is alive after the IN voltage ramps above UVLO (see sleep mode), resets all logic and timers, and starts to perform the D+D– detection along with many of the continuous monitoring routines. The D+/D– detection typically take less than 100ms, but can take as long as 600ms if there is no activity on the D+ or D– lines which indicates the device transceiver nor an adaptor is present. Typically the input voltage quickly rises through the UVLO and sleep states where the IC declares power good, starts the qualification charge at 100mA, finishes the USB detection routine, sets the input current limit threshold base on the source detected (ISET=adaptor or 100mA=USB), starts the safety timer and enables the CHG pin. See Figure 25 D+/D– Detection: This detection is designed to give the charger advance notice that an adaptor or USB port is connect for the cases where the battery is discharged and device transceiver is not able to communicate with a USB host or there is not a device transceiver. If an adaptor is detected, then the charger can immediately start charging at the programmed ISET level. Without this early detection, the charger would have to default to the 100mA input current level to make sure it was not over-loading a low power USB port. The detection method monitors the D+/D– communication lines looking for a short between the lines (Adaptor source connected) or pull down resistors on D+/D– (USB source connected) to determine what source is connected (no USB communication takes place). If an adaptor source is detected then the charger will transition from the 100mA startup level to the ISET programmed current level. If a USB port is detected, the input current limit will stay at the100mA level. If a different charge level is desired, than the one detected, the host has to change the state of the ISET2 pin (signals the internal logic to start using the ISET2 as the program pin) and then set to the desired state. The D+ and D– pin connections inside the charger are disconnected within 100ms of the D+ or D– lines being 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 pulled high (start of detection), to minimize any interaction between the charger detection pins and the USB normal communications. If the device transceiver is able to communicate with the USB host, communication typically starts after 100ms after the device has pulled the D+ or D– line high indicating it is “on line”, and by then the IC detection is complete and has been disconnected. The device host then may change the ISET2 level or disable the IC by pulling the TS pin low. Sleep Mode If the IN pin voltage is between than VOUT+VDT and UVLO, the charge current is disabled, the safety timer counting stops (not reset) and the PG and CHG pins are high impedance. As the input voltage rises and the charger exits sleep mode, the PG pin goes low, the safety timer continues to count, charge is enabled and the CHG pin returns to its previous state. See Figure 18 New Charge Cycle A new charge cycle is started when a good power source is applied, performing a chip disable/enable (TS pin), exiting Termination and Timer Disable Mode (TTDM), detecting a battery insertion or the OUT voltage dropping below the VRCH threshold. The CHG pin is active low only during the first charge cycle, therefore exiting TTDM or a dropping below VRCH will not turn on the CHG pin FET, if the CHG pin is already high impedance. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 17 18 Submit Documentation Feedback Product Folder Link(s): bq24050 bq24052 bq24055 0V DISHYS EN 60°C 60°CHYS 45°C 45°CHYS 10°CHYS 10°C 0°CHYS 0°C LDOHYS LDO 1.8V VSS tDGL(TS) Disabled 4.06 V HOT Operation tDGL(TS) Normal Operation tDGL(TS) 4.06 V HOT Operation tDGL(TS) HOT Fault tDGL(TS) Cold Fault LDO Mode t < tDGL(IS) Normal Operation Cold Operation tDGL(TS_IOC) Falling tDGL(TS) tDGL(TTDM) Exit Cold Fault Drawing Not to Scale Dots Show Threshold Trip Points fllowed by a deglitch time before transitioning into a new mode. tDGL(TTDM) Enter Cold Operation tDGL(TS) Normal Operation tDGL(TS_IOC) Rising Disabled Normal Operation t tDGL(TS1_IOC) Cold to Normal t < tDGL(TTDM) Exit tDGL(TTDM) Enter LDO Mode bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com Figure 24. TS Battery Temperature Bias Threshold and Deglitch Timers Copyright © 2009, Texas Instruments Incorporated bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Apply Input Power Is Chip Enabled &Alive? VTS > VEN & VIN>VUVLO No Start Running USB Detection Routine Yes Is power good? VBAT +VDT < VIN < VOVP & VUVLO < VIN No Yes Turn on PG FET – PG pin LOW Set Input Current Limit to 100mA and Start Charge Perform ISET & OUT short tests Remember ISET2 State Yes Has ISET2 changed state since Detection Routine was run? No Yes Set charge current based on ISET2 truth table. Set charge current based Detection Routine.. Return to Charge Figure 25. Power-up Flow Diagram Overvoltage-Protection (OVP) – Continuously Monitored If the input source applies an overvoltage, the pass FET, if previously on, turns off after a deglitch, tBLK(OVP). The timer ends and the CHG and PG pin goes to a high impedance state. Once the overvoltage returns to a normal voltage, the PG pin goes low, timer continues, charge continues and the CHG pin goes low after a 25ms deglitch.. PG pin is optional on some packages. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 19 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com Power Good Indication (PG) After application of a 5V source, the input voltage rises above the UVLO and sleep thresholds (VIN>VOUT+VDT), but is less than OVP (VIN<VOVP), then the PG FET turns on and provides a low impedance path to ground. SEE Figure 5, Figure 6, and Figure 18. CHG Pin Indication The charge pin has an internal open drain FET which is on (pulls down to VSS) during the first charge only (independent of TTDM) and is turned off once the battery reaches voltage regulation and the charge current tapers to the termination threshold set by the PRE-TERM resistor. The charge pin will be high impedance in sleep mode and OVP (if PG is high impedance) and return to its previous state once the condition is removed. Cycling input power, pulling the TS pin low and releasing or entering pre-charge mode will cause the CHG pin to reset and is considered the start of a first charge. CHG and PG LED Pull-up Source For host monitoring, a pull-up resistor is used between the "STATUS" pin and the VCC of the host and for a visual indication a resistor in series with an LED is connected between the "STATUS" pin and a power source. If the CHG or PG source is capable of exceeding 7V, a 6.2V zener should be used to clamp the voltage. If the source is the OUT pin, note that as the battery changes voltage, the brightness of the LEDs vary. Charging State CHG FET/LED 1st Charge ON Refresh Charge OVP OFF SLEEP TEMP FAULT ON for 1st Charge VIN Power Good State PG FET/LED UVLO SLEEP Mode OFF OVP Mode Normal Input (VOUT + VDT < VIN < VOUP) ON PG is independent of chip disable (bq24055, VTS = 0V) Input DPM Mode (VIN-DPM or IN-DPM) The IN-DPM feature is used to detect an input source voltage that is folding back (voltage dropping), reaching its current limit due to an excessive load. When the input voltage drops to the VIN-DPM threshold the internal pass FET starts to reduce the current until there is no further drop in voltage at the input. This would prevent a source with voltage less than VIN-DPM to power the out pin. This works well with current limited adaptors and USB ports as long as the nominal voltage is above 4.3V and 4.4V respectively. This is an added safety feature that helps protect the source from excessive loads. OUT The Charger’s OUT pin provides current to the battery and to the system, if present. This IC can be used to charge the battery plus power the system, charge just the battery or just power the system (TTDM) assuming the loads do not exceed the available current. The OUT pin is a current limited source and is inherently protected against shorts. If the system load ever exceeds the output programmed current threshold, the output will be discharged unless there is sufficient capacitance or a charged battery present to supplement the excessive load. 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ISET An external resistor is used to Program the Output Current (50 to 800mA) and can be used as a current monitor. RISET = KISET ÷ IOUT (0) Where: IOUT is the desired fast charge current; KISET is a gain factor found in the electrical specification For greater accuracy at lower currents, part of the sense FET is disabled to give better resolution. Figure 19 shows the transition from low current to higher current. Going from higher currents to low currents, there is hysteresis and the transition occurs around 0.15A. The ISET resistor is short protected and will detect a resistance lower than 340Ω. The detection requires at least 80mA of output current. If a “short” is detected, then the IC will latch off and can only be reset by cycling the power. The OUT current is internally clamped to a maximum current between 1.1A and 1.35A and is independent of the ISET short detection circuitry, as shown in Figure 27. Also, see Figure 13 and Figure 14. 4.5 o For < 45 C, 4.2V Regulation No Operation During Cold Fault 3.5 3 60oC to 45oC HOT TEMP 4.06V Regulation VOUT 2.5 < 48oC 1.5 1 0.5 0 0 o 10oC 60oC Termination Disable 2 0C 100% of Programmed Current } IC Disable } Hot Fault Normalized OUT Current and VREG - V 4 50% Cold Fault IOUT 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VTS - Voltage - V Figure 26. OPERATION OVER TS BIAS VOLTAGE Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 21 bq24050 bq24052 bq24055 1.8 1.6 IO - Output Current - A 1.4 IOUT Clamp min - max IOUT Fault min - max SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com 1.2 IOUT Internal Clamp Range 1 0.8 IOUT Programmed max 0.6 ISET Short Fault Range min 0.4 0.2 Non Restricted Operating Area 0 1000 100 10000 ISET - W Figure 27. PROGRAMMED / CLAMPED OUT CURRENT PRE_TERM – Pre-Charge and Termination Programmable Threshold Pre-Term is used to program both the pre-charge current and the termination current threshold, on the bq24050/2/5. The pre-charge current level is a factor of two higher than the termination current level. The termination can be set between 5 and 50% of the programmed output current level set by ISET. If left floating the termination and pre-charge are set internally at 10/20% respectively. The pre-charge-to-fast-charge, Vlowv threshold is set to 2.5V. RPRE-TERM = %Term × KTERM = %Pre-CHG × KPRE-CHG (0) Where: %Term is the percent of fast charge current where termination occurs; %Pre-CHG is the percent of fast charge current that is desired during precharge; KTERM and KPRE-CHG are gain factors found in the electrical specifications. 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ISET2 Is a 3-state input and programs the Input Current Limit/Regulation Threshold. A low will program a regulated fast charge current via the ISET resistor and is the maximum allowed input/output current for any ISET2 setting, Float will program a 100mA Current limit and High will program a 500mA Current limit. Note that initially the D+/D– detection will latch the charge mode according to the source detected (dedicated charger: ISET; USB Host: at 100mA) until the ISET2 pin has changed states, indicating the processor or transceiver is controlling the pin. The detection routine registers the input level (Low–High-Z–High) of the ISET2 pin ~532 μs after applying input power (VIN > 3.4 V – UVLO). After the detection routine is complete, which is ~100 ms after a pull-up on the D+ or D– line or after ~570 ms if no pull-up, the IC monitors the ISET2 pin for a change of state. If the state changes (Low–High-Z–High) from the one registered, for more than 5 μs, then the "detected" latched charge mode is released and is then controlled by the ISET2 pin. The completion of the detection routine varies due to the mechanical-plugging action of the USB cable; therefore, it is best to wait ≥ 600 ms after VIN > 3.4 V to take control of the ISET2 pin. The following illustration shows two configurations for driving the 3-state ISET2 pin: VCC VCC To ISET2 R1 To ISET2 Drive Logic Q1 OR Drive Logic R1/R2 Divider set to 0.9 V Which is the Float Voltage R2 Q2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 23 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com TS The TS pin is designed to follow the new JEITA temperature standard for Li-Ion batteries. There are now four thresholds, 60°C, 45°C, 10°C, and 0°C. Normal operation occurs between 10°C and 45°C. If between 0°C and 10°C the charge current level is cut in half and if between 45°C and 60°C the regulation voltage is reduced to 4.1Vmax, see Figure 26. The TS feature is implemented using an internal 50μA current source to bias the thermistor (bq24050/5 designed for use with a 10k NTC β = 3370 (SEMITEC 103AT-2 or Mitsubishi TH05-3H103F), and bq24052 with a 100k NTC β = 3540 (Mitsubishi TH05-36104F) or equivalent) connected from the TS pin to VSS. If this feature is not needed, a fixed 10k can be placed between TS and VSS to allow normal operation. This may be done if the host is monitoring the thermistor and then the host would determine when to pull the TS pin low to disable charge. The TS pin has two additional features, when the TS pin is pulled low or floated/driven high. A low disables charge (similar to a CE feature) and a high puts the charger in TTDM. Above 60°C or below 0°C the charge is disable. Once the thermistor reaches –10°C the TS current folds back to keep a cold thermistor (between –10°C and –50°C) from placing the IC in the TTDM mode. If the TS pin is pulled low into disable mode, the current is reduce to 30μA, see Figure 24. Since the ITS current is fixed along with the temperature thresholds, it is not possible to use thermistor values other than the 10k and 100k. Termination and Timer Disable Mode (TTDM) -TS pin high The battery charger is in TTDM when the TS pin goes high from removing the thermistor (removing battery pack/floating the TS pin) or by pulling the TS pin up to the TTDM threshold. When entering TTDM, the 10 hour safety timer is held in reset and termination is disabled. A battery detect routine is run to see if the battery was removed or not. If the battery was removed then the CHG pin will go to its high impedance state if not already there. If a battery is detected the CHG pin does not change states until the current tapers to the termination threshold, where the CHG pin goes to its high impedance state if not already there (the regulated output will remain on). The charging profile does not change (still has pre-charge, fast-charge constant current and constant voltage modes). This implies the battery is still charged safely and the current is allowed to taper to zero. When coming out of TTDM, the battery detect routine is run and if a battery is detected, then a new charge cycle begins and the CHG LED turns on. If TTDM is not desired upon removing the battery with the thermistor, one can add a 237k resistor between TS and VSS to disable TTDM. This keeps the current source from driving the TS pin into TTDM. This creates 0.1°C error at hot and a 3°C error at cold. Timers The pre-charge timer is set to 30 minutes . The pre-charge current, can be programmed to off-set any system load, making sure that the 30 minutes is adequate. The fast charge timer is fixed at 10 hours and can be increased real time by going into thermal regulation, IN-DPM or if in USB current limit. The timer clock slows by a factor of 2, resulting in a clock than counts half as fast when in these modes. If either the 30 minute or ten hour timer times out, the charging is terminated and the CHG pin goes high impedance if not already in that state. The timer is reset by disabling the IC, cycling power or going into and out of TTDM. Termination Once the OUT pin goes above VRCH, (reaches voltage regulation) and the current tapers down to the termination threshold, the CHG pin goes high impedance and a battery detect route is run to determine if the battery was removed or the battery is full. If the battery is present the charge current will terminate. If the battery was removed along with the thermistor, then the TS pin will be driven high and the charge will enter TTDM. If the battery was removed and the TS pin is held in the active region, then the battery detect routine will continue until a battery is inserted. 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Battery Detect Routine The battery detect routine should check for a missing battery while keeping the OUT pin at a useable voltage. Whenever the battery is missing the CHG pin should be high impedance. The battery detect routine is run when entering and exiting TTDM to verify if battery is present, or run all the time if battery is missing and not in TTDM. On power-up, if battery voltage is greater than VRCH threshold, a battery detect routine is run to determine if a battery is present. The battery detect routine will be disabled while the IC is in TTDM or has a TS fault. See Figure 28 for the Battery Detect Flow Diagram. Refresh Threshold After termination, if the OUT pin voltage drops to VRCH (100mV below regulation) then a new charge is initiated, but the CHG pin remains at a high impedance (off). Starting a Charge on a Full Battery The termination threshold is raised by 14%, for the first minute of a charge cycle so if a full battery is removed and reinserted or a new charge cycle is initiated, that the new charge terminates (less than 1 minute). Batteries that have relaxed many hours may take several minutes to taper to the termination threshold and terminate charge. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 25 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com Start BATT_DETECT Start 25ms timer Timer Expired? No Yes Is VOUT<VREG-100mV? Yes Battery Present Turn off Sink Current Return to flow No Set OUT REG to VREG-400mV Enable sink current Reset & Start 25ms timer Timer Expired? No Yes Yes Is VOUT>VREG-300mV? Battery Present Turn off Sink Current Return to flow No Battery Absent Don’t Signal Charge Turn off Sink Current Return to Flow Figure 28. Battery Detect Flow Diagram 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 bq2405x CHARGER APPLICATION DESIGN EXAMPLE bq24050/2 Adaptor DC+ 1 IN 2 ISET TS 9 3 VSS CHG 8 4 PRETERM 5 D+ OUT System Load 10 1.5kW GND Battery Pack + 1kW 1mF 1mF OR ISET 2 7 D- 6 VDD 2kW TTDM USB Port ISET/100/500 mA VBUS GND GND D+ D+ D- D- Host Disconnect after Detection Requirements • Supply voltage = 5 V • Fast charge current: IOUT-FC = 540 mA; ISET-pin 2 • Termination Current Threshold: %IOUT-FC = 10% of Fast Charge or 54mA • Pre-Charge Current by default is twice the termination Current or 108mA • TS – Battery Temperature Sense = 10k NTC (103AT) Calculations Program the Fast Charge Current, ISET: RISET = [K(ISET) / I(OUT)] from electrical characteristics table. . . K(SET) = 540AΩ RISET = [540AΩ/0.54A] = 1.0 kΩ Selecting the closest standard value, use a 1kΩ resistor between ISET (pin 16) and VSS. Program the Termination Current Threshold, ITERM: RPRE-TERM = K(TERM) × %IOUT-FC RPRE-TERM = 200Ω/% × 10% = 2kΩ Selecting the closest standard value, use a 2kΩ resistor between ITERM (pin 15) and Vss. One can arrive at the same value by using 20% for a pre-charge value (factor of 2 difference). RPRE-TERM = K(PRE-CHG) × %IOUT-FC RPRE-TERM = 100Ω/% × 20%= 2kΩ TS Function Use a 10k NTC thermistor in the battery pack (103AT). To Disable the temp sense function, use a fixed 10k resistor between the TS (Pin 1) and VSS. CHG and PG LED Status: connect a 1.5k resistor in series with a LED between the OUT pin and the CHG pin. Connect a 1.5k resistor in series with a LED between the OUT pin and the and PG pin. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 27 bq24050 bq24052 bq24055 SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com Processor Monitoring: Connect a pull-up resistor between the processor’s power rail and the CHG pin. Connect a pull-up resistor between the processor’s power rail and the PG pin. SELECTING IN AND OUT PIN CAPACITORS In most applications, all that is needed is a high-frequency decoupling capacitor (ceramic) on the power pin, input and output pins. Using the values shown on the application diagram, is recommended. After evaluation of these voltage signals with real system operational conditions, one can determine if capacitance values can be adjusted toward the minimum recommended values (DC load application) or higher values for fast high amplitude pulsed load applications. Note if designed for high input voltage sources (bad adaptors or wrong adaptors), the capacitor needs to be rated appropriately. Ceramic capacitors are tested to 2x their rated values so a 16V capacitor may be adequate for a 30V transient (verify tested rating with capacitor manufacturer). THERMAL PACKAGE The bq2405x family is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the IC and the printed circuit board (PCB). The power pad should be directly connected to the VSS pin. Full PCB design guidelines for this package are provided in the QFN/SON PCB Attachment Application Note application note (SLUA271). The most common measure of package thermal performance is thermal impedance (θJA ) measured (or modeled) from the chip junction to the air surrounding the package surface (ambient). The mathematical expression for θJA is: θJA = (TJ – T) / P (0) Where: TJ = chip junction temperature T = ambient temperature P = device power dissipation Factors that can influence the measurement and calculation of θJA include: 1. Whether or not the device is board mounted 2. Trace size, composition, thickness, and geometry 3. Orientation of the device (horizontal or vertical) 4. Volume of the ambient air surrounding the device under test and airflow 5. Whether other surfaces are in close proximity to the device being tested Due to the charge profile of Li-Ion batteries the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. Typically after fast charge begins the pack voltage increases to 3.4V within the first 2 minutes. The thermal time constant of the assembly typically takes a few minutes to heat up so when doing maximum power dissipation calculations, 3.4V is a good minimum voltage to use. This is verified, with the system and a fully discharged battery, by plotting temperature on the bottom of the PCB under the IC (pad should have multiple vias), the charge current and the battery voltage as a function of time. The fast charge current will start to taper off if the part goes into thermal regulation. The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal PowerFET. It can be calculated from the following equation when a battery pack is being charged : P = [V(IN) – V(OUT)] × I(OUT) + [V(OUT) – V(OUT)] × I(OUT) (0) The thermal loop feature reduces the charge current to limit excessive IC junction temperature. It is recommended that the design not run in thermal regulation for typical operating conditions (nominal input voltage and nominal ambient temperatures) and use the feature for non typical situations such as hot environments or higher than normal input source voltage. With that said, the IC will still perform as described, if the thermal loop is always active. Leakage Current Effects on Battery Capacity To determine how fast a leakage current on the battery discharges, the battery is used for the calculation. The time from full to discharge can be calculated by dividing the Amp-Hour Capacity of the battery by the leakage current. For a 0.75AHr battery and a 10μA leakage current (750mAHr/0.010mA = 75000 Hours), it would take 75k hours or 8.8 years to discharge. In reality, the self discharge of the cell is much faster, so the 10μA leakage would be considered negligible. 28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 bq24050 bq24052 bq24055 www.ti.com.................................................................................................................................... SLUS940A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Layout Tips To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter capacitors from OUT to GND (thermal pad) should be placed as close as possible to the bq2405x, with short trace runs to both IN, OUT and GND (thermal pad). • All low-current GND connections should be kept separate from the high-current charge or discharge paths from the battery. Use a single-point ground technique incorporating both the small signal ground path and the power ground path. • The high current charge paths into IN pin and from the OUT pin must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces • The bq2405x family is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the IC and the printed circuit board (PCB); this thermal pad is also the main ground connection for the device. Connect the thermal pad to the PCB ground connection. It is best to use multiple 10-mill vias in the power pad of the IC and in close proximity to conduct the heat to the bottom ground plane. The bottom ground place should avoid traces that “cut off” the thermal path. The thinner the PCB the less temperature rise. The EVM PCB has a thickness of 0.031 inches and uses 2 oz. (2.8-mill thick) copper on top and bottom, and is a good example of optimal thermal performance. SPACER REVISION HISTORY Changes from Original (August 2009) to Revision A ..................................................................................................... Page • Changed the status of the devices From: Product Preview To: Prodcution Data ................................................................ 1 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): bq24050 bq24052 bq24055 29 PACKAGE OPTION ADDENDUM www.ti.com 15-Sep-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty BQ24050DSQR ACTIVE SON DSQ 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24050DSQT ACTIVE SON DSQ 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24052DSQR ACTIVE SON DSQ 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24052DSQT ACTIVE SON DSQ 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24055DSSR ACTIVE SON DSS 12 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24055DSST ACTIVE SON DSS 12 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Sep-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing BQ24050DSQR SON DSQ 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 BQ24050DSQT SON DSQ 10 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 BQ24052DSQR SON DSQ 10 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 BQ24052DSQT SON DSQ 10 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 BQ24055DSSR SON DSS 12 3000 179.0 8.4 2.3 3.2 1.0 4.0 8.0 Q1 BQ24055DSST SON DSS 12 250 179.0 8.4 2.3 3.2 1.0 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Sep-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24050DSQR SON DSQ 10 3000 195.0 200.0 45.0 BQ24050DSQT SON DSQ 10 250 195.0 200.0 45.0 BQ24052DSQR SON DSQ 10 3000 195.0 200.0 45.0 BQ24052DSQT SON DSQ 10 250 195.0 200.0 45.0 BQ24055DSSR SON DSS 12 3000 195.0 200.0 45.0 BQ24055DSST SON DSS 12 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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