Cypress CY7C185-25ZC 8k x 8 static ram Datasheet

185
CY7C185
8K x 8 Static RAM
Features
• High speed
— 15 ns
• Fast tDOE
• Low active power
— 715 mW
• Low standby power
— 220 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description[1]
The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE1), an active HIGH
chip enable (CE2), and active LOW output enable (OE) and
three-state drivers. This device has an automatic power-down
feature (CE1 or CE2), reducing the power consumption by 70%
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ/SOIC
Top View
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
I/O0
I/O1
I/O2
SENSE AMPS
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
256 x 32 x 8
ARRAY
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O4
I/O5
I/O6
CE1
CE2
WE
COLUMN DECODER
POWER
DOWN
I/O7
A12
A11
A10
A0
A9
OE
Selection Guide[2]
7C185-15
15
130
40/15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
7C185-20
20
110
20/15
7C185-25
25
100
20/15
7C185-35
35
100
20/15
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. For military specifications, see the CY7C185A data sheet.
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 13, 2002
CY7C185
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Range
Ambient
Temperature
VCC
DC Voltage Applied to Outputs
in High Z State[3] ............................................ –0.5V to +7.0V
Commercial
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
DC Input Voltage[3]......................................... –0.5V to +7.0V
Industrial
Electrical Characteristics Over the Operating Range
7C185-15
Parameter
Description
Test Conditions
Min.
Max.
2.4
7C185-20
Min.
Max.
2.4
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[3]
IIX
Input Load Current
GND ≤ VI ≤ VCC
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC,
Output Disabled
IOS
Output Short
Circuit Current[4]
VCC = Max.,
VOUT = GND
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA
ISB1
Automatic
Power-Down Current
Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL
Min. Duty Cycle = 100%
40
20
mA
ISB2
Automatic
Power-Down Current
Max. VCC, CE1 ≥ VCC – 0.3V,
or CE2 ≤ 0.3V
VIN ≥ VCC – 0.3V or VIN ≤ 0.3V
15
15
mA
0.4
V
0.4
V
V
2.2
VCC +
0.3V
2.2
VCC +
0.3V
–0.5
0.8
–0.5
0.8
V
–5
+5
–5
+5
µA
–5
+5
–5
+5
µA
–300
–300
mA
130
110
mA
Notes:
3. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05043 Rev. *A
Page 2 of 11
CY7C185
Electrical Characteristics Over the Operating Range (continued)
7C185-25
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[3]
IIX
Input Load Current
GND ≤ VI ≤ VCC
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC,
Output Disabled
IOS
Output Short
Circuit Current[4]
VCC = Max.,
VOUT = GND
ICC
VCC Operating
Supply Current
ISB1
ISB2
Min.
7C185-35
Max.
Min.
2.4
Max.
Unit
2.4
0.4
V
0.4
V
V
2.2
VCC +
0.3V
2.2
VCC +
0.3V
–0.5
0.8
–0.5
0.8
V
–5
+5
–5
+5
µA
–5
+5
–5
+5
µA
–300
–300
mA
VCC = Max.,
IOUT = 0 mA
100
100
mA
Automatic
Power-Down Current
Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL
Min. Duty Cycle = 100%
20
20
mA
Automatic
Power-Down Current
Max. VCC, CE1 ≥ VCC – 0.3V
or CE2 ≤ 0.3V
VIN ≥ VCC – 0.3V or VIN ≤ 0.3V
15
15
mA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
7
pF
7
pF
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 481 Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R1 481 Ω
5V
OUTPUT
R2
255Ω
(a)
ALL INPUT PULSES
3.0V
5 pF
INCLUDING
JIGAND
SCOPE
R2
255Ω
GND
10%
≤ 5 ns
90%
90%
10%
≤ 5 ns
(b)
THÉVENIN EQUIVALENT
OUTPUT
167Ω
Document #: 38-05043 Rev. *A
1.73V
Page 3 of 11
CY7C185
Switching Characteristics Over the Operating Range[6]
7C185-15
Parameter
Description
Min.
Max.
7C185-20
Min.
Max.
7C185-25
Min.
Max.
7C185-35
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
15
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE1
CE1 LOW to Data Valid
15
20
25
35
ns
tACE2
CE2 HIGH to Data Valid
15
20
25
35
ns
tDOE
OE LOW to Data Valid
8
9
12
15
ns
tLZOE
OE LOW to Low Z
15
3
OE HIGH to High
tLZCE1
CE1 LOW to Low
Z[8]
tLZCE2
CE2 HIGH to Low Z
CE1 HIGH to High
CE2 LOW to High Z
tPU
CE1 LOW to Power-Up
CE2 to HIGH to Power-Up
tPD
CE1 HIGH to Power-Down
CE2 LOW to Power-Down
20
35
25
5
3
7
35
5
3
8
ns
ns
3
10
ns
ns
10
ns
3
5
5
5
ns
3
3
3
3
ns
Z[7, 8]
tHZCE
25
5
3
Z[7]
tHZOE
20
7
0
8
0
15
10
0
20
10
0
20
ns
ns
20
ns
Write Cycle[9]
tWC
Write Cycle Time
15
20
25
35
ns
tSCE1
CE1 LOW to Write End
12
15
20
20
ns
tSCE2
CE2 HIGH to Write End
12
15
20
20
ns
tAW
Address Set-up to Write End
12
15
20
25
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
12
15
15
20
ns
tSD
Data Set-up to Write End
8
10
10
12
ns
tHD
Data Hold from Write End
0
0
0
0
ns
Z[7]
tHZWE
WE LOW to High
tLZWE
WE HIGH to Low Z
7
3
7
5
7
5
8
5
ns
ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device.
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *A
Page 4 of 11
CY7C185
Switching Waveforms
Read Cycle No.1[10,11]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No.2[12,13]
tRC
CE1
CE2
tACE
OE
OE
DATA OUT
tHZOE
tDOE
tLZOE
HIGH IMPEDANCE
tHZCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
Write Cycle No. 1 (WE Controlled)[11,13]
tWC
ADDRESS
tSCEI
CE1
tAW
tHA
tSCE2
CE
CE
2
tSA
WE
tPWE
OE
tSD
DATA I/O
NOTE 14
tHD
DATA IN VALID
tHZOE
10.
11.
12.
13.
Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
WE is HIGH for read cycle.
Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL.
The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH
to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
14. During this period, the I/Os are in the output state and input signals should not be applied.
Document #: 38-05043 Rev. *A
Page 5 of 11
CY7C185
Switching Waveforms (continued)
rite Cycle No. 2 (CE Controlled)[13,14,15]
tWC
ADDRESS
tSCE1
CE1
tSA
tSCE2
CE2
tAW
tHA
WE
tSD
tHD
DATA IN VALID
DATA I/O
Write Cycle No. 3 (WE Controlled, OE LOW)[13,14,15,16]
tWC
ADDRESS
CE1
tSCE1
CE2
tSCE2
tAW
tHA
tSA
WE
tSD
DATA I/O
tHD
DATA IN VALID
NOTE 14
tHZWE
tLZWE
Notes:
15. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05043 Rev. *A
Page 6 of 11
CY7C185
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
SB
1.2
I CC
0.8
0.6
0.4
4.5
5.0
0.8
0.6
0.4
V CC=5.0V
V IN=5.0V
5.5
ISB
0.0
–55
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.6
1.4
1.3
NORMALIZED t AA
NORMALIZED t AA
125
1.2
1.1
TA =25°C
1.0
1.4
1.2
1.0
VCC =5.0V
0.8
0.9
0.8
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
0.6
–55
6.0
2.5
25.0
DELTA tAA (ns)
30.0
2.0
1.5
1.0
25
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 38-05043 Rev. *A
80
VCC =5.0V
TA =25°C
60
40
20
0
0.0
5.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
VCC =5.0V
TA =25°C
80
60
40
20
0
0.0
125
20.0
15.0
10.0
0.0
1.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
NORMALIZED I CC vs. CYCLE TIME
1.25
VCC =4.5V
TA =25°C
5.0
0.5
2.0
100
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
1.0
120
AMBIENT TEMPERATURE (°C)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
0.0
0.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED I PO
25
OUTPUT SINK CURRENT (mA)
0.0
4.0
I CC
0.2
I SB
0.2
1.0
0
200
400
600
800 1000
CAPACITANCE (pF)
NORMALIZED I CC
1.0
NORMALIZED I,CC
I
NORMALIZED I,CCI
SB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
VCC =5.0V
TA =25°C
VCC =0.5V
1.00
0.75
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 7 of 11
CY7C185
Truth Table
CE1
CE2
WE
OE
Input/Output
Mode
H
X
X
X
High Z
Deselect/Power-Down
X
L
X
X
High Z
Deselect/Power-Down
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
High Z
Deselect
Address Designators
Address
Name
Address
Function
Pin
Number
A4
X3
2
A5
X4
3
A6
X5
4
A7
X6
5
A8
X7
6
A9
Y1
7
A10
Y4
8
A11
Y3
9
A12
Y0
10
A0
Y2
21
A1
X0
23
A2
X1
24
A3
X2
25
Ordering Information
Speed
(ns)
15
20
25
35
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C185-15PC
P21
28-Lead (300-Mil) Molded DIP
CY7C185-15SC
S21
28-Lead Molded SOIC
CY7C185-15VC
V21
28-Lead Molded SOJ
CY7C185-15VI
V21
28-Lead Molded SOJ
Industrial
CY7C185-20PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C185-20SC
S21
28-Lead Molded SOIC
CY7C185-20VC
V21
28-Lead Molded SOJ
CY7C185-20VI
V21
28-Lead Molded SOJ
Industrial
CY7C185-25PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C185-25SC
S21
28-Lead Molded SOIC
CY7C185-25VC
V21
28-Lead Molded SOJ
CY7C185-25VI
V21
28-Lead Molded SOJ
Industrial
CY7C185-35PC
P21
28-Lead (300-Mil) Molded DIP
Commercial
CY7C185-35SC
S21
28-Lead Molded SOIC
CY7C185-35VC
V21
28-Lead Molded SOJ
CY7C185-35VI
V21
28-Lead Molded SOJ
Document #: 38-05043 Rev. *A
Commercial
Industrial
Page 8 of 11
CY7C185
Package Diagrams
28-Lead (300-Mil) Molded DIP P21
51-85014-*B
28-Lead (300-Mil) Molded SOIC S21
51-85026-*A
Document #: 38-05043 Rev. *A
Page 9 of 11
CY7C185
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOJ V21
51-85031-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05043 Rev. *A
Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C185
Document History Page
Document Title: CY7C185 8K x 8 Static RAM
Document Number: 38-05043
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
107145
09/10/01
SZV
Change from Spec number: 38-00037 to 38-05043
*A
116470
09/16/02
CEA
Add applications foot note to data sheet.
Document #: 38-05043 Rev. *A
Page 11 of 11
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