Cypress CY62128BNLL-70ZXA 1-mbit (128k x 8) static ram Datasheet

CY62128BN
MoBL®
1-Mbit (128K x 8) Static RAM
Functional Description[1]
Features
• Temperature Ranges
The CY62128BN is a high-performance CMOS static RAM
organized as 128K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE1), an active
HIGH Chip Enable (CE2), an active LOW Output Enable (OE),
and tri-state drivers. This device has an automatic
power-down feature that reduces power consumption by more
than 75% when deselected.
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• 4.5V–5.5V operation
Writing to the device is accomplished by taking Chip Enable
One (CE1) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
• CMOS for optimum speed/power
• Low active power
(70 ns Commercial, Industrial, Automotive-A)
— 82.5 mW (max.) (15 mA)
Reading from the device is accomplished by taking Chip
Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
• Low standby power
(55/70 ns Commercial, Industrial, Automotive-A)
— 110 µW (max.) (15 µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
• Available in Pb-free and non-Pb-free 32-pin (450
mil-wide) SOIC, 32-pin STSOP and 32-pin TSOP-I
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Logic Block Diagram
Pin Configuration
Top View
SOIC
I/O 0
INPUT BUFFER
I/O 1
128K x 8
ARRAY
I/O 2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O 3
I/O 4
I/O 5
COLUMN
DECODER
CE1
CE2
WE
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GN
G
gnc
g
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O 7
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
OE
I/O 6
POWER
DOWN
NC
A16
A14
A12
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06498 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY62128BN
MoBL®
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62128BNLL Commercial
Operating, ICC (mA) Standby, ISB2 (µA)
Typ.[2]
Max.
Typ.[2]
Max.
Min.
Typ.[2]
Max.
Speed
(ns)
4.5
5.0
5.5
55
7.5
20
2.5
15
70
6
15
2.5
15
Industrial
55
7.5
20
2.5
15
70
6
15
2.5
15
Automotive-A
70
6
15
2.5
15
Automotive-E
70
6
25
2.5
25
Pin Configurations
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
STSOP
Top View
(not to scale)
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Pin Definitions
Input
A0–A16. Address Inputs
Input/Output
I/O0–I/O7. Data lines. Used as input or output lines depending on operation
Input/Control
WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted.
Input/Control
CE1. Chip Enable 1, Active LOW.
Input/Control
CE2. Chip Enable 2, Active HIGH.
Input/Control
OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins
Ground
GND. Ground for the device
Power Supply VCC. Power supply for the device
Note:
2. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production
variations as measured at VCC = 5.0V, TA = 25°C, and tAA = 70 ns.
Document #: 001-06498 Rev. *A
Page 2 of 12
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CY62128BN
MoBL®
Maximum Ratings
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-up Current..................................................... > 200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Range
[3]
Supply Voltage on VCC to Relative GND
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[3] .................................–0.5V to VCC + 0.5V
Commercial
Industrial
Ambient
Temperature (TA)[4]
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
Automotive-A
–40°C to +85°C
Automotive-E
–40°C to +125°C
Current into Outputs (LOW) .........................................20 mA
Electrical Characteristics Over the Operating Range
-55
Parameter
Description
VOH
Output HIGH
Voltage
Test Conditions
VCC = Min., IOH = –1.0 mA
Min.
-70
Typ.[2] Max.
2.4
Min.
Typ.[2] Max.
2.4
Unit
V
VOL
Output LOW Voltage VCC = Min., IOL = 2.1 mA
0.4
V
VIH
Input HIGH Voltage
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
V
VIL
Input LOW Voltage[3]
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage
Current
–1
+1
–1
+1
µA
IOZ
ICC
ISB1
ISB2
Output Leakage
Current
VCC Operating
Supply Current
GND ≤ VI ≤ VCC
GND ≤ VI ≤ VCC,
Output Disabled
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Commercial/
Industrial
Automotive-A
–1
+1
µA
Automotive-E
–10
+10
µA
–1
+1
µA
Commercial/
Industrial
–1
+1
Automotive-A
–1
+1
µA
Automotive-E
–10
+10
µA
6
15
mA
Automotive-A
6
15
mA
Automotive-E
6
25
mA
0.1
1
mA
0.1
1
mA
0.1
2
mA
2.5
15
µA
Automotive-A
2.5
15
µA
Automotive-E
2.5
25
µA
Commercial/
Industrial
Automatic CE
Max. VCC, CE1 ≥ VIH Commercial/
Power-down Current or CE2 < VIL,
Industrial
—TTL Inputs
VIN ≥ VIH or
Automotive-A
VIN ≤ VIL, f = fMAX
Automotive-E
Automatic CE
Max. VCC,
Power-down Current CE1 ≥ VCC – 0.3V,
or CE2 ≤ 0.3V,
—CMOS Inputs
VIN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f = 0
0.4
Commercial/
Industrial
7.5
0.1
2.5
20
2
15
Notes:
3. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
4. TA is the “Instant On” case temperature.
Document #: 001-06498 Rev. *A
Page 3 of 12
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CY62128BN
MoBL®
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Unit
9
pF
9
pF
Thermal Resistance[5]
Parameter
ΘJA
Description
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
32 SOIC
32 STSOP
32 TSOP
Unit
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
66.17
105.14
97.44
°C/W
30.87
14.09
26.05
°C/W
AC Test Loads and Waveforms
R1 1800Ω
R1 1800Ω
5V
ALL INPUT PULSES
5V
OUTPUT
VCC
90%
OUTPUT
100 pF
R2
990Ω
R2
990Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
GND
INCLUDING
JIG AND
SCOPE
(b)
90%
10%
10%
Fall TIme:
1 V/ns
Rise TIme:
1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
639Ω
1.77V
OUTPUT
Data Retention Waveform
VCC, min.
tCDR
VCC
DATA RETENTION MODE
VDR > 2V
VCC, min.
tR
CE1
or
CE2
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data
Retention Time
Conditions[6]
Min.
Max.
Unit
1.5
15
µA
1.5
25
µA
2.0
VCC = VDR = 2.0V,
CE1 ≥ VCC – 0.3V, or CE2 ≤ 0.3V,
VIN ≥ VCC – 0.3V or, VIN ≤ 0.3V
Commercial/
Industrial
Automotive-A
Automotive-E
Operation Recovery Time
tR
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
6. No input may exceed VCC + 0.5V.
Document #: 001-06498 Rev. *A
Typ.
V
0
ns
70
ns
Page 4 of 12
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CY62128BN
MoBL®
Switching Characteristics[7] Over the Operating Range
CY62128BN-55
Parameter
Description
Min.
Max.
CY62128BN-70
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
20
35
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[7, 9]
25
ns
tLZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z[9]
55
5
70
5
CE1 HIGH to High Z, CE2 LOW to High
tPU
CE1 LOW to Power-up, CE2 HIGH to Power-up
tPD
CE1 HIGH to Power-down, CE2 LOW to Power-down
ns
5
20
0
ns
25
0
55
ns
ns
0
20
Z[8, 9]
ns
5
0
tHZCE
WRITE CYCLE
70
ns
ns
70
ns
[10]
tWC
Write Cycle Time
55
70
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
45
60
ns
tAW
Address Set-up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
45
50
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
5
5
ns
tLZWE
tHZWE
WE HIGH to Low
Z[9]
WE LOW to High
Z[8, 9]
20
25
ns
Switching Waveforms
Read Cycle No.1[11, 12]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
11. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
12. WE is HIGH for read cycle.
Document #: 001-06498 Rev. *A
Page 5 of 12
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CY62128BN
MoBL®
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tHZCE
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
Write Cycle No. 1 (CE1 or CE2 Controlled)[14, 15]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tSCE
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Notes:
13. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
14. Data I/O is high impedance if OE = VIH.
15. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-06498 Rev. *A
Page 6 of 12
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CY62128BN
MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 16
tHZOE
Write Cycle No.3 (WE Controlled, OE LOW)[14, 15]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tSA
tHA
tPWE
WE
tSD
DATAI/O
NOTE 16
tHD
DATA VALID
tHZWE
tLZWE
Note:
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-06498 Rev. *A
Page 7 of 12
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CY62128BN
MoBL®
Truth Table
CE1
CE2
OE
WE
I/O0–I/O7
Mode
Power
H
X
X
X
High Z
Power-down
Standby (ISB)
X
L
X
X
High Z
Power-down
Standby (ISB)
L
H
L
H
Data Out
Read
Active (ICC)
L
H
X
L
Data In
Write
Active (ICC)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed (ns)
55
Ordering Code
Package
Diagram
CY62128BNLL-55SC
51-85081
32-pin 450-Mil SOIC
CY62128BNLL-55SXC
32-pin 450-Mil SOIC (Pb-Free)
CY62128BNLL-55SI
32-pin 450-Mil SOIC
CY62128BNLL-55SXI
CY62128BNLL-55ZAI
CY62128BNLL-55ZI
32-pin STSOP
51-85056
32-pin TSOP Type I
51-85081
32-pin 450-Mil SOIC
51-85056
32-pin TSOP Type I
32-pin TSOP Type I (Pb-Free)
51-85081
32-pin 450-Mil SOIC
51-85094
32-pin STSOP
51-85056
32-pin TSOP Type I
51-85056
32-pin TSOP Type I (Pb-Free)
CY62128BNLL-70SXI
CY62128BNLL-70ZAI
32-pin STSOP (Pb-Free)
CY62128BNLL-70ZXI
CY62128BNLL-70ZXA
Industrial
32-pin 450-Mil SOIC (Pb-Free)
CY62128BNLL-70ZAXI
CY62128BNLL-70ZI
Commercial
32-pin 450-Mil SOIC (Pb-Free)
CY62128BNLL-70ZXC
CY62128BNLL-70SI
Industrial
32-pin TSOP Type I (Pb-Free)
CY62128BNLL-70SXC
CY62128BNLL-70ZC
Commercial
32-pin STSOP (Pb-Free)
CY62128BNLL-55ZXI
CY62128BNLL-70SC
Operating
Range
32-pin 450-Mil SOIC (Pb-Free)
51-85094
CY62128BNLL-55ZAXI
70
Package Type
32-pin TSOP Type I (Pb-Free)
CY62128BNLL-70SXA
51-85081
32-pin 450-Mil SOIC (Pb-Free)
CY62128BNLL-70SXE
51-85081
32-pin 450-Mil SOIC (Pb-Free)
CY62128BNLL-70ZAXE
51-85094
32-pin STSOP (Pb-Free)
Automotive-A
Automotive-E
Please contact your local Cypress sales representative for availability of these parts
Document #: 001-06498 Rev. *A
Page 8 of 12
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CY62128BN
MoBL®
Package Diagrams
32-pin (450 Mil) Molded SOIC (51-85081)
16
1
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
17
32
0.793[20.142]
0.817[20.751]
0.006[0.152]
0.012[0.304]
0.101[2.565]
0.111[2.819]
0.118[2.997]
MAX.
0.004[0.102]
0.050[1.270]
BSC.
0.004[0.102]
MIN.
0.014[0.355]
0.020[0.508]
SEATING PLANE
Document #: 001-06498 Rev. *A
0.047[1.193]
0.063[1.600]
0.023[0.584]
0.039[0.990]
51-85081-*B
Page 9 of 12
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CY62128BN
MoBL®
Package Diagrams (continued)
32-pin STSOP (8 x 13.4 mm) (51-85094)
51-85094-*D
Document #: 001-06498 Rev. *A
Page 10 of 12
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CY62128BN
MoBL®
Package Diagrams (continued)
32-pin TSOP Type I (8 x 20 mm) (51-85056)
51-85056-*D
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-06498 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62128BN
MoBL®
Document History Page
Document Title: CY62128BN MoBL® 1-Mbit (128K x 8) Static RAM
Document Number: 001-06498
REV.
ECN NO.
Issue Date
Orig. of
Change
**
426503
See ECN
NXR
New Data Sheet
*A
488954
See ECN
NXR
Added Automotive product
Removed RTSOP Package
Updated ordering Information table
Document #: 001-06498 Rev. *A
Description of Change
Page 12 of 12
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