Austin AS3SSD4GB8PBGR/IT Solid state disk on chip (ssdoc) Datasheet

AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
Solid State Disk On Chip
(SSDoC)
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
FEATURES
• Capacities
- 4 GB
- 8 GB
- 16 GB
• PATA Compatibility
- ATA-5 compatible
- UDMA4 supported
- PIO Mode 4 supported
- MWDMA Mode 2 supported
• Performance
- Sustained Sequential Read Bandwidth:16 MB/s
- Sustained Sequential Write Bandwidth: 5 MB/s
• Form Factor
- BGA Package
• 31 mm (W) x 31 mm (L) x 4.2-7.8 mm (H)
• Weighs approximately 11 grams (TYP)
• Each NAND component, either a 4, 8 or 16Gb
device, based on the use of single and stacked
silicon solutions
• ECC correction = 6 Bytes within a 512 Byte
sector
• Automatic sleep mode
• Controller contained in base interposer
• SLC (Single-Level Cell) NAND Flash
• Reliability
- Mean Time Between Failure (MTBF)
>2,000,000 Hours (est.)
- Program/Erase >1,000,000 Times (est.)
- Temp Cycle 500/1000 cycles, JEDEC A104
Condition B -55ºC to +125ºC
• Power Supply Voltage: 5.0V or 3.3 V ± 10%
(TYP)
• Power Consumption (Vcc = 5.0 V)
- Idle: 10 mW (TYP)
- Active: 255 mW (TYP)
• Operating Temperature
- Commercial: 0C to 70C
- Industrial: -45C to 85C
• Shock and Vibration
- Shock: 1500G MIL-STD0810F
- Vibration: 15 G RMS MIL-STD0810F
• Compliances
- Lead free
- RoHS
- Sn/Pb Ball Option
OVERVIEW
The solid state disk is based on a proprietary
package stacking technology to create an extremely
space conscious, robust Solid State Disk. The SSD
is capable of operating in harsh, vibration prone
product platforms such embedded computing
applications, heavy transportation, ultra portables,
handhelds,
mobile
computing,
digital
radio, high-speed networking & enterprise
applications, as well as, military, aerospace and
industrial applications.
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
KEY FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
NAND FLASH Controller
(2) stacks, each containing (2 or 4) NAND components
Each NAND component, either a 4,8 or 16Gb device, based on the use of single
silicon and stacked silicon solutions
Providing a total bit density of either 4,8 or 16GB
Controller contained in base interposer
Fast ATA host to buffer transfer rates supporting True IDE, PIO/4 mode support
512Byte Sector Buffers
Flash Memory power-down logic
ECC correction = 6 Bytes within a 512 Byte sector
Automatic Sleep Mode
Burst Transfer rate, 16.67MB per second
Sustained Transfer rate: 6.7MB per second
Sophisticated Wear Leveling
ARCHITECTURE
The PATA controller in the PATA Solid State Drive utilizes a 32-bit RISC architecture which provides for
direct connection of one, two or four NAND flash memory devices (2 per channel). An on-chip error
correction code (ECC) and cyclic redundancy check (CRC) unit generates the required code bytes
facilitating error detection and correction of up to six bytes per 512 byte data sector. On the fly code
byte generation for read and write operations minimizes ECC performance impacts.
The controller’s flash memory interface allows the direct connection of up to 10 chips and support
Samsung (NAND) type flash memory. ASI PATA Solid State Drives use single level cell (SLC) Samsung
NAND Flash Memory devices.
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
BLOCK DIAGRAM
16 Gb
Dual
enable
NAND
16 Gb
Dual
enable
NAND
16 Gb
Dual
enable
NAND
16 Gb
Dual
enable
NAND
16 Gb
Dual
enable
NAND
16 Gb
Dual
enable
NAND
16 Gb
Dual
enable
NAND
16 Gb
Dual
enable
NAND
Controller
IDE Interface
REGULATORY COMPLIANCE
Since the PATA SSD is a component (or a set of components depending on the configuration) on the
motherboard, system certifications are the responsibility of the OEM or ODM.
DEVICE COMPLIANCE
Compliance
PB Free
RoHS
Description
Components and materials are lead free.
Restriction of Hazardous Substance Directive
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
PRODUCT SPECIFICATIONS
Capacity and User Addressable Sectors
Unformatted
4GB*
8GB*
16GB*
User Addressable Sector in LBA mode
7,880,544
15,761,088
31,522,176
Note: Formatting and other functions will use some of the space, thus
the listed capacity will not be available entirely for data storage.
Read and Write Perfomance
Operation
READ
WRITE
Access Type
Sustained Sequential Read Bandwidth
Sustained Sequential Write Bandwidth
MB/second
16 MB/second
5 MB/second
OPERATING CONDITIONS
Maximum Ratings
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not guaranteed.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings by Device
Parameter
Vcc supply voltage
Non-Operation Temperature
Symbol
Max.
Min.
Vcc_P
-0.5
+5.5
Ti
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
-40
+85
Unit
V
o
C
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
AUSTIN SEMICONDUCTOR,
INC.
SOLID
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
PRELIMINARY
Austin Semiconductor, Inc.
OPERATING CONDITIONS (continued)
Recommended Operating Conditions
Operating Temperature and Voltages
Parameter
o
Symbol
T0
o
Industrial: 0 C to +70 C
o
o
T0
Commercial: -40 C to +85 C
Vcc supply voltage
Ground supply voltage
Tcc_P
Tcc_P
GndPLN
Max.
Typ
Min.
0
-
70
o
70
5.5
3.6
0
o
0
4.5
3.0
0
5
3.3
0
Unit
C
C
V
V
V
DC Characteristics (PATA controller configuration)
Symbol
Paramenter
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
VOL
Output LOW Voltage
VOH
Output HIGH Voltage
Min.
-0.3
Max.
+0.8
Units
V
2.2
Vcc+0.3
V
0.45
V
IOL=4mA
V
IOH=-1mA
2.4
Conditions
Operating Current, VCC_R=5.0V
Sleep Mode
0.2
mA
Operating, 20 MHz
30
mA
Operating, 40 MHz
Operating Current, VCC_R=3.3V
50
mA
Sleep Mode
.02
m
Operating, 20 MHz
30
m
ILI
Operating, 40 MHz
Input Leakage Current
50
±10
m
μA
ILO
Output Leakage Current
±10
μA
CI/O
Input / Output Capacitance
10
pF
ICC
ICC
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
ELECTRICAL CHARACTERISTICS
Power Consumption
Setting
Value
Active Idle Current
Active Current
Active Power
Idle Power
1.85mA
51mA
255mW
9.25mW
ENVIRONMENTAL CONDITIONS
Temperature Specifications
Mode
Ambient Temperature
Operate - Commercial
Operate - Industrial
Max.
Min.
0
-40
+70
+85
Unit
o
o
C
C
Altitude
Since there are no moving parts, this device is not susceptible to a lack of air molecules and will operate correctly to 85,000 feet above sea level.
Shock and Vibration Characteristics
Condition
Operating Shock
Operating Vibration
Value
1500G MIL-STD-810F
15G RMS MIL-STD-810F
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
ENVIRONMENTAL CONDITIONS (continued)
Acoustics
This drive has no moving or noise-emitting parts; therefore, it produces negligible sound (0dB) in all
modes of operation.
Electrostatic Discharge (ESD)
The PATA SSD can withstand an electrostatic discharge of +/- of 2 KV. ESD testing is done to demonstrate that the units can withstand discharge encountered in normal handling or operations of the
equipment.
Humidity Specifications
Condition
Operate non-condensing
Value
Unit
5-95
%
Reliability Specifications
Parameter
Mean Time Between Failure (MTBF)
Program / Erase
Warranty
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Value
>2,000,000 Hours (est.)
>1,000,000 Time (est.)
2 Years
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
MECHANICAL INFORMATION
PATA SSD (Top, Side and Bottom Views)
o0.76
381 PLCS
1.27mm
0.61mm
7.41mm
1.27mm
29.21 SQ.
31.00 SQ.
Stacks, each containing (2 or 4) NAND Components
4GB
8GB & 16GB
0.61mm
5.01mm
(2)high + base
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
0.61mm
7.41mm
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
PIN ASSIGNMENTS
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
PIN ASSIGNMENTS (continued)
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
Vcc_P
Vcc_P
Vcc_P
IDE_D8
BLANK
BLANK
BLANK
BLANK
VccNAND_IN
VccNAND_IN
VccNAND_IN
IDE_D3
FOUT
FOUT
FOUT
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
Vcc_F
Vcc_F
Vcc_F
NC
VccPLN_IN
NC
FOUT
FOUT
NC
XTALI
XTALC
XTALR
Vcc_C
NC
NC
Vcc_F
NC
NC
VccPLN_IN
FC_RESET
NC
Vcc_F
Vcc_F
Vcc_F
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
FC_WP_EN1
FC_WP_EN1
VccNAND_IN
VccNAND_IN
VccNAND_IN
BLANK
BLANK
BLANK
BLANK
IDE_D8
IDE_D8
IDE_D8
IDE_D2
BLANK
BLANK
BLANK
BLANK
VccNAND_IN
VccNAND_IN
GndPLN
GndPLN
GndPLN
GndPLN
VccNAND_IN
VccNAND_IN
BLANK
BLANK
BLANK
BLANK
FADJ
FOUT
FOUT
FOUT
GndPLN
GndPLN
NC
VccPLN_IN
VccPLN_IN
VccPLN_IN
FOUT
FOUT
XTALI
XTALC
XTALR
Vcc_C
GndPLN
Vcc_C
Vcc_F
GndPLN
Vcc_F
VccPLN_IN
VccPLN_IN
VccPLN_IN
FC_RESET
NC
GndPLN
GndPLN
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
IDE_D2
IDE_D2
IDE_D2
IDE_D9
BLANK
BLANK
BLANK
BLANK
VccNAND_IN
GndPLN
GndPLN
GndPLN
GndPLN
GndPLN
GndPLN
VccNAND_IN
BLANK
BLANK
BLANK
BLANK
NC
FADJ
FADJ
FADJ
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
GndPLN
GndPLN
NC
VccPLN_IN
VccPLN_IN
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
VccPLN_IN
FOUT
FOUT
XTALI
XTALC
XTALR
Vcc_C
GndPLN
Vcc_C
Vcc_F
GndPLN
Vcc_F
VccPLN_IN
VccPLN_IN
VccPLN_IN
FC_RESET
NC
GndPLN
GndPLN
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
IDE_D9
IDE_D9
IDE_D9
IDE_PIOIS16\
BLANK
BLANK
BLANK
BLANK
GndPLN
GndPLN
GndPLN
GndPLN
GndPLN
GndPLN
GndPLN
GndPLN
BLANK
BLANK
BLANK
BLANK
NC
Vcc_R
Vcc_R
Vcc_R
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
IDE_PIOIS16\
IDE_PIOIS16\
IDE_PIOIS16\
IDE_D10
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
Vcc_R
GndPLN
GndPLN
GndPLN
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
IDE_D10
IDE_D10
IDE_D10
FC_WP_EN
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
CADJ
Vcc_R
Vcc_R
Vcc_R
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
FC_WP_EN
FC_WP_EN
FC_WP_EN
NC
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
COUT
CADJ
CADJ
CADJ
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Vcc_F
Vcc_F
Vcc_F
Vcc_F
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
BLANK
Vcc_F
COUT
COUT
COUT
GndPLN
GndPLN
NC
VccPLN_IN
VccPLN_IN
VccPLN_IN
FOUT
FOUT
XTALI
XTALC
XTALR
Vcc_C
GndPLN
Vcc_C
Vcc_F
GndPLN
Vcc_F
VccPLN_IN
VccPLN_IN
VccPLN_IN
FC_RESET
NC
GndPLN
GndPLN
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
SIGNAL DESCRIPTIONS
g
Symbol
IDE_A0
IDE_A1
IDE_A2
IDE_D0
IDE_D1
IDE_D2
IDE_D3
IDE_D4
IDE_D5
IDE_D6
IDE_D7
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
IDE_INTRQ
Type
Output
Output
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
IDE_IOWR\
Input
IDE_IORD\
Input
IDE_CS0\
Input
IDE_CS1\
Input
IDE_PIOIS16\
IDE_PDIG
Output
Input/Output
IDE_DMARQ
IDE_DMARQ\
Output
FC_WAIT
Output
Description
Address bus
Data bus. The signals D15..D0 represent the bidirectional
data bus; active high signals a "one".
Drive interrupt request.
I/O Data Write Enable is the strobe signal asserted by the
host to write device registers or the data port.
DIOW shall be negated by the host prior to the initiation of
an Ultra DMA burst. STOP shall be negated by the host
before the data is transferred in an Ultra DMA burst. The
assertion of STOP by the host during an Ultra DMA burst
signals the termination of the Ultra DMA burst.
I/O Data Read Enable is the strobe signal asserted by the
host to read device registers or the data port.
Drive chip select 0 is used by host to select Command
Block registers.
Drive chip select 1 is used by host to select Command
Block registers.
16-bit I/O transfer.
Passed diagnostics.
DMA request. This signal, used for DMA data transfers
between host and device, shall be asserted by the device
when it is ready to transfer data to or from the host. For
multi word DMA transfers, the direction of data transfer is
Controller by IDE_IORD\ and IDE_IOWR\. When a DMS
operation is enabled, CS0\ and CS1\ shall not be asserted
and transfers shall be 16 bits wide. This signal shall be
release when the device is not selected.
Ready signal to IDE_IORDY
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
IDE_PRESET
FC_WP_EN
FC_WP_EN1
Input
Input
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
Reset
Write protect signal
# Reset processor. RESET# low resets the processor to the
initial state and halts all activity. RESET# must be low for
at least one cycle. On a transition from low to high, a Reset
exception occurs and the processor starts execution at the
Reset entry determined by the INT4 state. The transition
may occur asynchronously to the clock. We recommend
connecting this pin to a voltage monitoring circuit with
open-drain output (e.g. Torex XC61A) supplying a reset
signal for supply voltages less than 2.6 or 2.7V, connected
to a R/C combination of 100 kΩ and 100 nF giving an
additional reset delay in the order of 10 ms.
Operation LED signal
FC_RESET
Input
FC_LED\
FC_MODE
FC_IDEEN
Output
XTALR
Output
XTALC
Output
XTALI
Input
NC
Vcc_C
Supply
Master/Slave select and connect to IDE_CSEL for Cable
select option
R/C Clock Oscillator Resistor Output. The resistor
connected between this pin and XTALI determines the
operating clock frequency. Use a 470Ω resistor to obtain a
frequency of about 20 MHz
R/C Clock Oscillator Capacitor Output. Connect a 22pF
capacitor between this pin and XTALI.
R/C Clock Oscillator Input. This input connects to the other
side of the resisors and the capacitor connected to XTALR1,
XTALR2 and XTALC. Connect a 22pF capacitor from this pin
to ground.
Not connected
Power Supply Voltage, Core
Vcc_R
Supply
Power Supply Voltage, Regulator
Vcc_F
Supply
Power Supply Voltage, Flash Memory
Vcc_P
Supply
FADJ
Input
FOUT
Output
CADJ
Input
COUT
Output
VccNAND_IN
VccPLN_IN
GndPLN
Supply
Supply
Supply
Power Supply Voltage, controller
3.3V Flash Memory Power Supply Adjustment. Connect a
270pF capacitor from this pin to FOUT.
3.3V Flash Memory Power Supply. This output provides a
regulated 3.3V supply if the power supply voltage is above
3.3V. This supply voltage must also be connected to the
VCC_F pins.
2.5V Core Power Supply Adjustment. Connect a 220kΩ
resistor from this pin to GND, a 220kΩ resistor from this
pin to COUT, and a 270pF capacitor from this pin to COUT.
2.5V Core Power Supply. This output provides a regulated
2.5V supply if the power supply voltage is above 3.3V. This
supply voltage must be connected to the VCC_C pins.
3.3V Flash Memory Power Supply
Supply to the controller
Supply ground
Output
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
TYPICAL APPLICATION DESIGN
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
COMMAND SETS
The PATA SSD device supports all the mandatory ATA commands as defined in the ATA/ATAPI-5 specification.
ATA General Feature Command Set
The PATA SSD device supports the ATA General Feature command set.
Common Name
EXECUTE DEVICE DIAGNOSTIC
IDENTIFY DEVICE
IDENTIFY DEVICE DMA
INITIALI E DRIVE PARAMETERS
NOP
READ BUFFER
READ DMA
READ LONG
READ MULTIPLE
READ NATIVE MAX ADDRESS
READ SECTOR(S)
READ VERIFY SECTOR(S)
RECALIBRATE
SEEK
SET FEATURES
SET MULTIPLE MODE
SMART
TRANSLATE SECTOR
WRITE BUFFER
WRITE DMA
WRITE LONG
WRITE MULTIPLE
WRITE MULTIPLE without ERASE
WRITE SECTOR(S)
WRITE SECTOR(S)without ERASE
WRITE VERIFY
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Code
90h
ECh
EEh
91h
00h
E4h
C8h, C9h
22h, 23h
C4h
F8h
20h, 21h
40h, 41h
1Xh
7Xh
EFh
C6h
B0h
87h
E8h
CAh, CBh
32h, 31h
C5h
CDh
30h, 31h
38h
3Ch
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
14
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
REFERENCE
This document also references standards and specifications defined by a variety of organizations.
Please use the following information to identify the location of an organization's standards information.
DateorRevisionNumber
February2000
December2004
March2006
January2007
Title
Location
http://www.t13.org/Documents/
UploadedDocuments/project/d1321r3Ͳ
ATAATAPIͲ5.pdf
ATAͲ5
JEDECStandardJESD22ͲC101C:
FieldͲInduced
ChargedͲDeviceModelTest
MethodforElectrostaticͲ
DischargeͲWithstandThresholds
ofMicroelectronicComponents
HyperstonF2Ͳ16x,32ͲBitFlashMemory
ControllerSpecification
JEDECStandard:Electrostatic
Discharge(ESD)Sensitivity
TestingHumanBodyModel(HBM)
http://www.jedec.org/download/search/
default2.cfm
http://www.hyperstone.com/fmc_f2_en,15593.html
http://www.jedec.org/download/search/
default2.cfm
GLOSSARY
This document incorporates many industry and device specific words. Use the following list to define a
variety of terms and acronyms.
y
y
Term
ATA
CFA
CPRM
CRC
DMA
ECC
ESD
HDD
HPA
IDE
LBA
MTBF
MWDMA
ODM
OEM
PATA
PCMCIA
PIO
SATA
SSD
UMDA
Definition
Advanced Technology Attachment
CompactFlash Association
Content Protection for Recordable Media
Cyclic Redundancy Check
Direct Memory Access
Error Correction Code
Electrostatic Discharge
Hard Disk Drive
Host Protected Area
Integrated Device Electronics
Logical Block Addressing
Mean Time Between Failure
Multi-word DMA
Original Design Manufacturer
Original Equipment Manufacturer
Parallel ATA
Personal Computer Memory Card International Assocoation
Programmable Input / Output
Serial ATA
Solid state drive
Ultra DMA, also know Ultra ATA
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
AUSTIN SEMICONDUCTOR,
INC.
SOLID
ST
ATE DISK
STA
PRELIMINARY
Austin Semiconductor, Inc.
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
ORDER CHART
PartNumber
AS3SSD4GB8PBGR/IT
AS3SSD8GB8PBGR/IT
AS3SSD16GB5PBGR/IT
AS3SSD4GB8PBGR/CT
AS3SSD8GB8PBGR/CT
AS3SSD16GB5PBGR/CT
StorageDensity
4GB
8GB
16GB
4GB
8GB
16GB
SustainedTransferRate
7.7MB/sec
7.7MB/sec
5.0MB/sec
7.7MB/sec
7.7MB/sec
5.0MB/sec
AvailableProcesses
o
o
CT=CommercialTemperatureRange 0 Cto+70 C
IT=IndustrialTemperatureRange
Ͳ40°Cto+85°C
R=RoHSCompliant/LeadFree
Blank=Sn/PbFinishOption
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
AUSTIN SEMICONDUCTOR,
INC.
SOLID
PRELIMINARY
Austin Semiconductor, Inc.
ST
ATE DISK
STA
AS3SSD4GB8PBG
AS3SSD8GB8PBG
AS3SSD16GB5PBG
DOCUMENT TITLE
4GB, 8GB, 16GB Solid State Disk on Chip
REVISION HISTORY
Rev #
1.0
1.1
1.2
1.3
History
Initial Release
Updated Mechanical Information
Updated Order Chart
Updated 4GB & 8GB Drawing
AS3SSD4GB8PBG, AS3SSD8GB8PBG, AS3SSD16GB5PBG
Rev. 1.3 07/09
Release Date
December 2008
January 2009
March 2009
July 2009
Status
Preliminary
Preliminary
Preliminary
Preliminary
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
Similar pages