Sony CXA3275Q Pll/osc/mix ic for digital tuner Datasheet

CXA3275Q
PLL/OSC/MIX IC for Digital Tuner
Description
The CXA3275Q is a monolithic tuner IC for single
conversion system digital broadcast tuners. This IC
integrates three sets of local oscillator and mixer
circuits (VHF Low Band/ VHF High Band/UHF Band),
an IF amplifier and a tuning PLL onto a single chip,
enabling further miniaturization of the tuner.
Features
• Balanced oscillators with low-phase noise and
excellent oscillation stability (UHF: 4 pins, VHF: 2 pins)
• High linearity mixer and IF amplifier
• IF output switchable between balanced and
unbalanced
• Low-phase noise PLL synthesizer
(3-wire bus format)
• Reference frequency programmable in 4 bits
• On-chip high voltage drive transistor for charge
pump
• On-chip 4-output band switch (PNP transistor
on/off)
• 40-pin QFP package
Applications
Digital CATV tuners
40 pin QFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage Vcc, PLLVcc
–0.3 to +6.0
V
IFVcc
–0.3 to +6.0
V
• Storage temperature
Tstg
–55 to +150 °C
• Allowable power dissipation
PD
1.58
W
(when mounted on a printed circuit board)
Operating Conditions
• Supply voltage Vcc, PLLVcc
IFVcc
• Operating temperature
Topr
4.5 to 5.5
4.5 to 5.5
V
V
–40 to +80
°C
Structure
Bipolar silicon monolithic IC
This IC has pins whose electrostatic discharge strength is weak as a high-frequency process is used for this IC.
Take care when handling the IC.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00461-PS
CXA3275Q
NC
BS4
BS3
BS2
BS1
VLIN1
VLIN2
VHIN1
VHIN2
UIN1
Block Diagram and Pin Configuration
30
29
28
27
26
25
24
23
22
21
PLLVcc 31
20 UIN2
VLMIX
VHMIX
UMIX
CP 32
19 Vcc
VT 33
18 MIXOUT1
XI 34
17 MIXOUT2
XO 35
Ref
OSC
Charge
Pump
Ref
Div.
Phase
Det
16 GND
Band
SW
15 IFIN1
PLLGND 36
Program
Div.
14 IFIN2
LOCK 37
Bus
Interface
SDA 38
Lock
Det
13 RFGND
12 UOSCB1
SCL 39
IF Amp
5
IFOUT1
IFOUT2
IFVcc
IFGND
VLOSC2
6
7
8
9
10
UOSCE2
4
UOSCB2
3
VHOSC1
2
UOSC
VHOSC2
1
VHOSC
VLOSC1
VLOSC
CE 40
–2–
11 UOSCE1
CXA3275Q
Pin Description and Equivalent Circuit
Pin
No.
Symbol
Pin voltage
[V]
Equivalent circuit
IFVcc
3
1
Description
IF outputs.
IFOUT1 and IFOUT2 output a
balanced signal.
When taking a signal as an
unbalanced output, connect
the pin not used for output to
IFVCC. At this time the output
stage current is saved.
IFOUT1
40k
2.5
1
2
2
IFOUT2
3
IFVcc
—
IF amplifier power supply.
4
IFGND
—
IF amplifier GND.
5
6
Vcc
19
5
VLOSC2
2.5
20k
20k
External resonance circuit
connection for VL oscillator.
3k
3k
6
VLOSC1
2.5
20k
20k
7
8
Vcc
19
7
VHOSC2
2.5
20k
20k
External resonance circuit
connection for VH oscillator.
3k
3k
8
VHOSC1
9
UHF: 2.2
UOSCB2 VL/VH: 2.3
10
UOSCE2
2.5
20k
9
3k
3k
UOSCE1
UHF: 1.5
VL/VH: –
12
UOSCB1
UHF: 2.2
VL/VH: 2.3
13
RFGND
10
11
19
UHF: 1.5
VL/VH: –
11
20k
12
Vcc
External resonance circuit
connection for UHF oscillator.
Analog GND.
—
–3–
CXA3275Q
Pin
No.
Symbol
Pin voltage
[V]
Equivalent circuit
Description
IFVcc
3
14
IFIN2
2.7
14
15
IF inputs.
5k
15
IFIN1
2.7
16
GND
0
17
MIXOUT2
—
5k
GND
18
17
20
20
Mixer outputs.
18
MIXOUT1
—
19
Vcc
—
20
UIN2
VL/VH: 0
UHF: 1.9
Band switch, mixer and local
oscillator circuit power supply.
Vcc
19
UHF inputs.
21
UIN1
22
VHIN2
23
VHIN1
24
VLIN2
25
VLIN1
VL/VH: 0
UHF: 1.9
VH: 3
VL: 3.16
UHF: 3.24
VH: 3
VL: 3.16
UHF: 3.24
VH: 3.16
VL: 3
UHF: 3.24
VH: 3.16
VL: 3
UHF: 3.24
20
21
Vcc
19
22 24
23 25
VH and VL inputs.
5k
5k
–4–
CXA3275Q
Pin
No.
Symbol
Pin voltage
[V]
Equivalent circuit
Vcc
19
26
Description
BS1
20k
ON: 4.9
OFF: 0
Pin 26: Band switch 1 output.
Pin 29: Band switch 4 output.
The pin corresponding to the
band selected by the data
goes High.
26
29
29
BS4
Vcc
19
27
20k
BS2
Pin 27: Band switch 2 output.
Pin 28: Band switch 3 output.
27
ON: 4.9
OFF: 0
28
The pin corresponding to the
band selected by the data
goes High.
70k
30k
28
BS3
30
NC
—
NC.
31
PLLVcc
—
PLL VCC.
PLLVcc
31
32
CP
Charge pump output.
Connects the loop filter.
—
32
33
50
33
VT
Transistor open collector
output for varicap diode drive.
Connects the loop filter.
—
PLLVcc
34
XI
31
3.1
500
34
External reference clock input.
Connects the crystal when
used as a reference oscillator.
35
35
XO
3.0
Connects the crystal when
used as a reference oscillator.
36
PLLGND
—
PLL GND.
–5–
CXA3275Q
Pin
No.
Symbol
Pin voltage
[V]
Equivalent circuit
Description
PLLVcc
31
5.0
(lock)
37
37
LOCK
Lock detection.
High when locked, Low when
unlocked.
0.2
(unlock)
PLLVcc
31
5k
38
38
SDA
Data input.
—
20
PLLVcc
31
5k
39
SCL
39
—
Clock input.
PLLVcc
31
150k
40
CE
1.25
(when open)
40
Enable pin.
50k
–6–
CXA3275Q
Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.)
(Vcc = 5V, IFVcc = 5V, PLLVcc = 5V, Ta = 25°C)
Circuit Current
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
Iccv1
During VHF operation
Unbalanced output
Band switch output open
80
113
145
mA
Iccu1
During UHF operation
Unbalanced output
Band switch output open
85
120
151
mA
Iccv2
During VHF operation
Balanced output
Band switch output open
91
130
170
mA
Iccu2
During UHF operation
Balanced output
Band switch output open
100
137
177
mA
Circuit current
OSC/MIX/IF Amplifier Block
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
CG1-1
VL operation
fRF = 50MHz, fIF = 39MHz
18.5
21.5
25
dB
CG1-2
VL operation
fRF = 150MHz, fIF = 39MHz
19
22
25.5
dB
CG1-3
VH operation
fRF = 150MHz, fIF = 39MHz
19
22
25.5
dB
CG1-4
VH operation
fRF = 450MHz, fIF = 39MHz
19
22
25.5
dB
CG1-5
UHF operation fRF = 450MHz, fIF = 39MHz
23.5
26.5
30
dB
CG1-6
UHF operation fRF = 850MHz, fIF = 39MHz
24.5
27.5
31
dB
CG2-1
VL operation
fRF = 50MHz, fIF = 39MHz
25.5
28.5
32
dB
CG2-2
VL operation
fRF = 150MHz, fIF = 39MHz
26
29
32.5
dB
Conversion gain 2 ∗1, ∗2 CG2-3
(Balanced)
CG2-4
VH operation
fRF = 150MHz, fIF = 39MHz
26
29
32.5
dB
VH operation
fRF = 450MHz, fIF = 39MHz
26
29
32.5
dB
Conversion gain 1 ∗1
(Unbalanced)
Noise figure ∗1, ∗3
(Unbalanced)
CG2-5
UHF operation fRF = 450MHz, fIF = 39MHz
30.5
33.5
37
dB
CG2-6
UHF operation fRF = 850MHz, fIF = 39MHz
31.5
34.5
38
dB
NF1
VL operation
fRF = 50MHz, fIF = 39MHz
15.5
18.5
dB
NF2
VL operation
fRF = 150MHz, fIF = 39MHz
15
18
dB
NF3
VH operation
fRF = 150MHz, fIF = 39MHz
15
18
dB
NF4
VH operation
fRF = 450MHz, fIF = 39MHz
15
18
dB
NF5
UHF operation fRF = 450MHz, fIF = 39MHz
10.5
13.5
dB
NF6
UHF operation fRF = 850MHz, fIF = 39MHz
10.5
13.5
dB
–7–
CXA3275Q
OSC/MIX/IF Amplifier Block (cont.)
Symbol
Item
∗1, ∗4
1% cross modulation 1
(Unbalanced)
∗1, ∗5
1% cross modulation 2
(Unbalanced)
Maximum output power
Phase noise 1
Phase noise 2
∗6
∗6
∗6, ∗7
Oscillator phase noise
Measurement conditions
Min.
Typ.
Max.
Unit
CM1-1
VL operation fD = 50MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)
83.5
87.5
dBµ
CM1-2
VL operation fD = 150MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)
83.5
87.5
dBµ
CM1-3
VH operation fD = 150MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)
83
87
dBµ
CM1-4
VH operation fD = 450MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)
83
87
dBµ
CM1-5
UHF operation fD = 450MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)
78
82
dBµ
CM1-6
UHF operation fD = 850MHz, fIF = 39MHz,
fUD = ±6MHz (80% AM)
77
81
dBµ
CM2-1
VL operation fD = 50MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)
91.5
95.5
dBµ
CM2-2
VL operation fD = 150MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)
91.5
95.5
dBµ
CM2-3
VH operation fD = 150MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)
90
94
dBµ
CM2-4
VH operation fD = 450MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)
89
93
dBµ
CM2-5
UHF operation fD = 450MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)
85
89
dBµ
CM2-6
UHF operation fD = 850MHz, fIF = 39MHz,
fUD = ±12MHz (40% AM)
84
88
dBµ
+10
+13
dBm
Pomax 50Ω load, saturation output, fIF = 45MHz
PN 1
1kHz offset
Phase comparison frequency = 218.75kHz
Charge pump current: 900µA
73
dBc/Hz
PN 2
10kHz offset
Phase comparison frequency = 218.75kHz
Charge pump current: 900µA
90
dBc/Hz
C/N
50kHz offset
Phase comparison frequency = 218.75kHz
Charge pump current variable
70
dBc
–8–
60
CXA3275Q
∗1 Value measured with the untuned input.
∗2 Value compensated for the loss due to the external parts connected to Pins 1 and 2, and converted to the
IC output pin amplitude.
∗3 Noise figure is the direct-reading value of NF meter in DSB.
∗4
SG1
Ypad
fD
–30dBm
Spectrum analyzer
DUT
SG2
fD ± 6MHz
AM80%, Audio 100kHz
Input value (SG2, 50Ω termination) when S/I = 46dB with the spectrum analyzer
∗5
SG1
Ypad
fD
–30dBm
Spectrum analyzer
DUT
SG2
fD ± 12MHz
AM40%, Audio 100kHz
Input value (SG2, 50Ω termination) when S/I = 46dB with the spectrum analyzer
∗6 Value when 14MHz (300mVp-p) is SG (Hewlett-Packard Japan, Ltd.: 8644A) input as the external REF
CLOCK.
∗7 The spectrum analyzer is set for SPAN:100kHz, RBW:3kHz and VBW:100Hz.
–9–
CXA3275Q
PLL Block
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
Lock-up time 1
LUT1
fosc 89MHz ←
→ fosc 479MHz
10
ms
Lock-up time 2
LUT2
fosc 479MHz ←→ fosc 889MHz
10
ms
Reference leak
REFL
Phase comparison frequency = 218.75kHz
65
dBc
CL and DA input
"H" level input voltage
VIH
3
Vcc
V
"L" level input voltage
VIL
GND
1.5
V
"H" level input current
IIH
VIH = Vcc
0
–0.1
µA
"L" level input current
IIL
VIL = GND
–0.2
–4
µA
CE input
"H" level input voltage
VIH
3
Vcc
V
"L" level input voltage
VIL
GND
1
V
"H" level input current
IIH
VIH = Vcc
100
200
µA
"L" level input current
IIL
VIL = GND
–35
–100
µA
Output current 1
ICPO2
When 300µA is selected
±210
±300
±420
µA
Output current 2
ICPO4
When 900µA is selected
±600
±900
±1215
µA
33
V
0.3
0.8
V
CPO (charge pump)
VT (VC voltage output)
Maximum output voltage
VTH
Minimum output voltage
VTL
Sink current = 1mA
REFOSC
Oscillation frequency range FXTOSC
3
4
5
MHz
Drive frequency
REFIN1
3
14
20
MHz
Drive level
REFIN2
External reference clock: sine wave
250
350
500
mVp-p
Output current
IBS
When ON
–5
mA
Saturation voltage
VSAT
When ON
150
300
mV
Leak current
LeakBS
When OFF IFVCC = 5.5V
0.5
3
µA
"H" output voltage
VLOCKH
When locked
Vcc
V
"L" output voltage
VLOCKH
When unlocked
0.5
V
Band SW
Source current = 5mA
LOCK
– 10 –
Vcc – 1 Vcc – 0.3
0
0.1
CXA3275Q
PLL Block (cont.)
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
Unit
Bus timing (3-wire bus)
Data setup time
Data hold time
Enable waiting time
Enable setup time
Enable hold time
tSD
tHD
tWE
tSE
tHE
– 11 –
300
ns
600
ns
300
ns
300
ns
600
ns
CXA3275Q
Electrical Characteristics Measurement Circuit
Inductance Constants
0.5
1.5T
3.4φ
30
1n
PLLGND
LOCK
DA
56p 200
CL
56p 200
1n
CE
2k
VLIN2
34
MIXOUT2
17
4T 1n
5V
36
IFIN1
15
37
IFIN2
14
38
RFGND
13
39
UOSCB1
12
40
UOSCE1
11
IFOUT1
2
3
4
5
6
7
8
30
30
20
20
1n
IF
12p
12p
12p
12p
0.5p (UK)
5V
1T363 220p
8p
56p
0.5p (UK)
3k
L1
1T363 100p
L2
10k
3k
1n 1n
1T363
∗1: 14MHz, sine wave, 300mVp-p input (Hewlett-Packard Japan, Ltd.: 8644A)
8p
4p
56p
10k
3.3k
0.5p
(UK)
3.3k
– 12 –
2.5p
0.5p
(UK)
L3
10µ
6T
6T
10
9
1n
1.3k 39p
39p
GND
16
10k
IF
1n
35
180
4T
VLIN1
MIXOUT1
18
1n
4T
BS1
33
2
180
BS2
32
Vcc
19
For IF balanced output
1n
21
22
UIN2
20
1
UHF
4T
31
µ-com
1
1n
UOSCE2
XO
1n
UOSCB2
10n
23
VHOSC1
XI
24
25
VHOSC2
VT
1n
VLOSC1
CP
100n 20 200 100p
∗1
51
REF CLOCK
26
1n
VLOSC2
30V
27
IFGND
PLLVcc
47n 5.1k
30k
28
IFVcc
5V
1n
29
IFOUT2
10µ
BS3
NC
BS4
100k 100k 100k 100k 1n
UIN1
L3
VHIN2
3.2φ
3.2φ
VHF Low
7.5T
1.5T
VHIN1
0.5
0.5
VHF High
Wire diameter Number of windings Winding diameter
L1
L2
1T363
CXA3275Q
Description of Operation
The CXA3275Q is a tuner IC which frequency converts 55 to 860MHz cable digital broadcasts to IF.
In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC
also integrates a PLL circuit for local oscillation frequency control onto a single chip.
The functions of the various circuits are described below.
1. Mixer circuit
This circuit outputs the frequency difference between the signal input to VLIN, VHIN or UIN and the local
oscillation signal.
There are three sets of mixer circuits for VHF Low Band, VHF High Band and UHF Band.
VHF Low and VHF High are common emitter type mixer input circuits, and UHF is a common base type
mixer input circuit.
2. Local oscillation circuit
A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and
inductance.
There are three sets of oscillation circuits for VHF Low Band, VHF High Band and UHF Band.
VHF Low and VHF High are 2-pin fully differential oscillation circuits and UHF is a 4-pin fully differential
oscillation circuit.
3. IF amplifier circuit
This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage.
IF output is low impedance (emitter follower output), and can be selected from balanced and unbalanced
output.
When unbalanced output is selected, the output stage current can be saved by connecting the pin not used
for output to IFVCC.
4. PLL circuit
This PLL circuit controls the local oscillation frequency.
It consists of a programmable divider, phase comparator, charge pump and reference oscillator.
The control format supports the 3-wire bus format.
5. Band switch circuit
The MT58A has four sets of built-in PNP transistors which can be controlled by the bus data.
These outputs switch the on-chip mixer and oscillator circuits, and the relationship with the control data is
as shown in the table below.
Relationship between the Band Switch Data and Mixer/Oscillator Operation
Band switch data
Mixer circuit
VHF Low VHF High
Oscillation circuit
BS1
BS2
BS3
BS4
∗
1
0
∗
O
X
X
O
X
X
∗
0
1
∗
X
O
X
X
O
X
∗
0
0
∗
X
X
O
X
X
O
∗: Don't care
O: Operating
X: Not operating
– 13 –
UHF
VHF Low VHF High
UHF
CXA3275Q
Description of PLL Block
The CXA3275Q supports the 3-wire bus control format.
Serial data is transferred using the DA pin (DATA), CL pin (CLOCK) and CE pin (ENABLE) inputs. Data is
loaded to the shift register at the falling edge of the clock signal, and is latched at the falling edge of the enable
signal.
The clocks during the enable period are counted, and 28 bits of data as counted from the rising edge of the
enable signal are loaded as valid data.
The MT58A has the power-on reset function and the register data become all "0" after the power is turned on.
The threshold value of the power-on reset is approximately 3.0V.
The VCO lock frequency is obtained according to the following formula.
fosc = fref × (16M + S) fosc: Local oscillator frequency
fref: Phase comparison frequency
M: Main divider frequency division ratio S: Swallow counter frequency division ratio
The variable frequency division ranges of M and S are as follows, and are set as binary.
S < M ≤ 8191
0 ≤ S ≤ 15
The control format is as shown below.
Serial data (total 28 bits): Band data (4 bits) + various settings (3 bits)
+ reference frequency data (4 bits) + frequency data (17 bits)
Invalid data
DATA
Band switch data
BS4
1
BS3
BS2
Various data
BS1
0
4
5
CD
CP
R2
R1
Frequency data
R0
R3
M12 M11
11
12
S2
Invalid data
S1
S0
28
CLOCK
ENABLE
Time
M0 to:
S0 to:
CD:
CP:
BS1 to BS4:
R0 to R3:
Latch
Main divider frequency division ratio setting
Swallow counter frequency division ratio setting
Charge pump OFF and varicap output OFF (when "1")
Charge pump current switching (See the Charge Pump Current Table.)
Band switch control (Output PNP transistor ON when "1". See the Band Switch Output Table.)
Reference divider frequency division ratio setting. (See the Reference Divider Frequency
Division Ratio Table.)
– 14 –
CXA3275Q
Charge Pump Current Table
Charge pump current
CP
300µA
0
900µA
1
Reference Divider Frequency Division Ratio Table
R3
R2
R1
R0
Frequency division ratio
0
0
0
0
2
0
0
0
1
4
0
0
1
0
8
0
0
1
1
16
0
1
0
0
32
0
1
0
1
64
0
1
1
0
128
0
1
1
1
256
1
0
0
0
512
1
0
0
1
6
1
0
1
0
12
1
0
1
1
24
1
1
0
0
48
1
1
0
1
96
1
1
1
0
192
1
1
1
1
384
Band Switch Output Table
Band switch data
Band switch pins
BS1
BS2
BS3
BS4
BS1
BS2
BS3
BS4
Operating mode
(MIX/OSC)
1
0
0
0
ON
OFF
OFF
OFF
UHF
0
1
0
0
OFF
ON
OFF
OFF
VL
0
0
1
0
OFF
OFF
ON
OFF
VH
0
0
0
1
OFF
OFF
OFF
ON
UHF
<Supplement>
• Operation for Power On
When the data transfer is not performed after the power on, both the mixer and oscillator blocks operate in
UHF as the register data are all "0" by the power-on reset.
At this time, the Pin 33 (VT) voltage becomes the value equal to the varicap diode supply voltage (30V) when
the external clock is input to Pin 34 (XI) or when the crystal is connected to this pin for self-oscillation. When
the external clock is not input simultaneously with the power-on or the crystal is not connected, the Pin 33
voltage becomes unstable.
– 15 –
CXA3275Q
3-wire Bus Timing Chart
tSD
DATA
3V
1.5V
3V
1.5V
CLOCK
ENABLE
tHD
3V
1.5V
tWE
tSE
tSD: Data setup time
tHD: Data hold time
tSE: Enable setup time
tHE
tHE: Enable hold time
tWE: Enable waiting time
– 16 –
CXA3275Q
Characteristics Graphs
Circuit current vs. Supply voltage
(Unbalanced output)
Circuit current vs. Supply voltage
(Balanced output)
150
170
140
160
UHF
120
VHF
110
100
90
80
70
60
140
VHF
130
120
110
100
90
80
50
4.4
4.6
4.8
5.0
5.2
5.4
5.6
Supply voltage [V]
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
BS1
BS2
BS3
BS4
4.7
4.6
4.5
0
2
4
6
8
10
12
70
4.4
4.6
4.8
5.0
5.2
Supply voltage [V]
Band SW output voltage vs. Output current
Output voltage [V]
UHF
150
Circuit current [mA]
Circuit current [mA]
130
14
16
Output current [mA]
– 17 –
5.4
5.6
CXA3275Q
Conversion gain vs. Reception frequency
(Untuned input)
Noise figure vs. Reception frequency
(Untuned input, in DSB)
35
30
30
UHF
25
VL
NF – Noise figure [dB]
CG – Conversion gain [dB]
35
VH
20
15
10
fIF = 39MHz
5
fIF = 39MHz
25
20
VL
15
UHF
10
5
0
0
0
100 200 300 400 500 600 700 800 900
0
100 200 300 400 500 600 700 800 900
Reception frequency [MHz]
Reception frequency [MHz]
1% adjacent cross modulation vs. Reception frequency
(Untuned input)
CM – 1% adjacent cross modulation [dBµ]
1% adjacent cross modulation vs. Reception frequency
(Untuned input)
CM – 1% adjacent cross modulation [dBµ]
VH
120
100
VL
VH
UHF
80
60
fIF = 39MHz
(100kHz 80% AM)
40
fD – 6MHz
fD + 6MHz
20
0
0
100 200 300 400 500 600 700 800 900
120
VL
100
UHF
80
60
fIF = 39MHz
(100kHz 40% AM)
40
fD – 12MHz
fD + 12MHz
20
0
0
Reception frequency [MHz]
VH
100 200 300 400 500 600 700 800 900
Reception frequency [MHz]
– 18 –
CXA3275Q
120
110
100
Oscillation frequency supply voltage fluctuation
(PLL off)
600
400
VL
UHF
VH
90
80
70
60
50
40
30
20
10
0
fIF = 39MHz
1kHz offset
10kHz offset
100kHz offset
UHF
0
–200
–400
Supply voltage = 5V
–600
VCC – 10%
VCC + 10%
–800
0
100 200 300 400 500 600 700 800 900
0
Reception frequency [MHz]
20
10
0
–10
fIF = 39MHz
–20
fRF = 50MHz (VL)
fRF = 440MHz (VH)
fRF = 850MHz (UHF)
–30
–40
–50
–60
–50
–40
–30
–20
–10
0
200
400
600
800
Reception frequency [MHz]
Input/output characteristics (Untuned input)
Output level [dBm]
VH
VL
200
+B drift [kHz]
OSC phase noise [dBc/Hz]
OSC phase noise vs. Reception frequency
(Untuned input)
10
20
Input level [dBm] (SG setting value)
– 19 –
1000
CXA3275Q
VHF Low Input Impedance
j50
j100
j25
0
50
55M
150M
24
25
1n
S11
–j25
–j100
–j50
VHF High Input Impedance
j50
j100
j25
0
50
150M
22
23
1n
450M
–j25
–j100
–j50
– 20 –
S11
CXA3275Q
UHF Input Impedance
j50
j25
800
700
600
j100
900
500
400
0
50
20
21
1n
S11
–j25
–j100
–j50
IF Output Impedance
j50
j100
j25
50M 40M
20M
0
30M
50
1
2
1n
S11
–j25
–j100
–j50
– 21 –
3
5V
CXA3275Q
Package Outline
Unit: mm
40PIN QFP (PLASTIC)
+ 0.35
1.5 – 0.15
+ 0.1
0.127 – 0.05
9.0 ± 0.4
+ 0.4
7.0 – 0.1
0.1
21
30
20
31
A
11
40
1
+ 0.15
0.3 – 0.1
0.65
10
0.24
M
0° to 10°
0.5 ± 0.2
(8.0)
+ 0.15
0.1 – 0.1
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-40P-L01
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
EIAJ CODE
QFP040-P-0707
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 22 –
Sony Corporation
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