TOSHIBA TB6560FG

TB6560HQ/FG
Preliminary
TOSHIBA BiCD Integrated Circuit
Silicon Monolithic
TB6560HQ,TB6560FG
PWM Chopper-Type bipolar
Stepping Motor Driver IC
The TB6560HQ/FG is a PWM chopper-type sinusoidal micro-step
bipolar stepping motor driver IC.
It supports both 2-phase/1-2-phase/W1-2-phase/2W1-2-phase
excitation mode and forward/reverse mode and is capable of
low-vibration, high-performance drive of 2-phase bipolar type
stepping motors using only a clock signal.
Features
TB6560HQ
TB6560FG
•
Single-chip bipolar sinusoidal micro-step stepping motor
driver
•
Uses high withstand voltage BiCD process:
Ron (upper  lower) = 0.6 Ω (typ.)
•
Forward and reverse rotation control available
•
Selectable phase drive (2, 1-2, W1-2, and 2W1-2)
•
High output withstand voltage: VCEO = 40 V
•
High output current: IOUT = HQ: 3.5 A (peak)
FG: 2.5 A (peak)
•
Packages: HZIP25-P-1.27/HQFP64-P-1010-0.50
•
Built-in input pull-down resistor: 100 kΩ (typ.)
•
Output monitor pin equipped: MO current (IMO (max) = 1 mA)
•
Equipped with reset and enable pins
•
Built-in overheat protection circuit
Weight:
HZIP25-P-1.27: 9.86 g (typ.)
HQFP64-P-1010-0.50: 0.26 g (typ.)
The TB6560HQ/FG is a Pb-free product.
The following conditions apply to solderability:
*Solderability
1. Use of Sn-63Pb solder bath
*solder bath temperature = 230°C
*dipping time = 5 seconds
*number of times = once
*use of R-type flux
2. Use of Sn-3.0Ag-0.5Cu solder bath
*solder bath temperature = 245°C
*dipping time = 5 seconds
*the number of times = once
*use of R-type flux
*: Since this product has a MOS structure, it is sensitive to electrostatic discharge. These ICs are highly sensitive to
electrostatic discharge. When handling them, please be careful of electrostatic discharge, temperature and
humidity conditions.
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TB6560HQ/FG
Block Diagram
VDD
Protect
20/30, 31
19/28
MO
VMA
17/23
18/25, 26
OUT_AP
Decoder
M1 23/36
16/19, 20
Bridge
driver A
M2 22/35
13/10, 11
CLK
OUT_AM
Overheat protection
circuit
CW/CCW 21/33
14/13, 14, 15
3/45
NFA
Input
circuit
RESET 5/48
ENABLE
Current selector
circuit A
+
8/55, 56 VMB
4/47
OUT_BP
DCY1 25/39
12/6, 7
Bridge
driver B B
Decoder
DCY2 24/38
9/61, 62
OSC
7/53
OUT_BM
OSC
Current selector
circuit B
+
11/2, 3, 4
NFB
Maximum current
setting circuit
2/43
1/42
TQ1
TQ2
6/50, 51
SGND
15/16
10/1
PGNDA PGNDB
TB6560HQ/TB6560FG
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TB6560HQ/FG
Pin Functions
Pin No.
I/O
Symbol
42
Input
TQ2
Torque setting input (current setting) (built-in pull-down resistor)
43
Input
TQ1
Torque setting input (current setting) (built-in pull-down resistor)
HQ
FG
1
2
Functional Description
3
45
Input
CLK
4
47
Input
ENABLE
H: Enable; L: All output OFF (built-in pull-down resistor)
Step transition, clock input (built-in pull-down resistor)
5
48
Input
RESET
L: Reset (output is reset to its initial state) (built-in pull-down resistor)
6
50/51
⎯
SGND
Signal ground (control side)
(Note 1)
7
53
⎯
OSC
Connects to and oscillates CR. Output chopping.
8
55/56
Input
VMB
Motor side power pin (B phase side)
(Note 1)
(Note 1)
9
61/62
Output
OUT_BM
OUT_B output
10
1
⎯
PGNDB
Power ground
11
2/3/4
⎯
NFB
B channel output current detection pin (resistor connection).
Short the two pins for FG.
(Note 1)
12
6/7
Output
OUT_BP
OUT_B output
(Note 1)
13
10/11
Output
OUT_AM
OUT_A output
(Note 1)
14
13/14/15
⎯
NFA
A channel output current detection pin (resistor connection).
Short the two pins for FG.
(Note 1)
15
16
⎯
PGNDA
Power ground
16
19/20
Output
OUT_AP
OUT_A output
17
23
Output
MO
Initial state detection output. ON when in initial state (open drain).
18
25/26
Input
VMA
Motor side power pin (A phase side)
19
28
Output
Protect
20
30/31
Input
VDD
21
33
Input
CW/CCW
22
35
Input
M2
Excitation mode setting input (built-in pull-down resistor)
23
36
Input
M1
Excitation mode setting input (built-in pull-down resistor)
24
38
Input
DCY2
Current Decay mode setting input (built-in pull-down resistor)
25
39
Input
DCY1
Current Decay mode setting input (built-in pull-down resistor)
(Note 1)
(Note 1)
When TSD, ON (open drain). Normal Z.
Control side power pin.
(Note 1)
Forward/Reverse toggle pin. L: Forward; H: Reverse
(built-in pull-down resistor)
HQ: No Non-connection (NC)
FG: Other than the above pins, all are NC
(Since NC pins are not connected to the internal circuit, a potential can be applied to those pins.)
All control input pins: Pull-down resistor 100 kΩ (typ.)
Note 1: If the FG pin number column indicates more than one pin, the indicated pins should be tied to each other at
a position as close to the pins as possible.
(The electrical characteristics of the relevant pins in this document refer to those when they are handled in
that way.)
<Terminal circuits>
Input pins
(M1, M2, CLK, CW/CCW,
ENABLE and RESET)
Output ins
(MO, PROTECT)
VDD
100 Ω
100 kΩ
100 Ω
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TB6560HQ/FG
Absolute Maximum Ratings (Ta = 25°C)
Characteristic
Power supply voltage
Output current
Peak
HQ
FG
MO drain current
Input voltage
Symbol
Rating
VDD
6
VMA/B
40
V
3.5
IO (PEAK)
A/phase
2.5
I (MO)
1
mA
VIN
5.5
V
5 (Note 1)
HQ
Power dissipation
Unit
43 (Note 2)
PD
W
1.7 (Note 3)
FG
4.2 (Note 4)
Operating temperature
Topr
−30 to 85
°C
Storage temperature
Tstg
−55 to 150
°C
Note 1: Ta = 25°C, No heat sink.
Note 2: Ta = 25°C, with infinite heat sink (HZIP25).
Note 3: Ta = 25°C, with soldered leads.
Note 4: Ta = 25°C, when mounted on the board (4-layer board).
Susceptible to the board layout and the mounting conditions.
Operating Range (Ta = −20 to 85°C)
Characteristic
Symbol
Min
Typ.
Max
Unit
⎯
4.5
5.0
5.5
V
4.5
⎯
26.4
V
VDD
Power supply voltage
Output current
Test Condition
VMA/B
HQ
FG
VMA/B >
= VDD
⎯
IOUT
⎯
⎯
3
⎯
⎯
1.5
A
Input voltage
VIN
⎯
0
⎯
5.5
V
Clock frequency
fCLK
⎯
⎯
⎯
15
kHz
OSC frequency
fOSC
⎯
⎯
⎯
600
kHz
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TB6560HQ/FG
Electrical Characteristics (Ta = 25°C, VDD = 5 V, VM = 24 V)
Characteristic
Input voltage
High
Low
Input hysteresis voltage
Input current
Consumption current VDD pin
Consumption current VM pin
Output channel margin of error
Test
Circuit
Min
Typ.
Max
2.0
⎯
VDD
−0.2
⎯
0.8
⎯
400
⎯
M1, M2, CW/CCW, CLK, RESET ,
ENABLE, DECAY, TQ1, TQ2, ISD
VIN = 5.0 V
Built-in pull-down resistor
30
55
80
IIN (L)
VIN = 0 V
⎯
⎯
1
IDD1
Output open,
RESET : H, ENABLE: H
(2, 1-2 phase excitation)
⎯
3
5
Output open,
RESET : H, ENABLE: H
(W1−2, 2W1-2 phase excitation)
⎯
3
5
IDD3
RESET : L, ENABLE: L
⎯
2
5
IDD4
RESET : H, ENABLE: L
⎯
2
5
RESET : H/L, ENABLE: L
⎯
0.5
1
RESET : H/L, ENABLE: H
⎯
0.7
2
B/A, COSC = 0.0033 µF
−5
⎯
5
TQ1 = H, TQ2 = H
10
20
30
TQ1 = L, TQ2 = H
47
50
55
TQ1 = H, TQ2 = L
70
75
80
Symbol
VIN (H)
VIN (L)
VH
IIN (H)
IDD2
IM1
IM2
∆VO
1
VNFHL
VNFLH
M1, M2, CW/CCW, CLK, RESET ,
ENABLE, DECAY, TQ1, TQ2, ISD
1
1
1
1
⎯
VNFHH
VNF level
Level differential
Test Condition
⎯
TQ1 = L, TQ2 = L
VNFLL
Unit
V
mV
µA
mA
mA
%
%
100
Minimum clock pulse width
tW (CLK)
⎯
⎯
⎯
100
⎯
ns
MO output residual voltage
VOL MO
⎯
IOL = 1 mA
⎯
⎯
0.5
V
TSD
⎯
(Design target value)
⎯
170
⎯
°C
TSDhys
⎯
(Design target value)
⎯
20
⎯
°C
C = 330 pF
60
130
200
kHz
TSD
TSD hysteresis
Oscillating frequency
fOSC
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TB6560HQ/FG
Electrical Characteristics (Ta = 25°C, VDD = 5 V, VM = 24 V)
Output Block
Characteristic
Symbol
Ron U1H
HQ
Ron L1H
Output ON resistor
Ron U1F
FG
A-B chopping current (Note)
Test
Circuit
Test Condition
Min
Typ.
Max
⎯
0.3
0.4
⎯
0.3
0.4
⎯
0.35
0.5
⎯
0.35
0.5
θ=0
⎯
100
⎯
IOUT = 1.5 A
4
IOUT = 1.5 A
Ron L1F
2W1-2phase
excitation
W1-2phase
excitation
1-2phase
excitation
2W1-2phase
excitation
⎯
⎯
θ = 1/8
93
98
100
2W1-2phase
excitation
W1-2phase
excitation
⎯
θ = 2/8
87
92
97
2W1-2phase
excitation
⎯
⎯
θ = 3/8
78
83
88
2W1-2phase
excitation
W1-2phase
excitation
1-2phase
excitation
66
71
76
2W1-2phase
excitation
⎯
⎯
θ = 5/8
51
56
61
2W1-2phase
excitation
W1-2phase
excitation
⎯
θ = 6/8
33
38
43
2W1-2phase
excitation
⎯
⎯
θ = 7/8
15
20
25
⎯
⎯
100
⎯
450
500
550
RL = 2 Ω, VNF = 0 V,
CL = 15 pF
⎯
0.1
⎯
⎯
0.1
⎯
RESET to output
⎯
0.1
⎯
⎯
0.3
⎯
⎯
0.2
⎯
⎯
―
1
⎯
―
1
Vector
⎯
θ = 4/8
2-phase excitation
Reference voltage
VNF
Output transistor switching
characteristics
tr
tf
tpLH
Delay time
⎯
7
tpLH
Upper side
ILH
Lower side
ILL
TQ1, TQ2 = L (100%)
OSC = 100 kHz
ENABLE to output
tpHL
Output leakage current
TQ1 = L, TQ2 = L
6
VM = 40 V
Unit
Ω
%
mV
µs
µA
Note: Maximum current (θ = 0): 100%
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TB6560HQ/FG
Description of Functions
1. Excitation Settings
You can use the M1 and M2 pin settings to configure four different excitation settings. (The default is
2-phase excitation using the internal pull-down.)
Input
M2
M1
Mode
(Excitation)
L
L
2-phase
L
H
1-2-phase
H
L
W1-2-phase
H
H
2W1-2-phase
2. Function
When the ENABLE signal goes Low level, it sets an OFF on the output. The output changes to the Initial
mode shown in the table below when the RESET signal goes Low level. In this mode, the status of the
CLK and CW/CCW pins are irrelevant.
Input
Output Mode
CW/CCW
RESET
ENABLE
L
H
H
CW
H
H
H
CCW
X
X
L
H
Initial mode
X
X
X
L
Z
CLK
X: Don’t care
3. Initial Mode
When RESET is used, the phase currents are as follows. In this instance, the MO pin is L (connected to
open drain).
Excitation Mode
A Phase Current
B Phase Current
2-phase
100%
−100%
1-2-phase
100%
0%
W1-2-phase
100%
0%
2W1-2-phase
100%
0%
4. Current Decay Settings
Output is generated by four PWM blasts; 25% decay is created by inducing decay during the last blast in
Fast mode; 50% decay is created by inducing decay during the last two blasts in Fast mode; and 100%
decay is created by inducing all four blasts in Fast mode.
If there is no input with the pull-down resistor connection then the setting is Normal.
Dcy2
Dcy1
Current Decay Setting
L
L
Normal 0%
L
H
25% Decay
H
L
50% Decay
H
H
100% Decay
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TB6560HQ/FG
5. Torque Settings (Current Value)
The current ratio used in actual operations is determined in regard to the current setting due to resistance.
Configure this for extremely low torque scenarios such as when Weak Excitation mode is stopped.
If there is no input with the pull-down resistor connection then the setting is 100% torque.
TQ2
TQ1
Current Ratio
L
L
100%
L
H
75%
H
L
50%
H
H
20%
(weak excitation)
6. Protect and MO (Output Pins)
You can configure settings from the receiving side by using an open-drain connection for the output pins
and making the pull-up voltage variable.
When a given pin is in its designated state it will go ON and output at Low level.
Pin State
Protect
MO
Low
Overheat protection operation
Initial state
Z
Normal operation
Other than initial state
Open-drain connection
7. OSC
Output chopping waves are generated by connecting the condenser and having the CR oscillate.
The values are as shown below (roughly: ± 30% margin of error).
Condenser
Oscillating Frequency
1000 pF
44 kHz
330 pF
130 kHz
100 pF
400 kHz
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TB6560HQ/FG
Relationship between Enable, RESET and Output (OUT and MO)
Ex-1: ENABLE 1-2-Phase Excitation (M1: H, M2: L)
CW
CLK
ENABLE
RESET
MO
(%)
100
71
IA
0
−71
−100
t0
t1
t2
t3
OFF
t7
t8
t9
t10
t11
t12
The ENABLE signal at Low level disables only the output signals. Internal logic functions proceed in
accordance with input clock signals and without regard to the ENABLE signal. Therefore output current is
initiated by the timing of the internal logic circuit after release of disable mode.
Ex-2: RESET 1-2-Phase Excitation (M1: H, M2: L)
CW
CLK
ENABLE
RESET
MO
(%)
100
71
IA
0
−71
−100
t0
t1
t2
t3
t2
t3
t4
t5
t6
t7
t8
When the RESET signal goes Low level, output goes Initial state and the MO output goes Low level (Initial
state: A Channel output current is 100%).
Once the RESET signal returns to High level, output continues from the next state after Initial from the
next raise in the Clock signal.
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TB6560HQ/FG
2-Phase Excitation (M1: L, M2: L, CW Mode)
CW
CLK
MO
(%)
100
IA
0
−100
(%)
100
IB
0
−100
t0
t1
t2
t3
t4
t5
t6
t7
1-2-Phase Excitation (M1: H, M2: L, CW Mode)
CW
CLK
MO
(%)
100
71
IA
0
−71
−100
(%)
100
71
IB
0
−71
−100
t0
t1
t2
t3
t4
t5
t6
10
t7
t8
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TB6560HQ/FG
W1-2-Phase Excitation (M1: L, M2: H, CW Mode)
CW
CLK
MO
(%)
100
92
71
38
IA
0
−38
−71
−92
−100
(%)
100
92
71
38
IB
0
−38
−71
−92
−100
t0
t1
t2
t3
t4
t5
t6
t7
11
t8
t9
t10
t11
t12
t13
t14
t15
t16
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TB6560HQ/FG
2W1-2-Phase Excitation (M1: H, M2: H, CW Mode)
CW
CLK
MO
(%)
100
98
92
83
71
56
38
20
IA
0
−20
−38
−56
−71
−83
−92
−98
−100
(%)
100
98
92
83
71
56
38
20
IB
0
−20
−38
−56
−71
−83
−92
−98
−100
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32
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TB6560HQ/FG
<Input Signal Example>
CK
MO
M1
M2
RESET
(%)
100
91
71.4
40
IA
0
−40
−71.4
−91
−100
1-2-phase excitation
W1-2-phase excitation
It is recommended that M1 and M2 signals be changed after setting the RESET signal Low during the Initial
state (MO is Low). Even when the MO is Low, changing the RESET signal without setting the RESET signal
Low may cause the discontinuity in the current waveform.
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TB6560HQ/FG
1. Current Waveform and Settings of Mixed Decay Mode
You can configure the points of the current’s shaped width (current’s pulsating flow) using 1-bit input in
Decay mode for constant-current control.
“NF” refers to the point at which the output current reaches its setting current value and “RNF” refers to
the monitoring timing of the setting current.
The smaller the MDT value, the smaller the current ripple (current wave peak), and the current’s decay
capability will fall.
fchop
OSC Pin
Internal
Waveform
Setting Current Value
Normal
Mode
NF
RNF
Charge mode → NF: Setting current value reached → Slow mode
→ Current monitoring → (When setting current value > Output
current) Charge mode
Setting Current Value
25%
Decay
Mode
NF
MDT
RNF
Charge mode → NF: Setting current value reached → Slow
mode → Mixed decay timing → Fast mode → Current monitoring
→ (When setting current value > Output current) Charge mode
Setting Current Value
50%
Decay
Mode
NF
MDT
Charge mode → NF: Setting current value reached → Slow
mode → Mixed decay timing → Fast mode → Current monitoring
→ (When setting current value > Output current) Charge mode
RNF
Setting Current Value
100%
Decay
Mode
NF
Charge mode → NF: Setting current value reached → Fast mode
→ Current monitoring → (When setting current value > Output
current) Charge mode
RNF
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TB6560HQ/FG
2. Current Control Modes (Decay Mode effect)
•
Direction in which current value increases (sine wave)
Slow
Setting
Current
Value
Slow
Slow
Setting
Current
Value
•
Charge
Fast
Charge
Slow
Fast
Fast
Charge
Fast
Direction in which sine wave decreases
(when a high decay ratio (MDT%) is used in Mixed Decay mode)
Slow
Setting
Current
Value
Slow
Since the current’s rate of decay is fast, its compliance
with the setting current value is also fast.
Charge
Charge
Fast
Fast
Slow
Slow
Setting
Current
Value
Fast
•
Charge
Charge
Fast
Direction in which sine wave decreases
(when a low decay ratio (MDT%) is used in Mixed Decay mode)
Since the current’s rate of decay is slow, its
compliance with the setting current value takes a
long time (or may not follow at all).
Slow
Setting
Current
Value
Slow
Fast
Charge
Charge
Fast
Slow
Fast
Setting
Current
Value
Slow
Fast
During Mixed Decay mode and Fast Decay mode, if the setting current value < output current at RNF:
current monitoring point, the Charge mode at the next chopping cycle will disappear and the pattern will
change to Slow  Fast Mode (Slow → Fast occurs at MDT). (In reality, a charge is applied momentarily to
confirm the current.)
Note: These figures are intended for illustrative purposes only. If designed more realistically, they would show
transient response curves.
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TB6560HQ/FG
3. Mixed Decay Mode Waveform (Current Waveform)
fchop
fchop
OSC Pin
Internal
Waveform
IOUT
Setting Current
Value
Setting
Current
Value
25%
Mixed
Decay
Mode
NF
NF
RNF
MDT (Mixed Decay Timing) Points
•
When the NF points come after mixed decay timing
Switches to Fast mode after Charge mode
fchop
fchop
IOUT
Setting current value
NF
MDT (Mixed Decay Timing) Points
Setting
Current
Value
RNF
NF
25%
Mixed
Decay
Mode
RNF
CLK Signal Input
•
When the output current value > Setting current value in mixed decay mode
fchop
Setting
Current
Value
fchop
fchop
NF
IOUT
RNF
NF
Setting Current
Value
25%
MIXED
DECAY
MODE
RNF
MDT (Mixed Decay Timing) Points
CLK Signal Input
*: Even if the output current rises above the setting current at the RNF point, a charge is applied momentarily to
confirm the current.
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TB6560HQ/FG
4. Fast Decay Mode Waveform
After the current value set by RNF, torque or other means is attained, the output current to load will
make the transition to full regenerative mode.
fchop
Setting
Current
Value
IOUT
Transition to Charge mode for a brief moment
Fast
Decay
Mode
(100%
Decay
Mode)
RNF
Setting
Current
Value
NF
RNF
Since the setting current value > output
current, charge mode → NF → Fast Decay
mode transition will take place at even the
next cycle.
RNF
CLK Signal Input
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TB6560HQ/FG
5. CLK Signal and Internal CR CK Output Current Waveform
(when the CLK signal is input in the middle of Slow mode)
25% Mixed Decay Mode
fchop
fchop
fchop
OSC Pin
Internal
Waveform
Setting
Current
Value
IOUT
NF
MDT
NF
Setting
Current
Value
RNF
MDT
RNF
Transition to Charge mode for a brief moment
CLK Signal Input
The CR counter is reset here.
When the CLK signal is input, the Chopping Counter (OSC Counter) is forcibly reset at the timing of the
OSC.
As a result, the response to input data is fast in comparison to methods that don’t reset the counter.
The delay time is one OSC cycle: 10 µs @100 kHz Chopping using the Logic Block logic value.
After the OSC Counter is reset by CLK signal input, the transition is invariably made to Charge mode
for a brief moment to compare the current.
Note: Even in Fast Decay Mode, the transition is invariably made to Charge mode for a brief moment to
compare the current.
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TB6560HQ/FG
6. CLK Signal and Internal OSC Output Current Waveform
(when the CLK signal is input in the middle of Charge mode)
25% Mixed Decay Mode
fchop
fchop
fchop
OSC Pin
Internal
Waveform
Setting
Current
Value
MDT
NF
IOUT
Setting
Current
Value
MDT
RNF
RNF
Transition to Charge mode for a brief moment
CLK Signal Input
The OSC Counter is reset here.
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7. CLK Signal AND Internal OSC Output Current Waveform
(when the CLK signal is input in the middle of Fast mode)
25% Mixed Decay Mode
fchop
fchop
fchop
OSC Pin
Internal
Waveform
Setting
Current
Value
IOUT
NF
MDT
Setting
Current
Value
NF
MDT
RNF
RNF
Transition to Charge mode for a brief moment
CLK Signal Input
The OSC Counter is reset here.
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8. Internal OSC Output Current Waveform when Setting Current is Reverse
(when the CLK signal is input using 2-phase excitation)
25% Mixed Decay Mode
fchop
fchop
fchop
Setting
Current
Value
IOUT
0
RNF
RNF
Setting
Current
Value
NF
MDT
NF
CLK Signal Input
The OSC Counter is reset here.
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Current Draw-out Path when ENABLE is Input in Mid Operation
When all the output transistors are forced OFF during Slow mode, the coil energy is drawn out in the
following modes:
Note: Parasitic diodes are indicated on the designed lines. However, these are not normally used in Mixed
Decay mode.
VM
VM
U1
ON
Note
U2
U1
OFF
OFF
VM
Note
Load
ON
ON
L1
L2
L1
RNF
Charge Mode
OFF
OFF
L2
ON
RNF
PGND
U1
ENABLE is input
Load
OFF
U2
U2
OFF
Note
Load
L1
L2
OFF
OFF
RNF
PGND
Slow Mode
PGND
Force OFF Mode
As shown in the figure above, an output transistor has parasitic diodes.
Normally, when the energy of the coil is drawn out, each transistor is turned ON and the power flows in the
opposite-to-normal direction; as a result, the parasitic diode is not used. However, when all the output
transistors are forced OFF, the coil energy is drawn out via the parasitic diode.
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Output Stage Transistor Operation Mode
VM
VM
U1
U2
U1
OFF
OFF
OFF
ON
ON
L1
L2
L1
ON
Note
VM
Note
Load
U2
U1
OFF
OFF
L2
ON
L1
L2
ON
RNF
OFF
RNF
PGND
PGND
Charge Mode
ON
Note
Load
Load
RNF
U2
PGND
Slow Mode
Fast Mode
Output Stage Transistor Operation Functions
CLK
U1
U2
L1
L2
CHARGE
ON
OFF
OFF
ON
SLOW
OFF
OFF
ON
ON
FAST
OFF
ON
ON
OFF
Note: The above chart shows an example of when the current flows as indicated by the arrows in the above figures.
If the current flows in the opposite direction, refer to the following chart:
CLK
U1
U2
L1
L2
CHARGE
OFF
ON
ON
OFF
SLOW
OFF
OFF
ON
ON
FAST
ON
OFF
OFF
ON
Upon transitions of above-mentioned functions, a dead time of about 300 ns is inserted respectively.
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Measurement Waveform
CLK
tCLK
tCLK
tpLH
VM
90%
tpHL
50%
GND
90%
50%
10%
10%
tr
tf
Figure 1 Timing Waveforms and Names
OSC-Charge DELAY:
The conversion from the OSC waveform to the internal OSC waveform is done by recognizing the level of
chopping wave. The voltages of 2 V or above are considered as a High level, and voltages of 0.5 V or below are
considered as a Low level as designed values. However, there is a response delay and that there occurs the
peak-to-peak voltage variation.
2V
OSC
Waveform
0.5 V
OSC Pin
Internal
Waveform
Figure 2 Timing Waveforms and Names (CR and Output)
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Power Dissipation
TB6560HQ
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1. How to Turn on the Power
Turn on VDD. When the voltage has stabilized, turn on VMA/B.
In addition, set the Control Input pins to Low when inputting the power.
(All the Control Input pins are pulled down internally.)
Once the power is on, the CLK signal is received and excitation advances when RESET goes high and
excitation is output when ENABLE goes high. If only RESET goes high, excitation won't be output and
only the internal counter will advance. Likewise, if only ENABLE goes high, excitation won't advance even
if the CLK signal is input and it will remain in the initial state.
The following is an example:
<Recommended Control Input Sequence>
CLK
RESET
H
L
ENABLE
H
L
OUT
H
L
Z
Output
Internal current Setting
Output current setting
Z
Internal current setting: Invariable
Output OFF
Internal current setting: Variable
2. Calculating the Setting Current
To perform constant-current operations, it is necessary to configure the base current using an external
resistor. If the voltage on the NFA (B) pin is 0.5 V (with a torque of 100%) or greater, it will not charge.
Ex.: If the maximum current value is 1 A, the external resistance will be 0.5 W.
3. PWM Oscillator Frequency (External Condenser Setting)
An external condenser connected to the OSC pin is used to internally generate a saw tooth waveform. PWM
is controlled using this frequency. Toshiba recommends 100 to 3300 pF for the capacitance, taking
variations between ICs into consideration.
Approximation: fosc = 1/(Cosc × 1.5 × (10/Cosc + 1)/66) × 1000 kHz
4. Power Dissipation
The IC power dissipation is determined by the following equation:
P = VDD × IDD + IOUT × Ron × 2 drivers
The higher the ambient temperature, the smaller the power dissipation.
Check the PD-Ta curve, and be sure to design the heat dissipation with a sufficient margin.
5. Heat Sink Fin Processing
The IC fin (rear) is electrically connected to the rear of the chip. If current flows to the fin, the IC will
malfunction. If there is any possibility of a voltage being generated between the IC GND and the fin, either
ground the fin or insulate it.
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6. Thermal Protection
When the temperature reaches 170°C (as standard value), the thermal protection circuit is activated
switching the output to off. There is a variation of plus or minus about 20°C in the temperature that
triggers the circuit operation.
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5 V
10 µF
1 µF
47 µF
VDD
CLK
VMA
24 V
VMB
OUTAP
RESET
ENABLE
1 µF
H-SW A
OUTAM
Logic
M1
NFCompA
M2
OUTBP
M
H-SW B
MCU
or
External
input
CW/CCW
DCY1
OUTBM
Current
Control
NFA
NFCompB
DCY2
RNFA
TQ1
TQ2
NFB
Protect
RNFB
MO
R1
R2
OSC
100 pF ∼
− 400 kHz
SGND
PGND
0.5 Ω: IOUTmax = 1.0 A
3.3 V
or
5.0 V
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Package Dimensions
Weight: 9.86 g (typ.)
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Package Dimensions
Weight: 0.26 g (typ.)
Note: The rear heat sink block will be 5.5 mm × 5.5 mm. (PROVISIONAL)
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RESTRICTIONS ON PRODUCT USE
060116EBA
• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others. 021023_C
• The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E
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