Catalyst CAT24FC01LETE13REV-F 1-kb i2c serial eeprom Datasheet

H
CAT24FC01
EE
GEN FR
ALO
1-kb I2C Serial EEPROM
LE
A D F R E ETM
FEATURES
■ 1,000,000 program/erase cycles
■ 400 kHz (2.5 V) and 100 kHz (1.8 V) I2C bus
compatible
■ 100 year data retention
■ 1.8 to 5.5 volt operation
■ 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and MSOP
■ Low power CMOS technology
packages
■ 16-byte page write buffer
- “Green” package option available
■ Industrial and extended temperature ranges
■ 256 x 8 memory organization
■ Self-timed write cycle with auto-clear
■ Hardware write protect
DESCRIPTION
The CAT24FC01 is a 1-kb Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements.
The CAT24FC01 features a 16-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and
MSOP packages.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L)
A0
A1
A2
1
2
3
8
7
6
VSS
4
5
EXTERNAL LOAD
SOIC Package (J, W)
VCC
WP
SCL
SDA
A0
A1
A2
1
2
3
8
7
6
VCC
WP
SCL
VSS
4
5
SDA
VCC
VSS
TSSOP Package (U, Y)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
WP
SCL
SDA
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
WP
CONTROL
LOGIC
XDEC
COLUMN
DECODERS
E2PROM
MSOP Package (R, Z)
DATA IN STORAGE
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
HIGH VOLTAGE/
TIMING CONTROL
SCL
PIN FUNCTIONS
Pin Name
A0
A1
A2
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
1.8 V to 5.5 V Power Supply
VSS
Ground
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry
the I2C Bus Protocol.
1
Doc. No. 1073, Rev. D
CAT24FC01
Lead Soldering Temperature (10 seconds) ...... 300°C
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
Output Short Circuit Current(2) ....................... 100 mA
–55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
*COMMENT
Voltage on Any Pin with
Respect to Ground(1) ............ –2.0 V to VCC + 2.0 V
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
VCC with Respect to Ground ............. –2.0 V to +7.0 V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
NEND(3)
TDR
Typ
Max
Units
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
(3)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
4000
Volts
Latch-up
JEDEC Standard 17
100
mA
VZAP
ILTH(3)(4)
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC
Power Supply Current (Read)
ICC
Min
Typ
Max
Units
fSCL = 100 kHz
1
mA
Power Supply Current (Write)
fSCL = 100 kHz
3
mA
ISB(5)
Standby Current (VCC = 5.0 V)
VIN = GND or VCC
1
µA
ILI
Input Leakage Current
VIN = GND to VCC
1
µA
ILO
Output Leakage Current
VOUT = GND to VCC
1
µA
VIL
Input Low Voltage
–1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 1.0
V
VOL1
Output Low Voltage (VCC = 3.0 V)
IOL = 3 mA
0.4
V
VOL2
Output Low Voltage (VCC = 1.8 V)
IOL = 1.5 mA
0.5
V
Max
Units
CAPACITANCE TA = 25°C, f = 400 kHz, VCC = 5 V
Symbol
Test
Conditions
Min
Typ
CI/O(3)
Input/Output Capacitance (SDA)
VI/O = 0 V
8
pF
CIN(3)
Input Capacitance (other pins)
VIN = 0 V
6
pF
Note:
(1) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1.0 V to VCC + 1.0 V.
(5) Maximum standby current (ISB) = 10µA for the Extended Automotive temperature range.
Doc. No. 1073, Rev. D
2
CAT24FC01
A.C. CHARACTERISTICS
VCC = 1.8 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8 V - 5.5 V
2.5 V - 5.5 V
Min
Max
Min
Max
Units
0
100
0
400
kHz
FSCL
Clock Frequency
TI(1)
Noise Suppression Time
Constant at SCL, SDA Inputs
100
100
ns
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
0.9
µs
tBUF(1)
Time the Bus Must be Free Before
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
tLOW
4.7
1.3
µs
4
0.6
µs
Clock Low Period
4.7
1.3
µs
tHIGH
Clock High Period
4
0.6
µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
µs
tHD:DAT
Data In Hold Time
0
0
ns
tSU:DAT
Data In Setup Time
250
100
ns
tR(1)
SDA and SCL Rise Time
1
0.3
µs
SDA and SCL Fall Time
300
300
ns
tF
(1)
tSU:STO
Stop Condition Setup Time
tDH
Data Out Hold Time
4
0.6
µs
100
100
ns
Power-Up Timing(1)(2)
Symbol
Parameter
tPUR
tPUW
Min
Typ
Max
Units
Power-up to Read Operation
1
ms
Power-up to Write Operation
1
ms
Max
Units
5
ms
Write Cycle Limits
Symbol
Parameter
tWR
Write Cycle Time
Min
Typ
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
3
Doc No. 1073, Rev. D
CAT24FC01
FUNCTIONAL DESCRIPTION
SDA: Serial Data/Address
The CAT24FC01 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
The CAT24FC01 supports the I2C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC01 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated. A maximum of
8 devices may be connected to the bus as determined by
the device address inputs A0, A1, and A2.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading multiple
devices. A maximum of eight devices can be cascaded
when using the device.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24FC01 when this pin is tied
to VCC, the entire array of memory is write protected.
When left floating, memory is unprotected.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24FC01 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input pin.
Figure 1. Bus Timing
tF
tHIGH
tLOW
tR
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tBUF
tDH
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
ACK
BYTE n
tWR
STOP
CONDITION
START
CONDITION
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1073, Rev. D
STOP BIT
4
ADDRESS
CAT24FC01
I2C BUS PROTOCOL
and define which device the Master is accessing. Up to
eight CAT24FC01 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
The following defines the features of the I2C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
address byte, the CAT24FC01 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC01 then performs a Read or a Write operation
depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC01 monitors the
SDA and SCL lines and will not respond until this
condition is met.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
STOP Condition
The CAT24FC01 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
When the CAT24FC01 begins a READ mode, it transmits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this acknowledge, the CAT24FC01 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC01 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
Normal Read and Write
DEVICE ADDRESS
5
Doc No. 1073, Rev. D
CAT24FC01
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24FC01 in a single write cycle.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24FC01. After receiving another
acknowledge from the Slave, the Master device transmits
the data byte to be written into the addressed memory
location. The CAT24FC01 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, the device will not respond to any request from
the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24FC01 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24FC01 is still busy with
the write operation, no ACK will be returned. If the
CAT24FC01 has completed the write operation, an ACK
will be returned and the host can then proceed with the
next read or write operation.
Page Write
WRITE PROTECTION
The CAT24FC01 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT24FC01 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
The CAT24FC01 is designed with a hardware protect
pin that enables the user to protect the entire memory.
Thehardware protection feature of the CAT24FC01 is
designed into the part to provide added flexibility to the
design engineers. The write protection feature of
CAT24FC01 allows the user to protect against inadvertent
programming of the memory array. If the WP pin is tied
to Vcc, the entire memory array is protected and becomes
read only. The entire memory becomes write protected
regardless of whether the write protect register has been
written or not. When WP pin is tied to Vcc, the user
cannot program the write protect register. If the WP pin
is left floating or tied to Vss, the device can be written
into.
If the Master transmits more than 16 bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
Figure 6. Byte Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Page Write Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+7
S
P
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1073, Rev. D
S
T
O
P
6
A
C
K
A
C
K
CAT24FC01
Read Operations
The READ operation for the CAT24FC01 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
read. After the CAT24FC01 acknowledge the word
address, the Master device resends the START condition
and the slave address, this time with the R/W bit set to
one. The CAT24FC01 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Immediate Address Read
Sequential Read
The CAT24FC01’s address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to
address N, the READ immediately following would
access data from address N + 1. If N = 217, the counter
will not ‘wrap around’. After the CAT24FC01 receives its
slave address information (with the R/W bit set to one),
it issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24FC01 sends the initial 8-bit
data requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC01 will continue to output a byte for
each acknowledge sent by the Master. The operation
will terminate operation when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from the CAT24FC01 is
outputted sequentially with data from address N followed
by data from address N + 1. The READ operation
address counter increments all of the CAT24FC01
address bits so that the entire memory array can be
read during one operation.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
Figure 8. Immediate Address Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
S
P
A
C
K
DATA
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
7
STOP
Doc No. 1073, Rev. D
CAT24FC01
Figure 9. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
S
T
O
P
SLAVE
ADDRESS
S
S
A
C
K
P
A
C
K
A
C
K
DATA n
N
O
A
C
K
Figure 10. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
S
T
O
P
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1073, Rev. D
8
CAT24FC01
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
24FC01
Product
Number
Suffix
J
I
Temperature Range
I = Industri
E = Extended (-40°C to +125°C)
TE13
REV-F
Tape & Reel
TE13: 2000/Reel
Die Revision
Package
P: PDIP
J: SOIC (JEDEC)
R: MSOP
U: TSSOP
L: PDIP (Lead free, Halogen free)
W: SOIC (JEDEC), (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Z: MSOP (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 24FC01JI-TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel)
9
Doc No. 1073, Rev. D
REVISION HISTORY
Date
Revision Comments
03/01/04
A
Initial Issue
05/15/04
B
Updated D.C. Operating Characteristics
Updated Write Cycle Limits
Updated Ordering Information
Updated Revision History
Updated Rev Number
06/07/04
C
Updated Write Cycle Limits
07/27/04
D
Updated table notes on page 2
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
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situation where personal injury or death may occur.
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
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Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
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Publication #:
Revison:
Issue date:
1073
D
7/27/04
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