Cypress CY7C131-15JC 1k x 8 dual-port static ram Datasheet

CY7C130/CY7C131
CY7C140/CY7C141
1K x 8 Dual-Port Static RAM
Features
Functional Description
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
The CY7C130/CY7C131/CY7C140 and CY7C141 are
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/ CY7C131 can be utilized as either a
standalone 8-bit dual-port static RAM or as a master dual-port
RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
• 1K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 110 mA (max.)
• Fully asynchronous operation
• Automatic power-down
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). Two flags are
provided on each port, BUSY and INT. BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. INT is an interrupt flag indicating
that data has been placed in a unique location (3FF for the left
port and 3FE for the right port). An automatic power-down
feature is controlled independently on each port by the chip
enable (CE) pins.
• Master CY7C130/CY7C131 easily expands data bus
width to 16 or more bits using slave CY7C140/CY7C141
• BUSY output flag on CY7C130/CY7C131; BUSY input
on CY7C140/CY7C141
• INT flag for port-to-port communication
• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC,
52-Pin TQFP.
• Pb-Free packages available
The CY7C130 and CY7C140 are available in 48-pin DIP. The
CY7C131 and CY7C141 are available in 52-pin PLCC, 52-pin
Pb-free PLCC, 52-pin PQFP and 52-pin Pb-free PQFP.
Logic Block Diagram
Pin Configurations
R/WL
CEL
R/WR
CER
OEL
OER
I/O7L
I/O
CONTROL
I/O0L
I/O7R
I/O
CONTROL
I/O0R
[1]
BUSYL
A 9L
A 0L
BUSYR
ADDRESS
DECODER
CEL
OEL
MEMORY
ARRAY
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
R/WL
A 9R
ADDRESS
DECODER
A 0R
CER
OER
R/WR
[2]
[2]
INTL
INTR
DIP
Top View
CE L
R/W L
BUSY L
INTL
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
12 7C130 37
13 7C140 36
14
35
15
34
16
33
17
32
18
31
30
19
20
29
28
21
22
27
23
26
24
25
VCC
CER
R/WR
BUSYR
INTR
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
Note:
1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor
CY7C140/CY7C141 (Slave): BUSY is input.
2. Open drain outputs: pull-up resistor required.
Cypress Semiconductor Corporation
Document #: 38-06002 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 29, 2005
CY7C130/CY7C131
CY7C140/CY7C141
Pin Configuration (continued)
OER
A0R
A1R
A2R
A3R
A4R
A5R
I/O5R
I/O6R
A6R
A7R
A8R
A9R
NC
I/O7R
BUSYR
INTR
NC
CER
R/WR
BUSYL
R/W
L
CEL
VCC
52 5150 49 48 47 4645 44 43 42 41 40
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O2R
I/O3R
I/O4R
1
2
3
4
5
6
7
8
9
10
11
12
13
OER
A0R
A1R
A2R
A3R
A4R
A5R
39
38
37
36
35
34
33
32
31
30
29
28
27
7C131
7C141
A6R
A7R
A8R
A9R
NC
I/O7R
I/O5R
I/O6R
I/O2R
I/O3R
I/O4R
NC
GND
I/O0R
I/O1R
I/O6L
I/O7L
1415 16 17 18 19 20 21 22 23 24 25 26
I/O4L
I/O5L
I/O0R
I/O1R
NC
GND
A0L
OEL
NC
INTL
BUSYR
INTR
NC
CER
R/WR
PQFP
Top View
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C131
40
7C141
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
I/O6L
I/O7L
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O4L
I/O5L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
BUSYL
R/W
L
CEL
VCC
A0L
OEL
NC
INTL
PLCC
Top View
Pin Definitions
Left Port
Right Port
Description
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L–A11/12L
A0R–A11/12R
Address
I/O0L–I/O15/17L
I/O0R–I/O15/17R
Data Bus Input/Output
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
VCC
Power
GND
Ground
Selection Guide
7C131-15[3]
7C141-15
7C131-25[3]
7C141-25
7C130-30
7C131-30
7C140-30
7C141-30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Unit
Maximum Access Time
15
25
30
35
45
55
ns
Maximum Operating Com’l/Ind
Current
Military
190
170
170
120
120
110
mA
170
170
120
Maximum Standby
Current
75
45
45
35
65
65
45
Com’l/Ind
Military
65
65
mA
Shaded areas contain preliminary information.
Note:
3. 15 and 25-ns version available only in PLCC/PQFP packages.
Document #: 38-06002 Rev. *D
Page 2 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Maximum Ratings[4]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Ambient
Temperature
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
–55°C to +125°C
5V ± 10%
Range
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ........................................... –0.5V to +7.0V
Commercial
Industrial
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Military
[5]
DC Input Voltage............................................ –3.5V to +7.0V
Output Current into Outputs (LOW) .............................20 mA
Electrical Characteristics Over the Operating Range[6]
7C131-15[3]
7C141-15
Parameter
Description
Test Conditions
Min.
2.4
VOH
Output HIGH
Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW
Voltage
IOL = 4.0 mA
IOL = 16.0
mA[7]
Max.
7C130-30[3]
7C131-25,30
7C140-30
7C141-25,30
7C130-35,45
7C131-35,45
7C140-35,45
7C141-35,45
Min.
Min.
Max.
2.4
Max.
2.4
V
0.4
0.4
0.4
0.5
0.5
0.5
0.5
Input HIGH Voltage
Input LOW Voltage
IIX
Input Leakage
Current
GND < VI < VCC
–5
+5
–5
+5
–5
+5
IOZ
Output Leakage
Current
GND < VO < VCC,
Output Disabled
–5
+5
–5
+5
–5
+5
IOS
Output Short
VCC = Max.,
Circuit Current[8, 9] VOUT = GND
ICC
VCC Operating
Supply Current
CE = VIL,
Outputs Open,
f = fMAX[10]
Com’l
Standby Current
Both Ports,
TTL Inputs
CEL and CER >
VIH, f = fMAX[10]
Com’l
Standby Current
One Port,
TTL Inputs
CEL or CER > VIH, Com’l
Active Port Outputs
Mil
Open,
[10]
f = fMAX
135
Standby Current
Both Ports,
CMOS Inputs
Both Ports CEL and Com’l
CER >
Mil
VCC – 0.2V,
VIN > VCC – 0.2V
or VIN < 0.2V, f = 0
15
ISB3
Max. Unit
0.4
VIL
ISB2
Min.
2.4
VIH
ISB1
7C130-55
7C131-55
7C140-55
7C141-55
2.2
2.2
0.8
2.2
0.8
2.2
0.8
V
0.8
V
–5
+5
µA
–5
+5
µA
–350
–350
–350
190
170
120
110
170
120
45
35
65
45
90
75
115
90
15
15
15
15
Mil
75
65
Mil
115
15
V
–350 mA
mA
mA
mA
mA
Shaded areas contain preliminary information.
Note:
4. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. TA is the “instant on” case temperature
6. See the last page of this specification for Group A subgroup testing information.
7. BUSY and INT pins only.
8. Duration of the short circuit should not exceed 30 seconds.
9. This parameter is guaranteed but not tested.
10. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.
Document #: 38-06002 Rev. *D
Page 3 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Electrical Characteristics Over the Operating Range[6] (continued)
Parameter
ISB4
Description
Test Conditions
Standby Current
One Port,
CMOS Inputs
7C131-15[3]
7C141-15
7C130-30[3]
7C131-25,30
7C140-30
7C141-25,30
7C130-35,45
7C131-35,45
7C140-35,45
7C141-35,45
Min.
Min.
Min.
Max.
One Port CEL or
Com’l
CER > VCC – 0.2V,
Mil
VIN > VCC – 0.2V
or VIN < 0.2V,
Active Port Outputs
Open,
f = fMAX[10]
125
Max.
Max.
105
7C130-55
7C131-55
7C140-55
7C141-55
Min.
Max. Unit
85
70
105
85
mA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
15
pF
10
pF
TA = 25°C, f = 1 MHz,
VCC = 5.0V
AC Test Loads and Waveforms
R1 893Ω
5V
OUTPUT
5V
R1 893Ω
5V
OUTPUT
R2
347Ω
30 pF
INCLUDING
JIGAND
SCOPE
Equivalent to:
(a)
THÉVENIN EQUIVALENT
OUTPUT
250Ω
Document #: 38-06002 Rev. *D
R2
347Ω
5 pF
INCLUDING
JIGAND
SCOPE
1.40V
BUSY
OR
INT
281Ω
30
pF
(b)
3.0V
GND
BUSY Output Load
(CY7C130/CY7C131 ONLY)
ALL INPUT PULSES
10%
≤ 5 ns
90%
90%
10%
≤5ns
Page 4 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics Over the Operating Range[6, 11]
[3]
7C131-15
7C141-15
Parameter
Description
Min.
Max.
7C130-25[3]
7C131-25
7C140-25
7C141-25
Min.
Max.
7C130-30
7C131-30
7C140-30
7C141-30
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
[12]
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
tDOE
ns
30
ns
10
15
20
ns
OE LOW to Low
OE HIGH to High Z[9, 13, 14]
Z[9, 13, 14]
3
Power-Up[9]
CE LOW to
tPD
CE HIGH to Power-Down[9]
3
10
3
Z[9, 13, 14]
tPU
WRITE
ns
25
Z[9, 13, 14]
CE HIGH to High
30
0
15
OE LOW to Data Valid
CE LOW to Low
25
0
ns
[12]
CE LOW to Data Valid
tHZOE
tHZCE
15
0
30
[12]
tLZOE
tLZCE
25
3
15
5
10
0
5
15
0
15
ns
15
ns
15
0
25
ns
ns
ns
25
ns
CYCLE[15]
tWC
Write Cycle Time
15
25
30
ns
tSCE
CE LOW to Write End
12
20
25
ns
tAW
Address Set-Up to Write End
12
20
25
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
R/W Pulse Width
12
15
25
ns
tSD
Data Set-Up to Write End
10
15
15
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
R/W LOW to High Z[14]
tLZWE
[14]
R/W HIGH to Low Z
10
0
15
0
15
0
ns
ns
Shaded areas contain preliminary information.
Note:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
IOL/IOH, and 30-pF load capacitance.
12. AC Test Conditions use VOH = 1.6V and VOL = 1.4V.
13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
14. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-06002 Rev. *D
Page 5 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics Over the Operating Range[6, 11] (continued)
7C131-15[3]
7C141-15
Parameter
Description
Min.
Max.
7C130-25[3]
7C131-25
7C140-25
7C141-25
Min.
Max.
7C130-30
7C131-30
7C140-30
7C141-30
Min.
Max.
Unit
BUSY/INTERRUPT TIMING
tBLA
BUSY LOW from Address Match
[16]
15
20
20
ns
tBHA
BUSY HIGH from Address Mismatch
15
20
20
ns
tBLC
BUSY LOW from CE LOW
15
20
20
ns
20
ns
[16]
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set Up for Priority
5
15
5
20
5
ns
tWB[17]
R/W LOW after BUSY LOW
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
13
20
30
ns
tBDD
BUSY HIGH to Valid Data
15
25
30
ns
tDDD
Write Data Valid to Read Data Valid
Note 18
Note 18
Note 18
ns
tWDD
Write Pulse to Data Delay
Note 18
Note 18
Note 18
ns
INTERRUPT TIMING
tWINS
R/W to INTERRUPT Set Time
15
25
25
ns
tEINS
CE to INTERRUPT Set Time
15
25
25
ns
tINS
Address to INTERRUPT Set Time
15
25
25
ns
OE to INTERRUPT Reset
Time[16]
15
25
25
ns
tEINR
CE to INTERRUPT Reset
Time[16]
15
25
25
ns
tINR
Address to INTERRUPT Reset Time[16]
15
25
25
ns
tOINR
Shaded areas contain preliminary information.
Note:
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C140/CY7C141 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Switching Characteristics Over the Operating Range[6,11]
7C130-35
7C131-35
7C140-35
7C141-35
Parameter
Description
Min.
Max.
7C130-45
7C131-45
7C140-45
7C141-45
Min.
Max.
7C130-55
7C131-55
7C140-55
7C141-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
[12]
45
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid[12]
35
45
55
ns
tDOE
[12]
20
25
25
ns
tLZOE
[9, 13, 14]
OE LOW to Low Z
0
tHZOE
OE HIGH to High Z
tLZCE
CE LOW to Low Z[9, 13, 14]
Document #: 38-06002 Rev. *D
0
3
[9, 13, 14]
45
ns
tAA
OE LOW to Data Valid
35
55
0
3
20
5
55
ns
3
20
5
ns
25
5
ns
ns
ns
Page 6 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics Over the Operating Range[6,11] (continued)
7C130-35
7C131-35
7C140-35
7C141-35
Parameter
tHZCE
tPU
tPD
Description
CE HIGH to High Z
Min.
[9, 13, 14]
[9]
CE LOW to Power-Up
Max.
7C130-45
7C131-45
7C140-45
7C141-45
Min.
20
0
[9]
CE HIGH to Power-Down
Max.
7C130-55
7C131-55
7C140-55
7C141-55
Min.
20
0
35
Max.
Unit
25
ns
0
35
ns
35
ns
WRITE CYCLE[15]
tWC
Write Cycle Time
35
45
55
ns
tSCE
CE LOW to Write End
30
35
40
ns
tAW
Address Set-Up to Write End
30
35
40
ns
tHA
Address Hold from Write End
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
R/W Pulse Width
25
30
30
ns
tSD
Data Set-Up to Write End
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
R/W LOW to High Z[14]
tLZWE
R/W HIGH to Low Z[14]
20
0
20
0
25
0
ns
ns
BUSY/INTERRUPT TIMING
tBLA
BUSY LOW from Address Match
tBHA
BUSY HIGH from Address
tBLC
BUSY LOW from CE LOW
Mismatch[16]
HIGH[16]
20
25
30
ns
20
25
30
ns
20
25
30
ns
30
ns
tBHC
BUSY HIGH from CE
tPS
Port Set Up for Priority
5
20
5
25
5
ns
tWB[17]
R/W LOW after BUSY LOW
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH
30
35
35
ns
tBDD
BUSY HIGH to Valid Data
35
45
45
ns
tDDD
Write Data Valid to Read Data Valid
Note
18
Note
18
Note
18
ns
tWDD
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
INTERRUPT TIMING
tWINS
R/W to INTERRUPT Set Time
25
35
45
ns
tEINS
CE to INTERRUPT Set Time
25
35
45
ns
tINS
Address to INTERRUPT Set Time
25
35
45
ns
OE to INTERRUPT Reset
Time[16]
25
35
45
ns
tEINR
CE to INTERRUPT Reset
Time[16]
25
35
45
ns
tINR
Address to INTERRUPT Reset Time[16]
25
35
45
ns
tOINR
Document #: 38-06002 Rev. *D
Page 7 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms
Read Cycle No. 1[19, 20]
Either Port Address Access
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATAVALID
DATA VALID
Read Cycle No. 2[19, 21]
Either Port CE/OE Access
CE
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
tLZCE
DATA VALID
DATA OUT
tPU
tPD
ICC
ISB
Read Cycle No. 3[20]
Read with BUSY, Master: CY7C130 and CY7C131
tRC
ADDRESSR
ADDRESS MATCH
tPWE
R/WR
tHD
DINR
VALID
ADDRESS MATCH
ADDRESSL
tPS
tBHA
BUSYL
tBLA
tBDD
DOUTL
VALID
tWDD
tDDD
Notes:
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = VIL and OE = VIL.
21. Address valid prior to or coincident with CE transition LOW.
Document #: 38-06002 Rev. *D
Page 8 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Write Cycle No. 1 (OE Three-States Data I/Os—Either Port[15, 22]
Either Port
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
R/W
tSD
DATAIN
tHD
DATA VALID
OE
tHZOE
HIGH IMPEDANCE
DOUT
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[16, 23]
tWC
ADDRESS
tSCE
tHA
CE
tSA
tAW
tPWE
R/W
tSD
DATAIN
tHD
DATA VALID
tHZWE
tLZWE
HIGH IMPEDANCE
DATAOUT
Notes:
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required tSD.
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06002 Rev. *D
Page 9 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESSL,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSYL
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
ADDRESSL
tRC or tWC
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESS R
tBLA
tBHA
BUSYR
Right Address Valid First:
ADDRESSR
tRC or tWC
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSYL
Document #: 38-06002 Rev. *D
Page 10 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Busy Timing Diagram No. 3
Write with BUSY (Slave:CY7C140/CY7C141)
CE
tPWE
R/W
tWB
tWH
BUSY
Document #: 38-06002 Rev. *D
Page 11 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR
tWC
ADDRL
WRITE 3FF
tINS
tHA
CEL
tEINS
R/WL
tSA
tWINS
INTR
Right Side Clears INTR
tRC
ADDRR
READ 3FF
tHA
tINT
CER
tEINR
R/WR
OER
tOINR
INTR
Right Side Sets INTL
t WC
ADDRR
WRITE 3FE
tHA
tINS
CER
tEINS
R/WR
INTL
tSA
tWINS
Left Side Clears INTL
tRC
ADDRR
READ 3FE
tHA
CEL
tINR
tEINR
R/WL
OEL
tOINR
INTL
Document #: 38-06002 Rev. *D
Page 12 of 19
CY7C130/CY7C131
CY7C140/CY7C141
ICC
1.0
0.8
0.6
0.4
1.0
0.8
0.6
0.0
4.0
4.5
5.0
5.5
VCC = 5.0V
VIN = 5.0V
0.4
I SB3
0.2
I SB3
0.2
ICC
0.6
–55
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
1.6
1.3
1.4
NORMALIZED tAA
1.2
1.1
TA = 25°C
1.2
1.0
VCC = 5.0V
0.8
0.9
4.5
5.0
5.5
0.6
–55
6.0
25
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
30.0
2.5
25.0
2.0
20.0
15.0
1.5
0.5
VCC = 4.5V
TA = 25°C
5.0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 38-06002 Rev. *D
80
60
VCC = 5.0V
TA = 25°C
40
20
0
0
5.0
0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
140
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
120
100
80
60
40
VCC = 5.0V
TA = 25°C
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
1.25
NORMALIZED ICC vs. CYCLE TIME
VCC = 4.5V
TA = 25°C
VIN = 0.5V
1.0
0.75
10.0
1.0
0
100
125
DELTA tAA (ns)
NORMALIZED tPC
0.8
4.0
120
NORMALIZED ICC
NORMALIZED tAA
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
0.0
125
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1.0
25
OUTPUT SINK CURRENT (mA)
1.2
1.2
NORMALIZED ICC, ISB
NORMALIZED ICC, ISB
1.4
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
0
200
400
600
800 1000
CAPACITANCE (pF)
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 13 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Ordering Information
Speed
(ns)
30
35
45
55
15
25
30
35
45
55
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C130-30PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C130-45PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-45PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-45DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C130-55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C130-55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C130-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C131-15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C131-15JXC
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C131-15NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-15JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-15JXI
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C131-25JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-25JXC
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C131-25NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-25NXC
N52
52-Pin Pb-Free Plastic Quad Flatpack
CY7C131-25JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-25NI
N52
52-Pin Plastic Quad Flatpack
CY7C131-30JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-30NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-30JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C131-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C131-35NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-35JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-35NI
N52
52-Pin Plastic Quad Flatpack
CY7C131-45JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-45NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-45JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-45NI
N52
52-Pin Plastic Quad Flatpack
CY7C131-55JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-55JXC
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C131-55NC
N52
52-Pin Plastic Quad Flatpack
CY7C131-55NXC
N52
52-Pin Pb-Free Plastic Quad Flatpack
CY7C131-55JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C131-55JXI
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C131-55NI
N52
52-Pin Plastic Quad Flatpack
Document #: 38-06002 Rev. *D
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 14 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Ordering Information (continued)
Speed
(ns)
30
35
45
55
15
25
30
35
45
55
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C140-30PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C140-30PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-35PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C140-35PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-35DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C140-45PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C140-45PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-45DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C140-55PC
P25
48-Lead (600-Mil) Molded DIP
Commercial
CY7C140-55PI
P25
48-Lead (600-Mil) Molded DIP
Industrial
CY7C140-55DMB
D26
48-Lead (600-Mil) Sidebraze DIP
Military
CY7C141-15JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C141-15NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-25JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-25JXC
J69
52-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C141-25NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-25JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-25NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-30JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-30NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-30JI
J69
52-Lead Plastic Leaded Chip Carrier
Industrial
CY7C141-35JC
J69
52-Lead Plastic Leaded Chip Carrier
Commercial
CY7C141-35NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-35JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-35NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-45JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-45NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-45JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-45NI
N52
52-Pin Plastic Quad Flatpack
CY7C141-55JC
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-55NC
N52
52-Pin Plastic Quad Flatpack
CY7C141-55JI
J69
52-Lead Plastic Leaded Chip Carrier
CY7C141-55NI
N52
52-Pin Plastic Quad Flatpack
Document #: 38-06002 Rev. *D
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 15 of 19
CY7C130/CY7C131
CY7C140/CY7C141
MILITARY SPECIFICATIONS
Switching Characteristics
Group A Subgroup Testing
Parameter
Subgroups
READ CYCLE
DC Characteristics
Parameter
Subgroups
VOH
1, 2, 3
VOL
1, 2, 3
VIH
1, 2, 3
VIL Max.
1, 2, 3
IIX
1, 2, 3
IOZ
1, 2, 3
ICC
1, 2, 3
ISB1
1, 2, 3
ISB2
1, 2, 3
ISB3
1, 2, 3
ISB4
1, 2, 3
tRC
7, 8, 9, 10, 11
tAA
7, 8, 9, 10, 11
tACE
7, 8, 9, 10, 11
tDOE
7, 8, 9, 10, 11
WRITE CYCLE
tWC
7, 8, 9, 10, 11
tSCE
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tPWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
BUSY/INTERRUPT TIMING
tBLA
7, 8, 9, 10, 11
tBHA
7, 8, 9, 10, 11
tBLC
7, 8, 9, 10, 11
tBHC
7, 8, 9, 10, 11
tPS
7, 8, 9, 10, 11
tWINS
7, 8, 9, 10, 11
tEINS
7, 8, 9, 10, 11
tINS
7, 8, 9, 10, 11
tOINR
7, 8, 9, 10, 11
tEINR
7, 8, 9, 10, 11
tINR
7, 8, 9, 10, 11
BUSY TIMING
tWB[24]
7, 8, 9, 10, 11
tWH
7, 8, 9, 10, 11
tBDD
7, 8, 9, 10, 11
Note:
24. CY7C140/CY7C141 only.
Document #: 38-06002 Rev. *D
Page 16 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Package Diagrams
48-Lead (600-Mil) Sidebraze DIP D26
MIL-STD-1835 D-14 Config. C
51-80044 **
52-Lead Plastic Leaded Chip Carrier J69
52-Lead Pb-Free Plastic Leaded Chip Carrier J69
SEATING PLANE
PIN #1 ID
7
1
MIN.
MAX.
0.004
DIMENSIONS IN INCHES
47
8
46
0.013
0.021
0.785
0.795
0.750
0.756
0.045
0.055
20
0.690
0.730
34
0.023
0.033
21
33
0.750
0.756
0.785
0.795
Document #: 38-06002 Rev. *D
0.020 MIN.
0.090
0.130
51-85004-*A
0.165
0.200
Page 17 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Package Diagrams (continued)
48-Lead (600-Mil) Molded DIP P25
51-85020-*A
52-Lead Plastic Quad Flatpack N52
52-Lead Pb-Free Plastic Quad Flatpack N52
51-85042-**
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06002 Rev. *D
Page 18 of 19
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C130/CY7C131
CY7C140/CY7C141
Document History Page
Document Title: CY7C130/CY7C131/CY7C140/CY7C141 1K x 8 Dual-Port Static RAM
Document Number: 38-06002
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110169
09/29/01
SZV
Change from Spec number: 38-00027 to 38-06002
*A
122255
12/26/02
RBI
Power up requirements added to Maximum Ratings Information
*B
236751
See ECN
YDT
Removed cross information from features section
*C
325936
See ECN
RUY
Added pin definitions table, 52-pin PQFP package diagram and Pb-free
information
*D
393153
See ECN
YIM
Added CY7C131-15JI to ordering information
Added Pb-Free parts to ordering information:
CY7C131-15JXI
Document #: 38-06002 Rev. *D
Page 19 of 19
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