TOSHIBA TC55NEM208AFTN55

TC55NEM208AFPN/AFTN55,70
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55NEM208AFPN/AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a
single 5V ± 10% power supply. Advanced circuit technology provides both high speed and low power at an operating
current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1 µA
standby current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select
the device and for data retention control, and output enable ( OE ) provides fast memory access. This device is well
suited to various microprocessor system applications where high speed, low power and battery backup are required.
And, with a guaranteed operating range of −40° to 85°C, the TC55NEM208AFPN/AFTN can be used in
environments exhibiting extreme temperature conditions. The TC55NEM208AFPN/AFTN is available in a
standard plastic 32-pin small-outline package (SOP) and normal and reverse pinout plastic 32-pin
thin-small-outline package (TSOP).
FEATURES
•
•
•
•
•
•
•
Low-power dissipation
Operating: 15 mW/MHz (typical)
Single power supply voltage of 5 V ± 10%
Power down features using CE .
Data retention supply voltage of 2.0 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of −40° to 85°C
Standby Current (maximum):20 µA
•
TC55NEM208AFPN/AFTN
•
PIN ASSIGNMENT (TOP VIEW)
Access Times (maximum):
55
70
Access Time
55 ns
70 ns
CE Access Time
55 ns
70 ns
OE Access Time
30 ns
35 ns
Package:
SOP32-P-525-1.27 (AFPN)
(Weight:
TSOP II32-P-400-1.27 (AFTN) (Weight:
g typ)
g typ)
PIN NAMES
32 PIN SOP & TSOP
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
A15
A17
R/W
A13
A8
A9
A11
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
A0~A18
Address Inputs
R/W
Read/Write Control
OE
Output Enable
CE
Chip Enable
I/O1~I/O8
Data Inputs/Outputs
VDD
Power (+5 V)
GND
Ground
(AFPN/AFTN)
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TC55NEM208AFPN/AFTN55,70
BLOCK DIAGRAM
ROW ADDRESS
DECODER
ROW ADDRESS
REGISTER
VDD
GND
MEMORY CELL ARRAY
2,048 × 256 × 8
(4,194,304)
8
SENSE AMP
COLUMN ADDRESS
DECODER
CLOCK
GENERATOR
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
DATA
CONTROL
A4
A5
A6
A7
A8
A9
A11
A14
A15
A16
A18
ROW ADDRESS
BUFFER
CE
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
CE
A0 A1 A2 A3 A10 A12A13 A17
OE
R/W
CE
CE
OPERATING MODE
MODE
CE
OE
R/W
I/O1~I/O8
POWER
Read
L
L
H
Output
IDDO
Write
L
*
L
Input
IDDO
Output Deselect
L
H
H
High-Z
IDDO
Standby
H
*
*
High-Z
IDDS
* = don't care
H = logic high
L = logic low
MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
VDD
Power Supply Voltage
−0.3~7.0
V
VIN
Input Voltage
−0.3*~7.0
V
VI/O
Input/Output Voltage
−0.5~VDD + 0.5
V
PD
Power Dissipation
0.6
W
Tsolder
Soldering Temperature (10s)
260
°C
Tstg
Storage Temperature
−55~150
°C
Topr
Operating Temperature
−40~85
°C
*: −2.0 V when measured at a pulse width of 20ns
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TC55NEM208AFPN/AFTN55,70
DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VDD
Power Supply Voltage
4.5
5.0
5.5
V
VIH
Input High Voltage
2.2

VDD + 0.3
V
VIL
Input Low Voltage
−0.3*

0.6
V
VDH
Data Retention Supply Voltage
2.0

5.5
V
*: −2.0 V when measured at a pulse width of 20 ns
DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 5 V ± 10%)
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT


±1.0
µA
IIL
Input Leakage
Current
VIN = 0 V~VDD
IOH
Output High Current
VOH = 2.4 V
−1.0


mA
IOL
Output Low Current
VOL = 0.4 V
2.1


mA
ILO
Output Leakage
Current
CE = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD


±1.0
µA
CE = VIL and R/W = VIH,
IOUT = 0 mA,
Other Input = VIH/VIL
MIN


35
1 µs

8

MIN


30
1 µs

3



3
Ta = 25°C

1

Ta = −40~40°C


3
Ta = −40~85°C


20
lDDO1
Operating Current
lDDO2
mA
CE = 0.2 V and R/W = VDD − 0.2 V,
IOUT = 0 mA,
Other Input = VDD − 0.2 V/0.2 V
tcycle
mA
CE = VIH
IDDS1
Standby Current
IDDS2
CE = VDD − 0.2 V,
VDD = 2.0 V~5.5 V
mA
µA
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
TEST CONDITION
MAX
UNIT
CIN
Input Capacitance
VIN = GND
10
pF
COUT
Output Capacitance
VOUT = GND
10
pF
Note:
This parameter is periodically sampled and is not 100% tested.
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TC55NEM208AFPN/AFTN55,70
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 5 V ± 10%)
READ CYCLE
TC55NEM208AFPN/AFTN
SYMBOL
PARAMETER
55
UNIT
70
MIN
MAX
MIN
MAX
tRC
Read Cycle Time
55

70

tACC
Address Access Time

55

70
tCO
Chip Enable Access Time

55

70
tOE
Output Enable Access Time

30

35
tCOE
Chip Enable Low to Output Active
5

5

tOEE
Output Enable Low to Output Active
0

0

tOD
Chip Enable High to Output High-Z

25

30
tODO
Output Enable High to Output High-Z

25

30
tOH
Output Data Hold Time
10

10

ns
WRITE CYCLE
TC55NEM208AFPN/AFTN
SYMBOL
PARAMETER
55
UNIT
70
MIN
MAX
MIN
MAX
tWC
Write Cycle Time
55

70

tWP
Write Pulse Width
40

50

tCW
Chip Enable to End of Write
45

55

tAS
Address Setup Time
0

0

tWR
Write Recovery Time
0

0

tODW
R/W Low to Output High-Z

25

30
tOEW
R/W High to Output Active
0

0

tDS
Data Setup Time
25

30

tDH
Data Hold Time
0

0

ns
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
TEST CONDITION
100 pF + 1 TTL Gate
0.4 V, 2.4 V
Timing measurements
1.5 V
Reference level
1.5 V
tR, tF
5 ns
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TC55NEM208AFPN/AFTN55,70
TIMING DIAGRAMS
READ CYCLE
(See Note 1)
tRC
Address
A0~A18
tACC
tOH
tCO
CE
tOE
tOD
OE
tOEE
tCOE
DOUT
I/O1~8
tODO
Hi-Z
VALID DATA OUT
WRITE CYCLE 1 (R/W CONTROLLED)
Hi-Z
(See Note 4)
tWC
Address
A0~A18
tAS
tWP
tWR
R/W
tCW
CE
tODW
DOUT
I/O1~8
(See Note 2)
tOEW
Hi-Z
tDS
DIN
I/O1~8
(See Note 5)
(See Note 3)
tDH
VALID DATA IN
(See Note 5)
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TC55NEM208AFPN/AFTN55,70
WRITE CYCLE 2 (CE CONTROLLED)
(See Note 4)
tWC
Address
A0~A18
tAS
tWP
tWR
R/W
tCW
CE
tCOE
DOUT
I/O1~8
tODW
Hi-Z
Hi-Z
tDS
DIN
I/O1~8
Note:
(1)
(See Note 5)
tDH
VALID DATA IN
(See Note 5)
R/W remains HIGH for the read cycle.
(2)
If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance.
(3)
If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance.
(4)
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
(5)
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
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TC55NEM208AFPN/AFTN55,70
DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
VDH
Data Retention Supply Voltage
IDDS2
Standby Current
MIN
TYP
MAX
UNIT
2.0

5.5
V
Ta = −40~40°C


3
Ta = −40~85°C


20
µA
tCDR
Chip Deselect to Data Retention Mode Time
0


ns
tR
Recovery Time
5


ms
CE CONTROLLED DATA RETENTION MODE
VDD
DATA RETENTION MODE
4.5 V
(See Note)
(See Note)
VIH
tCDR
CE
VDD − 0.2 V
tR
GND
Note: When CE is operating at the VIH level (2.2V), the standby current is given by IDDS1 during the transition
of VDD from 4.5 to 2.4V.
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TC55NEM208AFPN/AFTN55,70
PACKAGE DIMENSIONS
Weight:
g (typ)
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TC55NEM208AFPN/AFTN55,70
PACKAGE DIMENSIONS
Weight:
g (typ)
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TC55NEM208AFPN/AFTN55,70
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
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