TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 128-MBIT (16M u 8 BITS/8M x 16BITS) CMOS NAND E2PROM DESCRIPTION The TC58DxM72x1xxxx is a 128-Mbit (138,412,032) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes/264 words u 32 pages u 1024 blocks. The device uses dual power supplies (2.7 V to 3.6 V for VCC and 1.65 V to 1.95 V for VCCQ ). The device has a 528-byte/264-words static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte/256-words increments. The Erase operation is implemented in a single block unit (16 Kbytes 512 bytes: 528 bytes u 32 pages/8k words + 256 words:264 words x 32 pages). The TC58DxM72x1xxxx is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES x Organization TC58DxM72A1xxxx Memory cell allay 528 u 32K u 8 Register 528 u 8 Page size 528 bytes Block size (16K 512) bytes x Modes Read, Reset, Auto Page Program Auto Block Erase, Status Read x Mode control Serial input/output Command control x Power supply TC58DVM72x1xxxx Vcc: 2.7V to 3.6V Vccq: 2.7V to 3.6V x Program/Erase Cycles 1E5 cycle (with ECC) x Access time Cell array to register 25 Ps max Serial Read Cycle 50 ns min x Operating current Read (50 ns cycle) 10 mA typ. Program (avg.) 10 mA typ. Erase (avg.) 10 mA typ. Standby 50 PA max. x Package TSOP I 48-P-1220-0.50 (Weight:0.53g typ) TC58DxM72F1xxxx 264 x 32k x 16 264 x 16 264 words (8k + 256) words TC58DAM72x1xxxx 2.7V to 3.6V 1.65V to 1.95V 000707EBA1 xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. xThe products described in this document are subject to the foreign exchange and foreign trade laws. xThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. xThe information contained herein is subject to change without notice. 2003-01-24 1/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 PIN ASSIGNMENT (TOP VIEW) TC58DVM72F1FT00 / TC58DAM72F1FT00 TC58DVM72A1FT00 / TC58DAM72A1FT00 x16 x8 NC NC NC NC NC GND NC NC NC NC NC GND RY / BY RY / BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 x8 x16 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCCQ VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC VSS I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 NC NC VCCQ NC NC NC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 VSS PINNAMES I/O1 to I/O8 I/O port I/O9 to I/O16 I/O port (x16) CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect RY/BY Ready/Busy GND Ground input VCC Power supply VCCQ VSS I/O port Power supply Ground 2003-01-24 2/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 BLOCK DIAGRAM VCCQ VCC VSS Status register Address register I/O1 to Column buffer Column decoder I/O Control circuit I/O8 or I/O16 Command register Data register Row address buffer decoder CE CLE ALE Logic control Control WE RE WP Row address decoder Sense amp Memory cell array RY/BY RY/BY HV generator ABSOLUTE MAXIMUM RATINGS VALUE SYMBOL RATING TC58DVxxxxx TC58DAxxxx unit VCC Power Supply Voltage 0.6~4.6 0.6~4.6 V VCCQ I/O port Power Supply Voltage 0.6~4.6 0.6~2.6 V VIN Input Voltage for Control pins 0.6~4.6 0.6~2.6 V VI/O Input/Output Voltage for I/O pins 0.6 V~VCCQ 0.3 V (≦ 4.6 V) 0.6 V~VCCQ 0.3 V (≦ 2.6 V) PD Power Dissipation 0.3 0.3 W Tsolder Soldering Temperature(10s) 260 260 °C Tstg Storage Temperature 55~150 55~150 °C Topr Operating Temperature 0~70 0~70 °C CAPACITANCE *(Ta =25°C, f= 1 MHz) SYMB0L PARAMETER CONDITION CIN Input VIN COUT Output VOUT * 0V 0V MIN MAX UNIT 10 pF 10 pF This parameter is periodically sampled and is not tested for every device. 2003-01-24 3/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 VALID BLOCKS (1) SYMBOL NVB PARAMETER Number of Valid Blocks MIN TYP. MAX UNIT 1004 1024 Blocks (1) The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. (2) The first block (block address #00) is guaranteed to be a valid block at the time of shipment. RECOMMENDED DC OPERATING CONDITIONS TC58DVM72A1xxxx,TC58DVM72F1xxxx SYMBOL PARAMETER MIN TYP. MAX UNIT VCC Power Supply Voltage 2.7 3.3 3.6 V VCCQ I/O Port Power Supply Voltage 2.7 3.6 V VIH High Level input Voltage 2.0 VCCQ 0.3 V VIL Low Level Input Voltage 0.3* 0.8 V MIN TYP. MAX UNIT * 2 V (pulse width lower than 20 ns) TC58DAM72A1xxxx,TC58DAM72F1xxxx SYMBOL PARAMETER VCC Power Supply Voltage 2.7 3.3 3.6 V VCCQ I/O Port Power Supply Voltage 1.65 1.8 1.95 V VIH High Level input Voltage VCCQ X 0.78 VCCQ 0.3 V VIL Low Level Input Voltage 0.3* VCCQ X 0.22 V * 2 V (pulse width lower than 20 ns) DC CHARACTERISTICS (Ta = 0° to 70°C, VCC SYMBOL PARAMETER 2.7 V to 3.6 V) CONDITION 0 V to VCCQ MIN TYP. MAX UNIT r10 PA r10 PA 10 30 mA IIL Input Leakage Current VIN ILO Output Leakage Current VOUT ICCO1 Operating Current (Serial Read) CE VIL, IOUT ICCO3 Operating Current (Command Input) tcycle 50 ns 10 30 mA ICCO4 Operating Current (Data Input) tcycle 50 ns 10 30 mA ICCO5 Operating Current (Address Input) tcycle 50 ns 10 30 mA ICCO7 Programming Current 10 30 mA ICCO8 Erasing Current 10 30 mA ICCS1 Standby Current CE VIH, WP 0 V/VCCQ 1 mA ICCS2 Standby Current CE VCCQ 0.2 V, WP 10 50 PA VOH High Level Output Voltage IOH mA VCCQ -0.5 V VOL Low Level Output Voltage IOL 2.1 mA 0.4 V IOL ( RY/BY ) Output Current of RY/BY pin VOL 0.4 V 8 mA 0 V to VCCQ 0 mA, tcycle 50 ns 0 V/VCCQ 2003-01-24 4/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta 0° to 70°C, VCC 2.7 V to 3.6 V) SYMBOL PARAMETER MIN MAX UNIT ns tCLS CLE Setup Time 0 tCLH CLE Hold Time 10 ns tCS CE Setup Time 0 ns tCH CE Hold Time 10 ns ns tWP Write Pulse Width 25 tALS ALE Setup Time 0 ns tALH ALE Hold Time 10 ns tDS Data Setup Time 20 ns tDH Data Hold Time 10 ns tWC Write Cycle Time 50 ns tWH WE High Hold Time 15 ns tWW WP High to WE Low 100 ns tRR Ready to RE Falling Edge 20 ns tRP Read Pulse Width 35 ns tRC Read Cycle Time 50 ns tREA RE Access Time (Serial Data Access) 35 ns tCEA CE Access Time (Serial Data Access,ID Read) 45 ns tALEA ALE Access Time (ID Read) ns tCEH CE High Time for Last Address in Serial Read Cycle Ns RE Access Time (ID Read) 35 ns tOH Data Output Hold Time 10 ns tRHZ RE High to Output High Impedance 30 ns tCHZ CE High to Output High Impedance 20 ns tREH RE High Hold Time 15 ns Output-High-impedance-to- RE Falling Edge 0 ns tRSTO RE Access Time (Status Read) 35 ns tCSTO CE Access Time (Status Read) 45 ns tRHW RE High to WE Low 0 ns tWHC WE High to CE Low 30 ns tWHR WE High to RE Low 30 ns Ps tREAID tIR Memory Cell Array to Starting Address 25 tWB WE High to Busy 200 ns tAR2 ALE Low to RE Low (Read Cycle) 50 ns tRB RE Last Clock Rising Edge to Busy(in Sequential Read) 200 ns tCRY CE High to Ready(When interrupted by CE in Read Mode) tRST Device Reset Time (Read/Program/Erase) tR 1+ Ps tr( RY/BY ) NOTES (2) (1)(2) Ps 6/10/500 AC TEST CONDITIONS CONDITION PARAMETER Input level Input pulse rise and fall time TC58DVxxxxx TC58DAxxxx 2.4 V, 0.4 V VCCQ -0.2 V, 0.2 V 3 ns 3 ns Input comparison level 1.5 V, 1.5 V 0.9 V, 0.9 V Output data comparison level 1.5 V, 1.5 V 0.9 V, 0.9 V CL (100 pF) 1 TTL CL (30 pF) Output load 2003-01-24 5/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/ BY pin. (Refer to Application Note (9) toward the end of this document.) (2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay is less than 30 ns, RY/ BY signal stays Ready. tCEH t 100 ns * *: VIH or VIL CE RE 525 526 527 A : 0 to 30 ns oBusy signal is not output. A RY/BY Busy PROGRAMMING AND ERASING CHARACTERISTICS (Ta =0° to 70°C, VCC 2.7 V to 3.6 V) SYMBOL PARAMETER MIN TYP. MAX UNIT Ps tPROG Programming Time 200 1000 N Number of Programming Cycles on Same Page 3 tBERASE Block Erasing Time 2 10 NOTES (1) ms (1): Refer to Application Note (12) toward the end of this document. 2003-01-24 6/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE CE RE Setup Time Hold Time WE tDS tDH I/O1 to I/O8 : VIH or VIL Command Input Cycle Timing Diagram CLE tCLS tCS tCLH tCH CE tWP WE tALS tALH ALE tDS tDH I/O1 to I/O8 : VIH or VIL 2003-01-24 7/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Address Input Cycle Timing Diagram tCLS CLE tCS tWC tCH tCS CE tWP tWH tWP tWH tWP WE tALS tALH ALE tDS I/O1 to I/O8 tDH A0 to A7 tDS tDH tDS A9 to A16 tDH A17 to A23 : VIH or VIL Data Input Cycle Timing Diagram tCLH CLE tCH tCS tCH tCS CE tALS tWC ALE tWP tWH tWP tWP WE tDS I/O1 to I/O8 tDH DIN0 tDS tDH DIN1 tDS tDH DIN 527 : VIH or VIL 2003-01-24 8/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Serial Read Cycle Timing Diagram tRC CE tRP tREH RE tOH tRHZ tREA tRP tREA tRP tCH tOH tRHZ tCHZ tOH tRHZ tREA I/O1 to I/O8 tRR tCEA RY/BY Status Read Cycle Timing Diagram tCLS CLE tCLS tCLH tCS CE tWP tCH WE tWHC tCSTO tCHZ tWHR RE tOH tDS I/O1 to I/O8 tDH 70H* tIR tRSTO tRHZ Status output RY/BY * 70H represents the hexadecimal number : VIH or VIL 2003-01-24 9/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Read Cycle (1) Timing Diagram CLE tCLS tCLH tCS tCH CE tWC WE tALH tALS tALH tAR2 ALE tR tRR tRC tWB RE I/O1 to I/O8 tDS tDH tDS tDH tDS tDH tDS tDH 00H A0 to A7 A9 to A16 A17toA23 tREA DOUT N DOUT N1 DOUT N2 DOUT 527 Column address N* RY/BY * Read Operation using 00H Command N: 0 to 255 : VIH or VIL Read Cycle (1) Timing Diagram: When Interrupted by CE CLE tCLS tCLH tCS tCH CE tWC tCHZ WE tALH tALS tALH tAR2 ALE tR tRC tWB RE I/O1 to I/O8 tRR tDS tDH tDS tDH tDS tDH tDS tDH 00H A0 to A7 A9 to A16 A17toA23 tOH tREA DOUT N tRHZ DOUT N1 DOUT N2 Column address N* RY/BY * Read Operation using 00H Command N: 0 to 255 : VIH or VIL 2003-01-24 10/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Read Cycle (2) Timing Diagram CLE tCLS tCLH tCS tCH CE WE tALH tALS tALH tAR2 ALE tR tRR tRC tWB RE tDS tDH I/O1 to I/O8 tDS tDH 01H tREA A0 to A7 A9 to A16 A17toA23 DOUT DOUT DOUT 256 M 256 M 1 Column address N* 527 RY/BY * Read Operation using 01H Command N: 0 to 255 : VIH or VIL Read Cycle (3) Timing Diagram CLE tCLS tCLH tCS tCH CE WE tALH tALS tALH tAR2 ALE tR tRC tWB RE tDS tDH I/O1 to I/O8 tRR 50H tDS tDH A0 to A7 A9 to A16 A17toA23 Column address N* tREA DOUT DOUT DOUT 512 M 512 M 1 527 RY/BY * Read Operation using 50H Command N: 0 to15 : VIH or VIL 2003-01-24 11/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Sequential Read (1) Timing Diagram CLE CE WE ALE RE 00H A0 to A7 A9 to A16 A17toA23 Column Page address address M N N N1 N2 527 tR 0 1 2 527 2 527 tR RY/BY Page M 1 access Page M access : VIH or VIL Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 to I/O8 01H A0 to A7 A9 to A16 A17toA23 Page Column address address M N 527 tR 256 256 N N1 0 1 tR RY/BY Page M access Page M 1 access : VIH or VIL 2003-01-24 12/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 to I/O8 50H A0 to A7 A9 to A16 A17toA23 Column Page address address M N 527 tR 512 512 512 N N1 N2 512 513 527 tR RY/BY Page M access Page M 1 access : VIH or VIL 2003-01-24 13/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Auto-Program Operation Timing Diagram tCLS CLE tCLS tCLH tCS CE tCS tCH WE tALH tALS tALH tALS tPROG tWB ALE RE tDS tDS tDH I/O1 to I/O8 tDS tDH 80H tDH A0 to A7 A9 to A16 A17toA23 DIN0 tDS tDH DIN1 DIN 527 10H 70H Status output RY/BY : VIH or VIL : Do not input data while data is being output. Auto Block Erase Timing Diagram CLE tCLS tCLH tCS tCLS CE WE tALS tALH tWB tBERASE ALE RE tDS tDH I/O1 to I/O8 60H RY/BY Auto Block Erase Setup command A9 to A16 A17toA23 D0H Erase Start command : VIH or VIL 70H Busy Status output Status Read command : Do not input data while data is being output. 2003-01-24 14/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 ID Read Operation Timing Diagram CLE tCLS tCLS tCS tCH tCS CE tCH WE tCEA tALH tALS tALH tALEA ALE RE tDS tDH tREAID tREAID I/O1 to I/O8 90H 00 98H Address input Maker code 73H Device code : VIH or VIL 2003-01-24 15/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High. Address Latch Enable: ALE The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is latched if ALE is Low. NC NC NC NC NC GND RY/BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Chip Enable: CE 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vss I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 NC NC VCCQ NC NC NC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 Vss Figure 1 pinout The device goes into a low-power Standby mode when CE goes High during a Read operation. The CE signal is ignored when device is in Busy state ( RY/ BY L), such as during a Program or Erase operation, and will not enter Standby mode even if the CE input goes High. The CE signal must stay Low during the Read mode Busy state to ensure that memory array data is correctly transferred to the data register. Write Enable: WE The WE signal is used to control the acquisition of data from the I/O port. Read Enable: RE The RE signal controls serial data output. Data is available tREA after the falling edge of RE . The internal column address counter is also incremented (Address Address l) on this falling edge. I/O Port: I/O1 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. I/O Port: I/O9 to 16 The I/O9 to 16 pins are used as a port for input/output data to and from the device. The I/O9 to 16 pins are low level(VIL) when address and command are asserted. Write Protect: WP The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: RY/BY The RY/ BY output signal is used to indicate the operating condition of the device. The RY/ BY signal is in Busy state ( RY/ BY L) during the Program, Erase and Read operations and will return to Ready state ( RY/ BY H) after completion of the operation. The output buffer for this signal is an open drain. 2003-01-24 16/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Schematic Cell Layout and Address Assignment The Program operation works on page units while the Erase operation works on block units. I/O1 512 A page consists of 528 bytes in which 512 bytes are used for main memory storage and 16 bytes are for redundancy or for other uses. I/O8 16 1 page 528 bytes 1 block 528 bytes u 32 pages (16K 512) bytes Capacity 528 bytes u 32 pages u 1024 blocks 32 pages 32768 pages 1 block 1024 blocks 8I/O 528 Figure 2. Schematic Cell Layout I/O1 256 A page consists of 264 words in which 256 words are used for main memory storage and 8 words are for redundancy or for other uses. I/O16 8 1 page 264 words 1 block 264 words u 32 pages (8K 256) words Capacity 264 words u 32 pages u 1024 blocks 32 pages 32768 pages 1 block 1024 blocks An address is read in via the I/O port over three consecutive clock cycles, as shown in Table 1. 16I/O 264 Figure 2-2. x16 Schematic Cell Layout Table 1. Addressing I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 First cycle A7 A6 A5 A4 A3 A2 A1 A0 Second cycle A16 A15 A14 A13 A12 A11 A10 A9 *L A23 A22 A21 A20 A19 A18 A17 Third cycle A0~A7: A9~A23: A14~A23: A9~A13: Column address Page address Block address NAND address in block *: A8 is automatically set to Low or High by a 00H command or a 01H command. I/O9-16 should be low when address is input. * I/O8 must be set to Low in the third cycle. 2003-01-24 17/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Operation Mode: Logic and Command Tables The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2. Table 2. Logic table CLE ALE CE Command Input H L Address Input L Data Input Serial Data Output WE *1 RE WP L H * H L H * L L L H H L L L H * * L H H * * * H * * * During Programming (Busy) * * * * * H During Erasing (Busy) * * * * * H Program, Erase Inhibit * * * * * L Standby * * H * * 0 V/Vcc * During Read (Busy) H: VIH, L: VIL, *: VIH or VIL *1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit Table 3. Command table (HEX) First Cycle Second Cycle Serial Data Input 80 Read Mode (1) 00 Read Mode (2) 01 Read Mode (3) 50 Reset FF Auto Program 10 Auto Block Erase 60 D0 Status Read 70 ID Read 90 Acceptable while Busy HEX data bit assignment (Example) Serial data input: 80H 1 c 0 0 0 0 0 0 I/O8 7 6 5 4 3 2 I/O1 0 0 0 0 0 0 0 0 0 I/O16 15 14 13 12 11 10 I/O9 c 01 command isn’t implemented by x16. Table 4 shows the operation states for Read mode. Table 4. Read mode operation states CLE ALE CE WE RE I/O1~I/O16 Power Output Select L L L H L Data output Active Output Deselect L L L H H High impedance Active H: VIH, L: VIL, *: VIH or VIL 2003-01-24 18/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 DEVICE OPERATION Read Mode (1) Read mode (1) is set when a 00H command is issued to the Command register. Refer to Figure 3 below for timing details and the block diagram. CLE CE WE ALE RE RY/BY I/O Busy N M 00H Start-address input M m Select page N Cell array Figure 3. Read mode (1) operation X8 : m=527 X16 : m=263 Read Mode (2) A data transfer operation from the cell array to the register starts on the rising edge of WE in the third cycle (after the address information has been latched). The device will be in Busy state during this transfer period. The CE signal must stay Low after the third address input and during Busy state. After the transfer period the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start pointer designated in the address input cycle. x8 only CLE CE WE ALE RE RY/BY I/O Busy N M 01H Start-address input 256 M 527 Select page N The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer is to be set after column address 256, use Read mode (2). Cell array Figure 4. Read mode (2) operation 2003-01-24 19/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Read Mode (3) Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra 16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527. CLE CE WE ALE RE RY/BY Busy 50H Addresses bits A0~A3 are used to set the start pointer for the redundant memory cells, while A4~A7 are ignored. Once a 50H command has been issued, the pointer moves to the redundant cell locations and only those 16 cells can be addressed, regardless of the value of the A4-to-A7 address. (An 00H command is necessary to move the pointer back to the 0-to-511 main memory cell location.) A0~A3 512 527 Figure 5. Read mode (3) operation X8 : m=527 , n=512 X16 : m=263 , n=256 Sequential Read(1)(2)(3) This mode allows the sequential reading of pages without additional address input. 00H 01H Address input Data output Data output tR tR tR Busy Busy Busy RY/BY (00H) 0 m (01H) n/2 (50H) n m A A Sequential Read (1) A Sequential Read (2) Sequential Read (3) Sequential Read modes (1) and (2) output the contents of addresses 0~m as shown above, while Sequential Read mode (3) outputs the contents of the redundant address locations only. When the pointer reaches the last address, the device continues to output the data from this address ** on each RE clock signal. X8 : m=527,n=512 X16 : m=263,n=256 2003-01-24 20/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the I/O port on the RE clock after a 70H command input. The resulting information is outlined in Table 5. Table 5. Status output table STATUS OUTPUT I/O1 Pass/Fail Pass: 0 I/O2 Not Used 0 I/O3 Not Used 0 I/O4 Not Used 0 I/O5 Not Used 0 I/O6 Not Used 0 I/O7 Ready/Busy Ready: 1 Busy: 0 I/O8 Write Protect Protect: 0 Not Protected: 1 I/O9 to I/O16 Not Used Fail: 1 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state. 0 An application example with multiple devices is shown in Figure 6. CE1 CE2 CE3 CEN CEN 1 Device 1 Device 2 Device 3 Device N Device N1 CLE ALE WE RE I/O1 ~I/O8 RY/BY Busy RY/BY CLE ALE WE CE1 CEN RE I/O 70H 70H Status on Device 1 Status on Device N Figure 6. Status Read timing application example System Design Note: If the RY/ BY pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device. 2003-01-24 21/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Auto Page Program The device carries out an Automatic Page Program operation when it receives a “10H” Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) 80 10 70 Data input Address Data input Program command input 0 to 527 command Status Read command RY/BY I/O Pass Fail RY/BY automatically returns to Ready after completion of the operation. Data input Program Reading & verification Selected page Figure 7. Auto Page Program operation The data is transferred (programmed) from the register to the selected page on the rising edge of WE following input of the “10H” command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Auto Block Erase The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0H” which follows the Erase Setup command “60H”. This two-cycle process for Erase operations acts as an ertra layer of protection from aceidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. 60 D0 70 Block Address Erase Start input: 2 cycles command RY/BY Status Read command I/O Pass Fail Busy 2003-01-24 22/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Reset The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The response to an “FFH” Reset command input during the various device operations is as follows: When a Reset (FFH) command is input during programming Figure 8. 80 10 FF 00 Internal VPP RY/BY tRST (max 10 Ps) When a Reset (FFH) command is input during erasing Figure 9. D0 FF 00 Internal erase voltage RY/BY tRST (max 500 Ps) When a Reset (FFH) command is input during Read operation Figure 10. 00 FF 00 RY/BY tRST (max 6 Ps) When a Status Read command (70H) is input after a Reset Figure 11. FF 70 I/O status: Pass/Fail o Pass Ready/Busy o Ready RY/BY FF 70 I/O status: Ready/Busy o Busy RY/BY When two or more Reset commands are input in succession Figure 12. (1) (2) (3) FF FF FF RY/BY The second FF command is invalid, but the third FF command is valid. 2003-01-24 23/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 ID Read The device contains ID codes which identify the device type and the manufacturer. The ID codes can be read out under the following timing conditions: CLE tCEA CE WE tALEA ALE RE tREAID 90H I/O 00 98H 73H ID Read command Maker code Device code Address 00 For the specifications of the access times tREAID, tCR and tAR1 refer to the AC Characteristics. Figure 13. ID Read timing Table 6. ID Codes read out by ID read command 90H I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data Maker code 1 0 0 1 1 0 0 0 98H Device code 0 1 1 1 0 0 1 1 73H I/O9 to I/O16 are “0” . 2003-01-24 24/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 APPLICATION NOTES AND COMMENTS (1) Power-on/off sequence: The WP signal is useful for protecting against data corruption at power-on/off. The following timing sequence is necessary. The WP signal may be negated any time after the VCC reaches 2.5 V and CE signal is kept high in power up sequence. 2.7 V 0V VCC 1.65 V 1.5 V 0V VCCQ Don’t care Don’t care CE , WE , RE CLE, ALE WP VIH VIL VIL Operation Figure 15. Power-on/off Sequence In order to operate this device stably, after VCC becomes 2.5 V and VCCQ becomes 1.5V, it recommends starting access after about 200 Ps. (2) Status after power-on The following sequence is necessary because some input signals may not be stable at power-on. Power on FF Reset Figure 16. (3) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of command while Busy state During Busy state, do not input any command except 70H and FFH. (5) Acceptable commands after Serial Input command “80H” Once the Serial Input command “80H” has been input, do not input any command other than the Program Execution command “10H” or the Reset command “FFH”. If a command other than “10H” or “FFH” is input, the Program operation is not performed. 80 XX 10 For this operation the “FFH” command is needed. Command other than “10H” or “FFH” Programming cannot be executed. 2003-01-24 25/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 (6) Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random page address programming is prohibited. From the LSB page to MSB page DATA IN: Data (1) Ex.) Random page program (Prohibition) Data (32) DATA IN: Data (1) Data register Page 0 Page 1 Data (32) Data register Page 0 Page 1 Page 2 (1) (2) (3) Page 2 (2) (16) (3) Page 15 (16) Page 15 (1) Page 31 (32) Page 31 (32) Figure 17. page programming within a block (7) Status Read during a Read operation 00 command 00 70 [A] CE WE RY/BY RE Status Read command input Address N Status Read Status output Figure 18. The device status can be read out by inputting the Status Read command “70H” in Read mode. Once the device has been set to Status Read mode by a “70H” command, the device will not return to Read mode. Therefore, a Status Read during a Read operation is prohibited. However, when the Read command “00H” is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary 2003-01-24 26/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 (8) Pointer control for “00H”, “01H” and “50H” The device has three Read modes which set the destination of the pointer. Table 8 shows the destination of the pointer, and Figure 19 is a block diagram of their operations. Table 8. Pointer Destination Pointer Read Mode 0 Command (x8) (x16) n-1 n n/2-1 n/2 A (1) 00H 0~255 0~255 (2) 01H 256~511 −−− (3) 50H 512~527 256~263 B (1) 00H (2) 01H (3) 50H m C Pointer control Figure 19 Pointer control The pointer is set to region A by the “00H” command, to region B by the “01H” command, and to region C by the “50H” command. (Example) The “00H” command must be input to set the pointer back to region A when the pointer is pointing to region C. 00H 50H Add Start point A area Add Start point A area Add Start point C area Add Start point C area Add Start point B area Add Start point A area 50H Add Start point C area Add Start point A area 00H 01H To program region C only, set the start point to region C using the 50H command. 50H 80H 10H Add 01H DIN Programming region C only Start point C Area 80H 10H Add Start point B Area Programming region B and C Figure 20. Example of How to Set the Pointer 2003-01-24 27/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 (9) RY/ BY : termination for the Ready/Busy pin ( RY/ BY ) A pull-up resistor needs to be used for termination because the RY/ BY buffer consists of an open drain DIN circuit. VCCQ Ready VCCQ R Device Busy RY/BY CL tf tr VSS 1.5 Ps Figure 21. tf tr VCCQ 1.8 V Ta 25°C CL 30 pF 1.0 Ps 15 ns 10 ns tf tr This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. 0.5 Ps 0 5 ns 1 K: 2 K: 3 K: 4 K: R 2003-01-24 28/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 (10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN 80 10 WP RY/BY tWW (100 ns min) Disable Programming WE DIN 80 10 WP RY/BY tWW (100 ns min) Enable Erasing WE DIN 60 D0 WP RY/BY tWW (100 ns min) Disable Erasing WE DIN 60 D0 WP RY/BY tWW (100 ns min) 2003-01-24 29/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 (11) When four address cycles are input Although the device may read in a fourth address, it is ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H Address input Ignored RY/BY Internal read operation starts when WE goes High in the third cycle. Figure 22. Program operation CLE CE WE ALE I/O 80H Address input Data input Ignored Figure 23. 2003-01-24 30/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 (12) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 3 segments. Each segment can be programmed individually as follows: 1st programming Data Pattern 1 2nd programming All 1s 3rd programming Result All 1s All 1s Data Pattern 2 All 1s Data Pattern 1 Data Pattern 3 Data Pattern 2 Data Pattern 3 Figure 24. Note: The input data for unprogrammed or previously programmed page segments must be “1” 2003-01-24 31/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 (13) Invalid blocks (bad blocks) The device contains unusable blocks. Therefore, at the time of use, please check whether a block is bad and do not use these bad blocks. Bad Block Bad Block Figure 26. At the time of shipment, all data bytes in a Valid Block are FFh(x8) or FFFFh(x16). For Bad Block, all bytes are not in the FFh state(x8) or FFFFh state(x16). Please don’t perform erase operation to Bad Block. Check if the device has any bad blocks after installation into the system. Figure 27 shows the test flow for bad block detection. Bad blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the Bit line by the Select gate The number of valid blocks at the time of shipment is as follows: Valid (Good) Block Number MIN TYP. MAX UNIT 1004 1024 Block Bad Block Test Flow Read Check : to verify the column address 517 bytes(x8) or 256 and 261 words(x16) of the first page in the block with FFh(x8) or FFFFh(x16) Start Block No 1 Fail Read Check Pass Block No. Bad Block *1 Block No. 1 No Block No. 1024 Yes End *1: No erase operation is allowed to detected bad blocks Figure 27 2003-01-24 32/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 (14) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE Block Erase Failure Status Read after Erase o Block Replacement Page Programming Failure Status Read after Program o Block Replacement Single Bit Programming Failure 1o0 (1) Block Verify after Program o Retry (2) ECC x ECC: Error Correction Code x Block Replacement Program Error occurs Buffer memory Block A When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 28. Erase When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery is low. Power shoetage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. 2003-01-24 33/34 TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 Package Dimensions Unit : mm Weight: 0.53g (typ.) 2003-01-24 34/34