ATMEL AT84AD001TD-EB Dual 8-bit 1 gsps adc Datasheet

Features
•
•
•
•
•
•
•
•
•
Dual ADC with 8-bit Resolution
1 Gsps Sampling Rate per Channel, 2 Gsps in Interlaced Mode
Single or 1:2 Demultiplexed Output
LVDS Output Format (100Ω)
500 mVpp Analog Input (Differential Only)
Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs
Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output)
LQFP144 Package
Temperature Range:
– 0°C < TA < 70°C (Commercial Grade)
– -40°C < TA < 85°C (Industrial Grade)
• 3-wire Serial Interface
– 16-bit Data, 3-bit Address
– 1:2 or 1:1 Output Demultiplexer Ratio Selection
– Full or Partial Standby Mode
– Analog Gain (±1.5 dB) Digital Control
– Input Clock Selection
– Analog Input Switch Selection
– Binary or Gray Logical Outputs
– Synchronous Data Ready Reset
– Data Ready Delay Adjustable on Both Channels
– Interlacing Functions:
Offset and Gain (Channel to Channel) Calibration
Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel
– Internal Static or Dynamic Built-In Test (BIT)
Dual 8-bit
1 Gsps ADC
AT84AD001B
Smart ADC™
Performance
•
•
•
•
•
•
•
•
•
Low Power Consumption: 0.7W Per Channel
Power Consumption in Standby Mode: 120 mW
1.5 GHz Full Power Input Bandwidth (-3 dB)
SNR = 42 dB Typ (6.8 ENOB), THD = -51 dBc, SFDR = -54 dBc at Fs = 1 Gsps
Fin = 500 MHz
2-tone IMD3: -54 dBc (499 MHz, 501 MHz) at 1 Gsps
DNL = 0.25 LSB, INL = 0.5 LSB
Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration)
Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration)
Low Bit Error Rate (10-13) at 1 Gsps
Application
•
•
•
•
Instrumentation
Satellite Receivers
Direct RF Down Conversion
WLAN
2153C–BDC–04/04
1
Description
The AT84AD001B is a monolithic dual 8-bit analog-to-digital converter, offering low
1.4W power consumption and excellent digitizing accuracy. It integrates dual on-chip
track/holds that provide an enhanced dynamic performance with a sampling rate of up to
1 Gsps and an input frequency bandwidth of over 1.5 GHz. The dual concept, the integrated demultiplexer and the easy interleaving mode make this device user-friendly for
all dual channel applications, such as direct RF conversion or data acquisition. The
smart function of the 3-wire serial interface eliminates the need for external components, which are usually necessary for gain and offset tuning and setting of other
parameters, leading to space and power reduction as well as system flexibility.
Functional Description
The AT84AD001B is a dual 8-bit 1 Gsps ADC based on advanced high-speed
BiCMOS technology.
Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H),
and an 8-bit flash-like architecture core analog-to-digital converter. The output data is
followed by a switchable 1:1 or 1:2 demultiplexer and LVDS output buffers (100Ω).
Two over-range bits are provided for adjustment of the external gain control on each
channel.
A 3-wire serial interface (3-bit address and 16-bit data) is included to provide several
adjustments:
•
Analog input range adjustment (±1.5 dB) with 8-bit data control using a 3-wire bus
interface (steps of 0.18 dB)
•
Analog input switch: both ADCs can convert the same analog input signal I or Q
•
Gray or binary encoder output. Output format: DMUX 1:1 or 1:2 with control of the
output frequency on the data ready output signal
•
Partial or full standby on channel I or channel Q
•
Clock selection:
•
–
Two independent clocks: CLKI and CLKQ
–
One master clock (CLKI) with the same phase for channel I and channel Q
–
One master clock but with two phases (CLKI for channel I and CLKIB for
channel Q)
ISA: Internal Settling Adjustment on channel I and channel Q
•
FiSDA: Fine Sampling Delay Adjustment on channel Q
•
Adjustable Data Ready Output Delay on both channels
•
Test mode: decimation mode (by 16), Built-In Test.
A calibration phase is provided to set the two DC offsets of channel I and channel Q
close to code 127.5 and calibrate the two gains to achieve a maximum difference of
0.5 LSB. The offset and gain error can also be set externally via the 3-wire serial
interface.
The AD84AD001B operates in fully differential mode from the analog inputs up to the
digital outputs. The AD84AD001B features a full-power input bandwidth of 1.5 GHz.
2
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 1. Simplified Block Diagram
CLKI
Divider
2 to16
Clock Buffer
DDRB
DoirI
+
Vini
S/H
Vinib
-
8bit
ADC
I
DRDA
I
DMUX
1:2
or
1:1
I
8
Gain control I
Calibration
Gain/offset
ISA I
LVDS
Clock
Buffer
LVDS
Buffer
I
2
16
DOAI
DOAIN
16
DOBI
DOBIN
2
Data
BIT
3-wire Serial Interface
3WSI
Gain control Q
Calibration
Gain/offset
ISA Q & FiSDA
+
S/H
Vinqb
-
Clock
Ldn
DMUX control
Mode
2
DoirQ
Vinq
DOIRI
DOIRIN
DMUX control
Input switch
INPUT
MUX
CLKIO
8bit
ADC
Q
8
DMUX
1: 2
or
1: 1
Q
LVDS
buffe r
Q
DOIRQ
DOIRQN
16
DOAQ
DOAQN
16
DOBQ
DOBQN
CLKQ
Clock Buffer
DDRB
Divider
2 to 16
DRDA
Q
LVDS
Clock
Buffer
2
CLKQO
3
2153C–BDC–04/04
Typical Applications
Figure 2. Satellite Receiver Application
Satellite
Low Noise Converter
(Connected to the Dish)
Bandpass
Amplifier
Dish
Satellite Tuner
Low Pass
Filter
Bandpass
Amplifier
11..12 GHz
Tunable
Band Filter
IF
Band Filter
AGC
1..2 GHz
Synthesizer
1.5 … 2.5 GHz
Local oscillator
I
I
I
Local Oscillator
Control Functions:
AT84AD001B
Clock and Carrier
90
Q
Recovery...
Q
0
Q
Clock
Q
Quadrature
Demodulation
4
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 3. Dual Channel Digital Oscilloscope Application
DAC
Gain
A
Channel A
A
Analog switch
Channel B
ADC B
DAC
Offset
FISO
RAM
DAC
Offset
Display
µP
ADC A
DAC
Gain
Channel Mode
Selection
Clock
selection
Timing
circuit
DACs
Smart dual
ADC
DACs
Table 1. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Analog positive supply voltage
VCCA
3.6
V
Digital positive supply voltage
VCCD
3.6
V
Output supply voltage
VCCO
3.6
V
VCCA to VCCD
± 0.8
V
VCCO
1.6
V
Analog input voltage
VINI or VINIB
VINQ or VINQB
1/-1
V
Digital input voltage
VD
-0.3 to VCCD + 0.3
V
Clock input voltage
VCLK or VCLKB
-0.3 to VCCD + 0.3
V
VCLK - VCLKB
-2 to 2
V
Maximum junction temperature
TJ
125
°C
Storage temperature
Tstg
-65 to 150
°C
Tleads
300
°C
Maximum difference between VCCA and VCCD
Minimum VCCO
Maximum difference between VCLK and VCLKB
Lead temperature (soldering 10s)
Note:
Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
5
2153C–BDC–04/04
Table 2. Recommended Conditions of Use
Parameter
Symbol
Comments
Recommended Value
Unit
Analog supply voltage
VCCA
3.3
V
Digital supply voltage
VCCD
3.3
V
Output supply voltage
VCCO
2.25
V
VINi -VIniB or
VINQ -VINQB
500
mVpp
Vinclk
600
mVpp
ISA
-50
ps
0 < TA < 70
-40 < TA < 85
°C
Differential analog input voltage (full-scale)
Differential clock input level
Internal Settling Adjustment (ISA) with a 3-wire
serial interface for channel I and channel Q
Operating temperature range
TAmbient
Commercial grade
Industrial grade
Electrical Operating Characteristics
Unless otherwise specified:
•
VCCA = 3.3V; VCCD = 3.3V; VCCO = 2.25V
•
VINI - VINB or VINQ - VINQB = 500 mVpp full-scale differential input
•
LVDS digital outputs (100Ω)
•
TA (typical) = 25° C
•
Full temperature range: 0° C < TA < 70° C (commercial grade) or -40° C < TA < 85° C
(industrial grade)
Table 3. Electrical Operating Characteristics in Nominal Conditions
Parameter
Symbol
Min
Resolution
Typ
Max
8
Unit
Bits
Power Requirements
Positive supply voltage
- Analog
- Digital
Output digital (LVDS) and serial interface
VCCA
VCCD
VCCO
Supply current (typical conditions)
- Analog
- Digital
- Output
Supply current (1:2 DMUX mode)
- Analog
- Digital
- Output
6
3.15
3.15
2.0
3.3
3.3
2.25
3.45
3.45
2.5
V
V
V
ICCA
ICCD
ICCO
150
230
100
180
275
120
mA
mA
mA
ICCA
ICCD
ICCO
150
260
175
180
310
210
mA
mA
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Table 3. Electrical Operating Characteristics in Nominal Conditions (Continued)
Parameter
Typ
Max
ICCA
ICCD
ICCO
150
290
180
180
350
215
ICCA
ICCD
ICCO
80
160
55
95
190
65
mA
mA
mA
Supply current
(1 channel only, 1:2 DMUX mode)
- Analog
- Digital
- Output
ICCA
ICCD
ICCO
80
170
90
95
205
110
mA
mA
mA
Supply current (full standby mode)
- Analog
- Digital
- Output
ICCA
ICCD
ICCO
12
24
3
17
34
5
mA
mA
mA
Nominal dissipation
(1 clock, 1:1 DMUX mode, 2 channels)
PD
1.4
1.7
W
Nominal dissipation (full standby mode)
stbpd
120
Supply current (2 input clocks, 1:2 DMUX mode)
- Analog
- Digital
- Output
Supply current
(1 channel only, 1:1 DMUX mode)
- Analog
- Digital
- Output
Symbol
Min
Unit
mA
mW
Analog Inputs
Full-scale differential analog input voltage
VINi - VIniB
or
VINQ - VINQB
Analog input capacitance I and Q
CIN
Full power input bandwidth (-3 dB)
FPBW
mV
450
500
550
mV
2
Gain flatness (-0.5 dB)
pF
1.5
GHz
500
MHz
Clock Input
Logic compatibility for clock inputs and DDRB
Reset (pins 124,125,126,127,128,129)
PECL/LVDS clock inputs voltages
(VCLKI/IN or VCLKQ/QN)
Differential logical level
PECL/ECL/LVDS
VIL - VIH
Clock input power level
600
-9
0
Clock input capacitance
mV
6
2
dBm
pF
Digital Outputs
Logic compatibility for digital outputs
(depending on the value of VCCO)
Differential output voltage swings
(assuming VCCO = 2.25V)
LVDS
VOD
220
270
350
mV
7
2153C–BDC–04/04
Table 3. Electrical Operating Characteristics in Nominal Conditions (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
Output levels (assuming VCCO = 2.25V)
100Ω differentially terminated
Logic 0 voltage
Logic 1 voltage
VOL
VOH
1.0
1.25
1.1
1.35
1.2
1.45
V
V
Output offset voltage (assuming VCCO = 2.25V)
100Ω differentially terminated
VOS
1125
1250
1325
mV
Output impedance
RO
50
W
Output current (shorted output)
12
mA
Output current (grounded output)
30
mA
Output level drift with temperature
1.3
mV/°C
Digital Input (Serial Interface)
Maximum clock frequency (input clk)
Fclk
50
MHz
Input logical level 0 (clk, mode, data, ldn)
-0.4
0
0.4
V
Input logical level 1 (clk, mode, data, ldn)
VCCO - 0.4
VCCO - 0.4
VCCO + 0.4
V
Output logical level 0 (cal)
-0.4
0
0.4
V
Output logical level 1 (cal)
VCCO - 0.4
VCCO
VCCO + 0.4
V
15
pF
Maximum output load (cal)
Note:
The gain setting is 0 dB, one clock input, no standby mode [full power mode], 1:1 DMUX, calibration off.
Table 4. Electrical Operating Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
DC Accuracy
No missing code
Guaranteed over specified temperature range
Differential non-linearity
DNL
0.25
0.6
LSB
Integral non-linearity
INL
0.5
1
LSB
Gain error (single channel I or Q) with calibration
-0.5
0
0.5
LSB
Input offset matching (single channel I or Q) with calibration
-0.5
0
0.5
LSB
0.062
0.064
Gain error drift against temperature
Gain error drift against VCCA
Mean output offset code with calibration
127
LSB/°C
LSB/mV
127.5
128
LSB
BER
10-13
10-10
Error/
sample
TS
170
Transient Performance
Bit Error Rate
Fs = 1 Gsps
Fin = 250 MHz
ADC settling time channel I or Q
(between 10% - 90% of output response)
VIni -ViniB = 500 mVpp
Note:
8
ps
Gain setting is 0 dB, two clock inputs, no standby mode [full power mode], 1:2 DMUX, calibration on.
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Table 5. AC Performances
Parameter
Symbol
Min
Typ
Max
Unit
42
44
dBc
40
42
dBc
41
dBc
7
7.2
Bits
6.5
6.8
Bits
6.2
Bits
48
54
dBc
45
51
dBc
42
dBc
50
56
dBc
48
54
dBc
43
dBc
-54
dBc
±0.5
dB
AC Performance
Signal-to-noise Ratio
Fs = 1 Gsps
Fin = 20 MHz
Fs = 1 Gsps
Fin = 500 MHz
Fs = 1 Gsps
Fin = 1 GHz
SNR
Effective Number of Bits
Fs = 1 Gsps
Fin = 20 MHz
Fs = 1 Gsps
Fin = 500 MHz
Fs = 1 Gsps
Fin = 1 GHz
ENOB
Total Harmonic Distortion (First 9 Harmonics)
Fs = 1 Gsps
Fin = 20 MHz
Fs = 1 Gsps
Fin = 500 MHz
Fs = 1 Gsps
Fin = 1 GHz
|THD|
Spurious Free Dynamic Range
Fs = 1 Gsps
Fin = 20 MHz
Fs = 1 Gsps
Fin = 500 MHz
Fs = 1 Gsps
Fin = 1 GHz
|SFDR|
Two-tone Inter-modulation Distortion (Single Channel)
FIN1 = 499 MHz , FIN2 = 501 MHz at Fs = 1 Gsps
IMD
Band flatness from DC up to 600 MHz
Phase matching using auto-calibration and FiSDA
in interlace mode (channel I and Q)
Fin = 250 MHz
Fs = 1 Gsps
dϕ
Crosstalk channel I versus channel Q
Fin = 250 MHz, Fs = 1 Gsps(2)
Cr
Notes:
-0.7
0
0.7
-55
°
dB
1. Differential input [-1 dBFS analog input level], gain setting is 0 dB, two input clock signals, no standby mode,
1:1 DMUX, ISA = -50 ps.
2. Measured on the AT84AD001TD-EB Evaluation Board.
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2153C–BDC–04/04
Table 6. AC Performances in Interlace Mode
Parameter
Symbol
Min
Typ
Max
Unit
Maximum equivalent clock frequency Fint = 2 x Fs
Where Fs = external clock frequency
Fint
2
Minimum clock frequency
Fint
20
Msps
Differential non-linearity in interlace mode
intDNL
0.25
LSB
Integral non-linearity in interlace mode
intINL
0.5
LSB
42
dBc
40
dBc
7.1
Bits
6.8
Bits
52
dBc
49
dBc
54
dBc
52
dBc
-54
dBc
Interlace Mode
Gsps
Signal-to-noise Ratio in Interlace Mode
Fint = 2 Gsps
Fin = 20 MHz
iSNR
Fint = 2 Gsps
Fin = 250 MHz
Effective Number of Bits in Interlace Mode
Fint = 2 Gsps
Fin = 20 MHz
iENOB
Fint = 2 Gsps
Fin = 250 MHz
Total Harmonic Distortion in Interlace Mode
Fint = 2 Gsps
Fin = 20 MHz
|iTHD|
Fint = 2 Gsps
Fin = 250 MHz
Spurious Free Dynamic Range in Interlace Mode
Fint = 2 Gsps
Fin = 20 MHz
Fint = 2 Gsps
Fin = 250 MHz
|iSFDR|
Two-tone Inter-modulation Distortion (Single Channel) in Interlace Mode
FIN1 = 249 MHz , FIN2 = 251 MHz at Fint = 2 Gsps
Note:
10
iIMD
One analog input on both cores, clock I samples the analog input on the rising and falling edges. The calibration
phase is necessary. The gain setting is 0 dB, one input clock I, no standby mode, 1:1 DMUX, FiSDA adjustment.
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Table 7. Switching Performances
Parameter
Symbol
Min
Typ
Max
Unit
Switching Performance and Characteristics - See “Timing Diagrams” on page 12.
Maximum operating clock frequency
Maximum operating clock frequency in BIT and
decimation modes
FS
1
Gsps
FS
(BIT, DEC)
750
Minimum clock frequency (no transparent mode)
Minimum clock frequency (with transparent mode)
FS
Msps
10
Msps
1
Ksps
Minimum clock pulse width [high]
(No transparent mode)
TC1
0.4
0.5
50
ns
Minimum clock pulse width [low]
(No transparent mode)
TC2
0.4
0.5
50
ns
Aperture delay: nominal mode with ISA & FiSDA
TA
1
ns
Aperture uncertainty
Jitter
0.4
ps (rms)
Data output delay between input clock and data
TDO
3.8
ns
Data Ready Output Delay
TDR
3
ns
TRDR
2
ns
TD2
1/2 Fs
+Tdrda
ps
Tdrda range
-560 to 420
ps
Data Ready Reset to Data Ready
Data Output Delay with Data Ready
Data Ready (CLKO) Delay Adjust (140 ps steps)
Output skew
50
100
ps
Output rise/fall time for DATA (20% - 80%)
TR/TF
300
350
500
ps
Output rise/fall time for DATA READY (20% - 80%)
TR/TF
300
350
500
ps
3 (port B)
3.5 (port A, 1:1 DMUX mode)
4 (port A, 1:2 DMUX mode)
Data pipeline delay (nominal mode)
TPD
Data pipeline delay (nominal mode) in S/H
transparent mode
DDRB recommended pulse width
Clock cycles
2.5 (port B)
3 (port A, 1:1 DMUX mode)
3.5 (port A, 1:2 DMUX mode)
1
ns
11
2153C–BDC–04/04
Timing Diagrams
Figure 4. Timing Diagram, ADC I or ADC Q, 1:2 DMUX Mode, Clock I for ADC I, Clock Q for ADC Q
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X 1 X 0 0
TA
N+3
N+1
VIN
N+2
N
CLKI or CLKQ
Pipeline delay = 4 clock cycles
DOIA[0:7]
or DOQA[0:7]
N-4
TDO
Pipeline delay = 3 clock cycles
DOIB[0:7]
or DOQB[0:7]
N
N - 2
N-3
TDO
N-1
N +1
Programmable delay
TD2
CLKOI or CLKOQ
(= CLKI/2)
CLKOI or CLKOQ
(= CLKI/4)
Figure 5. 1:1 DMUX Mode, Clock I = ADC I, Clock Q = ADC Q
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 1 X X 0 X 0 0
TA
N+3
N+1
VIN
N+2
N
CLKI or CLKQ
Pipeline delay = 3.5 clock cycles
DOIA[0:7]
or DOQA[0:7]
N -3
N -2
TDO
N - 1
N
N+1
CLKOI or CLKOQ
DOIB[0:7] and DOQB[0:7] are high impedance
12
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 6. 1:2 DMUX Mode, Clock I = ADC I, Clock I = ADC Q
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 1 X 0 0
TA
N+3
N+2
N+1
VIN
N
CLKI
TDO
Pipeline delay = 4 clock cycles
DOIA[0:7]
NI - 4
NI
NI - 2
Pipeline delay = 3 clock cycles
TDO
DOIB[0:7]
NI - 3
NI - 1
NI +1
DOQA[0:7]
NQ - 4
NQ - 2
NQ
DOQB[0:7]
NQ - 3
NQ - 1
NQ +1
TD2
CLKOI
(= CLKI/2)
CLKOI
(= CLKI/4)
CLKOQ is high impedance
13
2153C–BDC–04/04
Figure 7. 1:1 DMUX Mode, Clock I = ADC I, Clock I = ADC Q
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 0 X 0 0
TA
N+3
N+1
VIN
N+2
N
CLKI
TDO
Pipeline delay = 3.5 clock cycles
DOIA[0:7]
N -3
N -2
N - 1
N
N+1
DOQA[0:7]
N -3
N -2
N - 1
N
N+1
CLKOI
DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance
14
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 8. 1:2 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q
Address: D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 1 X 0 0
N+6
N+4
N+2
TA
N+5
VIN
N
N+1
N+3
CLKI
CLKIN
TDO
Pipeline delay = 4 clock cycles
DOQA[0:7]
N -8
Pipeline delay = 3 clock cycles
DOQB[0:7]
N
N- 4
N -6
TDO
N -2
Pipeline delay = 3.5 clock cycles
N+2
TDO
DOIA[0:7]
N -7
N -3
N+1
DOIB[0:7]
N -5
N -1
N+3
TD2
CLKOI
(= CLKI/2)
CLKOI
(= CLKI/4)
CLKOQ is high impedance
15
2153C–BDC–04/04
Figure 9. 1:1 DMUX Mode, Clock I = ADC I, Clock IN = ADC Q
Address: D7 D6 D5 D4 D3 D2 D1 D0
0 X X X 0 X 0 0
N+6
N+4
N+2
TA
N+5
VIN
N
N+3
N+1
CLKI
CLKIN
TDO
Pipeline delay = 3.5 clock cycles
DOQA[0:7]
N -6
N -4
N -5
N+2
N +1
N+3
TDO
Pipeline delay = 3 clock cycles
DOIA[0:7]
N
N - 2
N -3
N - 1
CLKOI
(= CLKI/2)
DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance
Figure 10. 1:1 DMUX Mode, Decimation Mode Test (1:16 Factor)
Address: D7 D6 D5 D4 D3 D2 D1 D0
1 0 X X 0 X 0 0
N - 16
VIN
N
N + 16
N + 32
16 clock cycles
CLKI
DOIA[0:7]
N - 16
N
N + 16
N + 32
N + 48
DOQA[0:7]
N - 16
N
N + 16
N + 32
N + 48
CLKOI
DOIB[0:7] and DOQB[0:7] are high impedance
CLKOQ is high impedance
Notes:
16
1. The maximum clock input frequency in decimation mode is 750 Msps.
2. Frequency(CLKOI) = Frequency(Data) = Frequency(CLKI)/16.
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 11. Data Ready Reset
500 ps
CLKI or
CLKQ
500 ps
1 ns min
DDRB
FORBIDDEN
FORBIDDEN
ALLOWED
ALLOWED
Figure 12. Data Ready Reset 1:1 DMUX Mode
TA
N
VIN
N+1
Clock in
Reset
CLKI or
CLKQ
Pipeline Delay + TDO
DOIA[0:7] or
DOQA[0:7]
N
TDR
CLKOI or
CLKOQ
TDR
2 ns
DDRB
1 ns min
Note:
The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the reset
occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low) and then
only, remains in reset state (frozen to a low level in 1:1 DMUX mode). The next falling edge of the input clock after reset makes
the output clock return to normal mode (after TDR).
17
2153C–BDC–04/04
Figure 13. Data Ready Reset 1:2 DMUX Mode
TA
N
VIN
N+1
Clock in
Reset
CLKI or
CLKQ
Pipeline Delay + TDO
DOIA[0:7] or
DOQA[0:7]
N
DOIB[0:7] or
DOQB[0:7]
N+1
TDR
TDR
CLKOI or CLKOQ
(= CLKI/2)
TDR + 2 cycles
CLKOI or CLKOQ
(= CLKI/4)
TDR + 2 cycles
2 ns
DDRB
1 ns min
Notes:
1. In 1:2 DMUX, Fs/2 mode:
The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the
reset occurs when it is low, it goes high only when its half cycle is complete; if the reset occurs when it is high, it remains
high) and then only, remains in reset state (frozen to a high level in 1:2 DMUX Fs/2 mode). The next rising edge of the input
clock after reset makes the output clock return to normal mode (after TDR).
2. In 1:2 DMUX, Fs/4 mode:
The Data Ready Reset is taken into account only 2 ns after it is asserted. The output clock first completes its cycle (if the
reset occurs when it is high, it goes low only when its half cycle is complete; if the reset occurs when it is low, it remains low)
and then only, remains in reset state (frozen to a low level in 1:2 DMUX Fs/4 mode). The next rising edge of the input clock
after reset makes the output clock return to normal mode (after TDR).
18
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Functions Description
Table 8. Description of Functions
Name
Function
VCCA
Positive analog power supply
VCCD
Positive digital power supply
VCCO
Positive output power supply
GNDA
Analog ground
GNDD
Digital ground
GNDO
Output ground
VINI, VINIB
Differential analog inputs I
VINQ, VINQB
Differential analog inputs Q
CLKOI, CLKOIN, CLKOQ,
CLKOQN
Differential output data ready I
and Q
VCCA = 3.3V
VCCD = 3.3V
VCCO = 2.25V
VINI
32
D0AI0
D0AI0N
D0BI0
D0BI0N
DOAI7
DOAI7N
DOBI7
DOBI7N
32
D0AQ0
D0AQ0
DOAQ7
DOAQ7
VINIB
CLKI, CLKIN, CLKQ, CLKQN
Differential clock inputs I and Q
DDRB, DDRBN
Synchronous data ready reset
I and Q
Mode
Bit selection for 3-wire bus or
nominal setting
Clk
Input clock for 3-wire bus
interface
Data
Input data for 3-wire bus
Ldn
Beginning and end of register
line for 3-wire bus interface
<D0AI0:DOAI7>
<D0AI0N:DOAI7N>
<D0BI0:DOBI7>
<D0BI0N:DOBI7N>
Differential output data port
channel I
<D0AQ0:DOAQ7>
<D0AQ0N:DOAQ7N>
<D0BQ0:DOBQ7>
<D0BQ0N:DOBQ7N>
Differential output data port
channel Q
VINQ
DOBQ0
DOQBQ7
DOBQ0N DOQBQ7N
VINQB
AT84AD001B
CLKI
4
DOIRI, DOIRIN
DOIRQ, DOIRQN
CLKQ
4
CLOCKOI, CLOCKOIB
CLOCKOQ, CLOCKOQB
CLKQB
2
VtestI
VtestQ
CLKIB
Vdiode
GNDA
GNDD
GNDO
mode
clk
data ldn
DOIRI, DOIRIN DOIRQ,
DOIRQN
Differential output IN range
data I and Q
VtestQ
Test voltage output for ADC Q
(to be left open)
VtestI
Test voltage output for ADC I
(to be left open)
Cal
Output bit status internal
calibration
Vdiode
Test diode voltage for Tj
measurement
19
2153C–BDC–04/04
Digital Output Coding (Nominal Settings)
Table 9. Digital Output Coding (Nominal Setting)
Differential
Analog Input
Voltage Level
Digital Output
I or Q (Binary Coding)
Out-of-range Bit
> 250 mV
> Positive full-scale + 1/2 LSB
11111111
1
250 mV
248 mV
Positive full-scale + 1/2 LSB
Positive full-scale - 1/2 LSB
11111111
11111110
0
0
1 mV
-1 mV
Bipolar zero + 1/2 LSB
Bipolar zero - 1/2 LSB
10000000
01111111
0
0
-248 mV
-250 mV
Negative full-scale + 1/2 LSB
Negative full-scale - 1/2 LSB
00000001
00000000
0
0
< -250 mV
< Negative full-scale - 1/2 LSB
00000000
1
Pin Description
Table 10. AT84AD001B LQFP 144 Pin Description
Symbol
Pin number
Function
GNDA, GNDD, GNDO
10, 12, 22, 24, 36, 38, 40, 42, 44, 46, 51,
54, 59, 61, 63, 65, 67, 69, 85, 87, 97, 99,
109, 111, 130, 142, 144
Ground pins. To be connected to external
ground plane
VCCA
41, 43, 45, 60, 62, 64
Analog positive supply: 3.3V typical
VCCD
9, 21, 37, 39, 66, 68, 88, 100, 112, 123,
141
3.3V digital supply
VCCO
11, 23, 86, 98, 110, 143
2.25V output and 3-wire serial interface
supply
VINI
57, 58
In-phase (+) analog input signal of the
sample & hold differential preamplifier
channel I
VINIB
55, 56
Inverted phase (-) of analog input signal
(VINI)
VINQ
47, 48
In-phase (+) analog input signal of the
sample & hold differential preamplifier
channel Q
VINQB
49, 50
Inverted phase (-) of analog input signal
(VINQ)
CLKI
124
In-phase (+) clock input signal
CLKIN
125
Inverted phase (-) clock input signal
(CLKI)
CLKQ
129
In-phase (+) clock input signal
20
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Table 10. AT84AD001B LQFP 144 Pin Description (Continued)
Symbol
Pin number
Function
CLKQN
128
Inverted phase (-) clock input signal
(CLKQ)
DDRB
126
Synchronous data ready reset I and Q
DDRBN
127
Inverted phase (-) of input signal (DDRB)
DOAI0, DOAI1, DOAI2, DOAI3, DOAI4,
DOAI5, DOAI6, DOAI7
117, 113, 105, 101, 93, 89, 81, 77
In-phase (+) digital outputs first phase
demultiplexer (channel I) DOAI0 is the
LSB. D0AI7 is the MSB
DOAI0N, DOAI1N, DOAI2N, DOAI3N,
DOAI4N, DOAI5N, DOAI6N, DOAI7N,
118, 114, 106, 102, 94, 90, 82, 78
Inverted phase (-) digital outputs first
phase demultiplexer (channel I) DOAI0N
is the LSB. D0AI7N is the MSB
DOBI0, DOBI1, DOBI2, DOBI3, DOBI4,
DOBI5, DOBI6, DOBI7
119, 115, 107, 103, 95, 91, 83, 79
In-phase (+) digital outputs second phase
demultiplexer (channel I) DOBI0 is the
LSB. D0BI7 is the MSB
DOBI0N, DOBI1N, DOBI2N, DOBI3N,
DOBI4N, DOBI5N, DOBI6N, DOBI7N
120, 116, 108, 104, 96, 92, 84, 80
Inverted phase (-) digital outputs second
phase demultiplexer (channel I) DOBI0N
is the LSB. D0BI7N is the MSB
DOAQ0, DOAQ1, DOAQ2, DOAQ3,
DOAQ4, DOAQ5, DOAQ6, DOAQ7
136, 140, 4, 8, 16, 20, 28, 32
In-phase (+) digital outputs first phase
demultiplexer (channel Q) DOAI0 is the
LSB. D0AQ7 is the MSB
DOAQ0N, DOAQ1N, DOAQ2N, DOAQ3N,
DOAQ4N, DOAQ5N, DOAQ6N, DOAQ7N
135, 139, 3, 7, 15, 19, 27, 31
Inverted phase (-) digital outputs first
phase demultiplexer (channel Q) DOAI0N
is the LSB. D0AQ7N is the MSB
DOBQ0, DOBQ1, DOBQ2, DOBQ3,
DOBQ4, DOBQ5, DOBQ6, DOBQ7
134, 138, 2, 6, 14, 18, 26, 30
In-phase (+) digital outputs second phase
demultiplexer (channel Q) DOBQ0 is the
LSB. D0BQ7 is the MSB
DOBQ0N, DOBQ1N, DOBQ2N,
DOBQ3N, DOBQ4N, DOBQ5N,
DOBQ6N, DOBQ7N
133, 137, 1 ,5, 13, 17, 25, 29
Inverted phase (-) digital outputs second
phase demultiplexer (channel Q)
DOBQ0N is the LSB. D0BQ7N is the MSB
DOIRI
75
In-phase (+) out-of-range bit input
(I phase) combined demultiplexer
out-of-range is high on the leading edge of
code 0 and code 256
DOIRIN
76
Inverted phase of output signal DOIRI
DOIRQ
34
In-phase (+) out-of-range bit input
(Q phase) combined demultiplexer
out-of-range is high on the leading edge of
code 0 and code 256
DOIRQN
33
Inverted phase of output signal DOIRQ
MODE
74
Bit selection for 3-wire bus interface or
nominal setting
CLK
73
Input clock for 3-wire bus interface
DATA
72
Input data for 3-wire bus
LND
71
Beginning and end of register line for
3- wire bus interface
CLKOI
121
Output clock in-phase (+) channel I
21
2153C–BDC–04/04
Table 10. AT84AD001B LQFP 144 Pin Description (Continued)
Symbol
Pin number
Function
CLKOIN
122
Inverted phase (-) output clock channel I
CLKOQ
132
Output clock in-phase (+) channel Q,
1/2 input clock frequency
CLKOQN
131
Inverted phase (-) output clock channel Q
VtestQ, VtestI
52, 53
Pins for internal test (to be left open)
Cal
70
Calibration output bit status
Vdiode
35
Positive node of diode used for die
junction temperature measurements
Figure 14. AT84AD001B Pinout (Top View)
LQFP 144
20 by 20 by 1.4 mm
Atmel - Dual 8-bit
22
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Typical Characterization Results
Nominal conditions (unless otherwise specified):
Typical Full Power Input
Bandwidth
•
VCCA = 3.3V; VCCD = 3.3V; VCCO = 2.25V
•
VINI - VINB or VINQ to VINQB = 500 mVpp full-scale differential input
•
LVDS digital outputs (100Ω)
•
TA (typical) = 25° C
•
Full temperature range: 0°C < TA < 70°C (commercial grade) or -40°C
< TA < 85° C (industrial grade)
•
Fs = 500 Msps
•
Pclock = 0 dBm
•
Pin = -1 dBFS
•
Gain flatness (±0.5 dB) from DC to > 500 MHz
•
Full power input bandwidth at -3 dB > 1.5 GHz
Figure 15. Full Power Input Bandwidth
0
-1
-2
-3 dB Bandwidth
-3
dBFS
-4
-5
-6
-7
-8
-9
-10
-11
100
300
500
700
900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
Fin (MHz)
23
2153C–BDC–04/04
Typical Crosstalk
Figure 16. Crosstalk (Fs = 500 Msps)
80
70
60
dBc
50
40
30
20
10
0
0
100
200
300
400
500
600
700
800
900
1000
Fin (MHz)
Note:
Typical DC, INL and DNL
Patterns
Measured on the AT84AD001TD-EB Evaluation Board.
1:2 DMUX mode, Fs/4 DR type
Figure 17. Typical INL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input)
0,6
0,4
INL (Lsb)
0,2
0
-0,2
-0,4
-0,6
1
16
31
46
61
76
91 106 121 136 151 166 181 196 211 226 241 256
Codes
24
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 18. Typical DNL (Fs = 50 Msps, Fin = 1 MHz, Saturated Input)
0,3
0,2
DNL (Lsb)
0,1
0
-0,1
-0,2
-0,3
1
16
31
46
61
76
91 106 121 136 151 166 181 196 211 226 241 256
Codes
Typical Step Response
Figure 19. Step Response
250
Codes
200
150
100
50
0
2.4E-12 1.3E-09 2.5E-09 3.8E-09 5.0E-09 6.3E-09 7.5E-09 8.8E-09
Time (s)
Channel IA
•
Fs = 1 Gsps
•
Pclock = 0 dBm
•
Fin = 100 MHz
•
Pin = -1 dBFS
Channel QA
25
2153C–BDC–04/04
Figure 20. Step Response (Zoom)
250
200
Codes
90%
150
Tr = 160 ps
100
50
10%
0
4.9E-09
6.1E-09
Channel IA
•
Fs = 1 Gsps
•
Pclock = 0 dBm
•
Fin = 500 MHz
•
Pin = -1 dBFS
7.4E-09
Time (s)
Channel QA
Figure 21. Step Response
250
Codes
200
150
100
50
0
4.9E-13 2.5E-10 5.0E-10 7.5E-10 1.0E-09 1.3E-09 1.5E-09 1.8E-09
Time (s)
Channel IA
26
Channel QA
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 22. Step Response (Zoom)
250
90%
Codes
200
150
Tr = 170 ps
100
50
10%
0
9.8E-10
1.2E-09
1.5E-09
Channel IA
Typical Dynamic
Performances Versus
Sampling Frequency
Time (s)
Channel QA
Figure 23. ENOB Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)
7.6
7.4
ENOB (Bit)
7.2
7.0
6.8
6.6
6.4
6.2
6.0
100
200
300
400
500
600
700
800
900
1000
1100
Fs (Msps)
Figure 24. SFDR Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)
-50
SFDR (dBc)
-53
-56
-59
-62
-65
100
300
500
700
900
1100
Fs (Msps)
27
2153C–BDC–04/04
Figure 25. THD Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)
-48
-50
THD (dBc)
-52
-54
-56
-58
-60
100
300
500
700
900
1100
Fs (Msps)
Figure 26. SNR Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)
45
SNR (dBc)
44
43
42
41
40
100
300
500
700
900
1100
Fs (Msps)
Typical Dynamic
Performances Versus
Input Frequency
Figure 27. ENOB Versus Input Frequency (Fs = 1 Gsps)
8.0
7.5
ENOB (Bit)
7.0
6.5
6.0
5.5
5.0
0
200
400
600
800
1000
Fin (MHz)
28
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 28. SFDR Versus Input Frequency (Fs = 1 Gsps)
-35
-40
SFDR (dBc)
-45
-50
-55
-60
-65
0
200
400
600
800
1000
800
1000
800
1000
Fin (MHz)
Figure 29. THD Versus Input Frequency (Fs = 1 Gsps)
-35
-40
THD (dBc)
-45
-50
-55
-60
-65
0
200
400
600
Fin (MHz)
Figure 30. SNR Versus Input Frequency (Fs = 1 Gsps)
50
48
46
SNR (dBc)
44
42
40
38
36
34
32
30
0
200
400
600
Fin (MHz)
29
2153C–BDC–04/04
Typical Reconstructed
Signals and Signal
Spectrum
Figure 31. Fs = 1 Gsps and Fin = 20 MHz (1:2 DMUX, Fs/2 DR Type, FiSDA = -15 ps, ISA = -50 ps)
20
250
Ch IA
Ch QA
0
200
150
-40
dBc
Codes
-20
-60
100
-80
50
Ch IA
Ch QA
-100
-120
0
1
513
1025
1537
2049
2561
3073
0
3585
31
62
93
125
156
187
218
249
Fout/2
F (Msps)
Samples
Figure 32. Fs = 1 Gsps and Fin = 500 MHz (1:2 DMUX, Fs/2 DR Type, FiSDA = -15 ps, ISA = -50 ps)
20
250
Ch IA
Ch QA
0
200
-40
dBc
Codes
-20
150
-60
100
-80
50
Ch IA
Ch QA
0
-100
-120
1
513
1025
1537
2049
2561
3073
3585
0
31
62
93
Samples
125
156
187
218
249
Fout/2
F (Msps)
Figure 33. Fs = 1 Gsps and Fin = 1 GHz (1:2 DMUX, Fs/2 DR Type, FiSDA = -15 ps, ISA = -50 ps)
20
250
Ch IA
Ch QA
0
200
150
dBc
Codes
-20
-40
-60
100
-80
50
-100
Ch IA
Ch QA
-120
0
1
513
1025
1537
2049
Samples
Note:
30
2561
3073
3585
0
31
62
93
125
F (Msps)
156
187
218
249
Fout/2
The spectra are given with respect to the output clock frequency observed by the acquisition system (Figures 31 to 33).
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 34. Fs = 1 Gsps and Fin = 20 MHz (Interleaving Mode Fint = 2 Gsps, Fs/4 DR Type, FiSDA = -15 ps, ISA = -50 ps)
20
250
0
200
dBc
Codes
-20
150
-40
-60
100
-80
50
-100
-120
0
1
2048
4095
6142
8189
0
10236 12283 14330 16377
125
250
375
500
624
749
874
Fs (MHz)
Samples
999
Fs/2
Figure 35. Fs = 1 Gsps and Fin = 250 MHz (Interleaving Mode Fint = 2 Gsps, Fs/4 DR Type, FiSDA = -15 ps, ISA = -50 ps)
20
250
0
200
150
dBc
Codes
-20
-40
-60
100
-80
50
-100
0
-120
1
2048
4095
6142
8189
Samples
10236 12283 14330 16377
0
125
250
375
500
Fs (MHz)
624
749
874
999
Fs/2
31
2153C–BDC–04/04
Typical Performance
Sensitivity Versus Power
Supplies and
Temperature
Figure 36. ENOB Versus VCCA = VCCD (Fs = 1 Gsps, Fin = 500 MHz, 1:2 DMUX,
Fs/4 DR Type, ISA = -50 ps)
7.4
7.2
ENOB (Bit)
7.0
6.8
6.6
6.4
6.2
6.0
3.1
3.15
3.2
3.25
3.3
3.35
3.4
3.45
3.5
Vcca = Vccd (V)
Figure 37. SFDR Versus VCCA = VCCD (Fs = 1 Gsps, Fin = 500 MHz, 1:2 DMUX,
Fs/4 DR Type, ISA = -50 ps)
-40
SFDR (dBc)
-45
-50
-55
-60
3.1
3.15
3.2
3.25
3.3
3.35
3.4
3.45
3.5
Vcca = Vccd (V)
32
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 38. THD Versus VCCA = VCCD (Fs = 1 Gsps, Fin = 500 MHz, 1:2 DMUX,
Fs/4 DR Type, ISA = -50 ps)
-40
THD (dBc)
-45
-50
-55
-60
3.1
3.15
3.2
3.25
3.3
3.35
3.4
3.45
3.5
Vcca = Vccd (V)
Figure 39. SNR Versus VCCA = VCCD (Fs = 1 Gsps, Fin = 500 MHz, 1:2 DMUX,
Fs/4 DR Type, ISA = -50 ps)
45.0
SNR (dBc)
44.0
43.0
42.0
41.0
40.0
3.1
3.15
3.2
3.25
3.3
3.35
3.4
3.45
3.5
Vcca = Vccd (V)
33
2153C–BDC–04/04
Figure 40. ENOB Versus Junction Temperature (Fs = 1 Gsps, 1:2 DMUX, Fs/4 DR
Type, ISA = -50 ps)
8.0
7.5
1 Gsps 20 MHz
ENOB (Bit)
7.0
1 Gsps 502 MHz
6.5
6.0
1 Gsps 998 MHz
5.5
5.0
-50
-25
0
25
Tj (˚C)
50
75
100
Figure 41. SFDR Versus Junction Temperature (Fs = 1 Gsps, 1:2 DMUX, Fs/4 DR
Type, ISA = -50 ps)
-35
1 Gsps 998 MHz
-40
SFDR (dBc)
-45
1 Gsps 502 MHz
-50
-55
1 Gsps 20 MHz
-60
-65
-50
34
-25
0
25
Tj (˚C)
50
75
100
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 42. THD Versus Junction Temperature (Fs = 1 Gsps, 1:2 DMUX, Fs/4 DR
Type, ISA = -50 ps)
-35
1 Gsps 998 MHz
THD (dBc)
-40
-45
1 Gsps 502 MHz
-50
1 Gsps 20 MHz
-55
-60
-50
-25
0
25
50
75
100
Tj (˚C)
Figure 43. SNR Versus Junction Temperature (Fs = 1 Gsps, 1:2 DMUX, Fs/4 DR
Type, ISA = -50 ps)
45.0
SNR (dBc)
44.0
1 Gsps 20 MHz
43.0
1 Gsps 502 MHz
42.0
41.0
1 Gsps 998 MHz
40.0
-50
-25
0
25
Tj (˚C)
50
75
100
35
2153C–BDC–04/04
Test and Control Features
3-wire Serial Interface
Control Setting
Table 11. 3-wire Serial Interface Control Settings
Mode
Characteristics
Mode = 1 (2.25V)
3-wire serial bus interface activated
Mode = 0 (0V)
3-wire serial bus interface deactivated
Nominal setting:
Dual channel I and Q activated
One clock I
0 dB gain
DMUX mode 1:1
DRDA I & Q = 0 ps
ISA I & Q = 0 ps
FiSDA Q = 0 ps
Binary output
Decimation test mode OFF
Calibration setting OFF
Data Ready = Fs /2
36
AT84AD001B
2153C–BDC–04/04
AT84AD001B
3-wire Serial Interface and
Data Description
The 3-wire bus is activated with the control bit mode set to 1. The length of the word is
19 bits: 16 for the data and 3 for the address. The maximum clock frequency is
50 MHz.
Table 12. 3-wire Serial Interface Address Setting Description
Address
Setting
000
Standby
Gray/binary mode
1:1 or 1:2 DMUX mode
Analog input MUX
Clock selection
Auto-calibration
Decimation test mode
Data Ready Delay Adjust
001
Analog gain adjustment
Data7 to Data0: gain channel I
Data15 to Data8: gain channel Q
Code 00000000: -1.5 dB
Code 10000000: 0 dB
Code 11111111: 1.5 dB
Steps: 0.011 dB
010
Offset compensation
Data7 to Data0: offset channel I
Data15 to Data8: offset channel Q
Data7 and Data15: sign bits
Code 11111111b: 31.75 LSB
Code 10000000b: 0 LSB
Code 00000000b: 0 LSB
Code 01111111b: -31.75 LSB
Steps: 0.25 LSB
Maximum correction: ±31.75 LSB
011
100
Gain compensation
Data6 to Data0: channel I/Q (Q is matched to I)
Code 11111111b: -0.315 dB
Code 10000000b: 0 dB
Code 0000000b: 0 dB
Code 0111111b: 0.315 dB
Steps: 0.005 dB
Data6: sign bit
Internal Settling Adjustment (ISA)
Data2 to Data0: channel I
Data5 to Data3: channel Q
Data15 to Data6: 1000010000
37
2153C–BDC–04/04
Table 12. 3-wire Serial Interface Address Setting Description (Continued)
Address
101
110
111
Notes:
38
Setting
Testability
Data3 to Data0 = 0000
Mode S/H transparent
OFF: Data4 = 0
ON: Data4 = 1
Data7 = 0
Data8 = 0
Built-In Test (BIT)
Data0 = 0
BIT Inactive
Data0 = 1
BIT Active
Data1 = 0
Static BIT
Data1 = 1
Dynamic BIT
If Data1 = 1, then Ports BI & BQ = Rising Ramp
Ports AI & AQ = Decreasing Ramp
If Data1 = 0, then Data2 to Data9 = Static Data for BIT
Ports BI & BQ = Data2 to Data9
Ports AI & AQ = NOT (Data2 to Data9)
Data Ready Delay Adjust (DRDA)
Data2 to Data0: clock I
Data5 to Data3: clock Q
Steps: 140 ps
000: -560 ps
100: 0 ps
111: 420 ps
Fine Sampling Delay Adjustment (FiSDA) on channel Q
Data10 to Data6: channel Q
Steps: 5 ps
Data4: sign bit
Code 11111: -75 ps
Code 10000: 0 ps
Code 00000: 0 ps
Code 01111: 75 ps
1. The Internal Settling Adjustment could change independently of the two analog sampling times (TA channels I and Q) of the
sample/hold (with a fixed digital sampling time) with steps of ±50 ps:
Nominal mode will be given by Data2…Data0 = 100 or Data5…Data3 = 100.
Data5…Data3 = 000 or Data2…Data0 = 000: sampling time is -200 ps compared to nominal.
Data2…Data0 = 111 or Data5…Data3 = 111: sampling time is 150 ps compared to nominal.
We recommend setting the ISA to -50 ps to optimize the ADC’s dynamic performances.
2. The Fine Sampling Delay Adjustment enables you to change the sampling time (steps of ±5 ps) on channel Q more precisely, particularly in the interleaved mode.
3. A Built-In Test (BIT) function is available to rapidly test the device’s I/O by either applying a defined static pattern to the dual
ADC or by generating a dynamic ramp at the output of the dual ADC. This function is controlled via the 3-wire bus interface
at the address 110. The maximum clock frequency in dynamic BIT mode is 750 Msps.
Please refer to “Built-In Test (BIT)” on page 43 for more information about this function.
4. The decimation mode enables you to lower the output bit rate (including the output clock rate) by a factor of 16, while the
internal clock frequency remains unchanged. The maximum clock frequency in decimation mode is 750 Msps.
5. The “S/H transparent” mode (address 101, Data4) enables bypassing of the ADC’s track/hold. This function optimizes the
ADC’s performances at very low input frequencies (Fin < 50 MHz).
6. In the Gray mode, when the input signal is overflow (that is, the differential analog input is greater than 250 mV), the output
data must be corrected using the output DOIR:
If DOIR = 1: Data7 unchanged
Data6 = 0, Data5 = 0, Data4 = 0, Data3 = 0, Data2 = 0, Data1 = 0, Data0 = 0.
In 1:2 DMUX mode, only one out-of-range bit is provided for both A and B ports.
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Table 13. 3-wire Serial Interface Data Setting Description
Setting for Address:
000
D15
D14
D13
D12
D11
D10
D9(1)
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
1
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
0
No standby mode
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
0
Binary output mode
X
X
X
X
X
X
0
X
X
X
X
X
X
1
X
X
Gray output mode
X
X
X
X
X
X
0
X
X
X
X
X
X
0
X
X
DMUX 1:2 mode
X
X
X
X
X
X
0
X
X
X
X
X
1
X
X
X
DMUX 1:1 mode
X
X
X
X
X
X
0
X
X
X
X
X
0
X
X
X
Analog selection mode
Input I →ADC I
Input Q →ADC Q
X
X
X
X
X
X
0
X
X
X
1
1
X
X
X
X
Analog selection mode
Input I →ADC I
Input I →ADC Q
X
X
X
X
X
X
0
X
X
X
1
0
X
X
X
X
Analog selection mode
Input Q →ADC I
Input Q →ADC Q
X
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
Clock Selection mode
CLKI →ADC I
CLKQ →ADC Q
X
X
X
X
X
X
0
X
1
1
X
X
X
X
X
X
Clock selection mode
CLKI →ADC I
CLKI →ADC Q
X
X
X
X
X
X
0
X
1
0
X
X
X
X
X
X
Clock selection mode
CLKI →ADC I
CLKIN →ADC Q
X
X
X
X
X
X
0
X
0
X
X
X
X
X
X
X
Decimation OFF mode
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
X
Decimation ON mode
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
Keep last calibration
calculated value(4)
No calibration phase
X
X
X
X
0
1
0
X
X
X
X
X
X
X
X
X
No calibration phase(5)
No calibration value
X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
X
Start a new calibration
phase
X
X
X
X
1
1
0
X
X
X
X
X
X
X
X
X
Full standby mode
Standby channel I
(2)
Standby channel Q
(3)
39
2153C–BDC–04/04
Table 13. 3-wire Serial Interface Data Setting Description (Continued)
Setting for Address:
000
D15
D14
D13
D12
D11
D10
D9(1)
D8
D7
D6
D5
D4
D3
D2
D1
D0
Control wait bit
calibration(6)
X
X
a
b
X
X
0
X
X
X
X
X
X
X
X
X
In 1:2 DMUX
FDataReady
I & Q = Fs/2
X
0
X
X
X
X
0
X
X
X
X
X
X
X
X
X
In 1:2 DMUX
FDataReady
I & Q = Fs/4
X
1
X
X
X
X
0
X
X
X
X
X
X
X
X
X
Notes:
1.
2.
3.
4.
D9 must be set to “0”
Mode standby channel I: use analog input I Vini, Vinib and Clocki.
Mode standby channel Q: use analog input Q Vinq, Vinqb and Clockq.
Keep last calibration calculated value - no calibration phase: D11 = 0 and D10 = 1. No new calibration is required. The values taken into account for the gain and offset are either from the last calibration phase or are default values (reset values).
5. No calibration phase - no calibration value: D11 = 0 and D10 = 0. No new calibration phase is required. The gain and offset
compensation functions can be accessed externally by writing in the registers at address 010 for the offset compensation
and at address 011 for the gain compensation.
6. The control wait bit gives the possibility to change the internal setting for the auto-calibration phase:
For high clock rates (> 500 Msps) use a = b = 1.
For clock rates > 250 Msps and < 500 Msps use a = 1 and b = 0.
For clock rates > 125 Msps and < 250 Msps use a = 0 and b = 1.
For low clock rates < 125 Msps use a = 0 and b = 0.
3-wire Serial Interface Timing
Description
The 3-wire serial interface is a synchronous write-only serial interface made of three
wires:
•
sclk: serial clock input
•
sldn: serial load enable input
•
sdata: serial data input
The 3-wire serial interface gives write-only access to as many as 8 different internal registers of up to 16 bits each. The input format is always fixed with 3 bits of register
address followed by 16 bits of data. The data and address are entered with the Most
Significant Bit (MSB) first.
The write procedure is fully synchronous with the rising clock edge of “sclk” and
described in the write chronogram (Figure 44 on page 41).
40
•
“sldn” and “sdata” are sampled on each rising clock edge of “sclk” (clock cycle).
•
“sldn” must be set to 1 when no write procedure is performed.
•
A minimum of one rising clock edge (clock cycle) with “sldn” at 1 is required for a
correct start of the write procedure.
•
A write starts on the first clock cycle with “sldn” at 0. “sldn” must stay at 0 during the
complete write procedure.
•
During the first 3 clock cycles with “sldn” at 0, 3 bits of the register address from
MSB (a[2]) to LSB (a[0]) are entered.
•
During the next 16 clock cycles with “sldn” at 0, 16 bits of data from MSB (d[15]) to
LSB (d[0]) are entered.
•
An additional clock cycle with “sldn” at 0 is required for parallel transfer of the serial
data d[15:0] into the addressed register with address a[2:0]. This yields 20 clock
cycles with “sldn” at 0 for a normal write procedure.
AT84AD001B
2153C–BDC–04/04
AT84AD001B
•
A minimum of one clock cycle with “sldn” returned at 1 is requested to close the
write procedure and make the interface ready for a new write procedure. Any clock
cycle where “sldn” is at 1 before the write procedure is completed interrupts this
procedure and no further data transfer to the internal registers is performed.
•
Additional clock cycles with “sldn” at 0 after the parallel data transfer to the register
(done at the 20th consecutive clock cycle with “sldn” at 0) do not affect the write
procedure and are ignored.
It is possible to have only one clock cycle with “sldn” at 1 between two following write
procedures.
•
16 bits of data must always be entered even if the internal addressed register has
less than 16 bits. Unused bits (usually MSBs) are ignored. Bit signification and bit
positions for the internal registers are detailed in Table 12 on page 37.
To reset the registers, the Pin mode can be used as a reset pin for chip initialization,
even when the 3-wire serial interface is used.
Figure 44. Write Chronogram
Mode
1
2
3
4
a[1]
a[0]
d[15]
5
13
14
15
16
17
18
19
d[1]
d[0]
20
sclk
sldn
sdata
Internal register
value
a[2]
d[8]
d[7]
d[6]
d[5]
d[4]
d[3]
d[2]
New d
Reset setting
Reset
Write procedure
Figure 45. Timing Definition
Twlmode
Mode
Tsclk
Twsclk
Tdmode
Tdmode
sclk
Tssldn
Thsldn
Tssdata
Thsdata
sldn
sdata
41
2153C–BDC–04/04
Table 14. Timing Description
Value
Name
Parameter
Unit
Min
Typ
Max
Tsclk
Sclk period
20
ns
Twsclk
High or low time of sclk
5
ns
Tssldn
Setup time of sldn before rising edge of sclk
4
ns
Thsldn
Hold time of sldn after rising edge of sclk
2
ns
Tssdata
Setup time of sdata before rising edge of sclk
4
ns
Thsdata
Hold time of sdata after rising edge of sclk
2
ns
Twlmode
Minimum low pulse width of mode
5
ns
Tdmode
Minimum delay between an edge of mode and the
rising edge of sclk
10
ns
Calibration Description
The AT84AD001B offers the possibility of reducing offset and gain matching between
the two ADC cores. An internal digital calibration may start right after the 3-wire serial
interface has been loaded (using data D12 of the 3-wire serial interface with address
000).
The beginning of calibration disables the two ADCs and a standard data acquisition is
performed. The output bit CAL goes to a high level during the entire calibration phase.
When this bit returns to a low level, the two ADCs are calibrated with offset and gain and
can be used again for a standard data acquisition.
If only one channel is selected (I or Q) the offset calibration duration is divided by two
and no gain calibration between the two channels is necessary.
Figure 46. Internal Timing Calibration
3-wire Serial Interface
LDN
CAL
Tcal
The Tcal duration is a multiple of the clock frequency ClockI (master clock). Even if a
dual clock scheme is used during calibration, ClockQ will not be used.
The control wait bits (D13 and D14) give the possibility of changing the calibration’s setting depending on the clock’s frequency:
42
•
For high clock rates (> 500 Msps) use a = b = 1, Tcal = 10112 clock I periods.
•
For clock rates > 250 Msps and < 500 Msps use a = 1, b = 0, Tcal = 6016 clock I
periods.
•
For clock rates > 125 Msps and < 250 Msps use a = 0, b = 1 ,Tcal = 3968 clock I
periods.
•
For low clock rates (< 125 Msps) use a = 0, b = 0 , Tcal = 2944 clock I periods.
AT84AD001B
2153C–BDC–04/04
AT84AD001B
The calibration phase is necessary when using the AT84AD001B in interlace mode,
where one analog input is sampled at both ADC cores on the common input clock’s rising and falling edges. This operation is equivalent to converting the analog signal at
twice the clock frequency
Table 15. Matching Between Channels
Value
Parameter
Min
Gain error (single channel I or Q) without calibration
Gain error (single channel I or Q) with calibration
-0.5
0
-0.5
0
Unit
LSB
0.5
0
Mean offset code without calibration (single channel I or Q)
Mean offset code with calibration (single channel I or Q)
Max
0
Offset error (single channel I or Q) without calibration
Offset error (single channel I or Q) with calibration
Typ
LSB
LSB
0.5
LSB
127.5
127
127.5
128
During the ADC’s auto-calibration phase, the dual ADC is set with the following:
•
Decimation mode ON
•
1:1 DMUX mode
•
Binary mode
Any external action applied to any signal of the ADC’s registers is inhibited during the
calibration phase.
Gain and Offset
Compensation Functions
It is also possible for the user to have external access to the ADC’s gain and offset compensation functions:
•
Offset compensation between I and Q channels (at address 010)
•
Gain compensation between I and Q channels (at address 011)
To obtain manual access to these two functions, which are used to set the offset to middle code 127.5 and to match the gain of channel Q with that of channel I (if only one
channel is used, the gain compensation does not apply), it is necessary to set the ADC
to “manual” mode by writing 0 at bits D11 and D10 of address 000.
Built-In Test (BIT)
A Built-In Test (BIT) function is available to allow rapid testing of the device’s I/O by
either applying a defined static pattern to the ADC or by generating a dynamic ramp at
the ADC’s output. The dynamic ramp can be used with a clock frequency of up to
750 Msps. This function is controlled via the 3-wire bus interface at address 101.
•
The BIT is active when Data0 = 1 at address 110.
•
The BIT is inactive when Data0 = 0 at address 110.
•
The Data1 bit allows choosing between static mode (Data1 = 0) and dynamic mode
(Data1 = 1).
When the static BIT is selected (Data1 = 0), it is possible to write any 8-bit pattern by
defining the Data9 to Data2 bits. Port B then outputs an 8-bit pattern equal to Data9 ...
Data2, and Port A outputs an 8-bit pattern equal to NOT (Data9 ... Data2).
43
2153C–BDC–04/04
Example:
Address = 110
Data =
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
One should then obtain 01010101 on Port B and 10101010 on Port A.
When the dynamic mode is chosen (Data1 = 1) port B outputs a rising ramp while Port A
outputs a decreasing one.
Note:
Decimation Mode
The decimation mode is provided to enable rapid testing of the ADC at a maximum clock
frequency of 750 Msps. In decimation mode, one data out of 16 is output, thus leading to
a maximum output rate of 46.875 Msps.
Note:
Die Junction
Temperature Monitoring
Function
In dynamic mode, use the DRDA function to align the edges of CLKO with the middle of
the data.
Frequency (CLKO) = frequency (Data) = Frequency (CLKI)/16.
A die junction temperature measurement setting is included on the board for junction
temperature monitoring.
The measurement method forces a 1 mA current into a diode-mounted transistor.
Caution should be given to respecting the polarity of the current.
In any case, one should make sure the maximum voltage compliance of the current
source is limited to a maximum of 1V or use a resistor serial-mounted with the current
source to avoid damaging the transistor device (this may occur if the current source is
reverse-connected).
The measurement setup is illustrated in Figure 47.
Figure 47. Die Junction Temperature Monitoring Setup
VDiode (Pin 35)
1 mA
GNDD
(Pin 36)
44
Protection
Diodes
AT84AD001B
2153C–BDC–04/04
AT84AD001B
The VBE diode’s forward voltage in relation to the junction temperature (in steady-state
conditions) is shown in Figure 48.
Figure 48. Diode Characteristics Versus TJ
860
840
820
Diode Voltage (mV)
800
780
760
740
720
700
680
660
640
620
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
Junction Temperature (˚C)
VtestI, VtestQ
VtestI and VtestQ pins are for internal test use only. These two signals must be left
open.
Equivalent Input/Output Schematics
Figure 49. Simplified Input Clock Model
VCCD
CLK
100Ω
50Ω
VCCD/2
50Ω
100Ω
CLKB
GNDD
45
2153C–BDC–04/04
Figure 50. Simplified Data Ready Reset Buffer Model
VCCD
DDRB
100Ω
50Ω
VCCD/2
50Ω
100Ω
DDRBN
GNDD
Figure 51. Analog Input Model
Vcca
Vcca
DC Coupling
(Common Mode = Ground = 0V)
50Ω
Vinl Reverse
Termination
Sel Input I
ESD
GND
VinI
VinI Double Pad
GND – 0.4V
MAX
ESD
GND
50Ω
VinQ Reverse
Termination
GND
GND
VinQ
VinQ
Double
Pad
46
Sel Input Q
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 52. Data Output Buffer Model
VCCO
DOAIO, DOAI7
DOBIO, DOBI7
DOAION, DOAI7N
DOBION, DOBI7N
GNDO
Definitions of Terms
Table 16. Definitions of Terms
Abbreviation
Definition
Description
BER
Bit Error Rate
The probability to exceed a specified error threshold for a sample at a maximum specified
sampling rate. An error code is a code that differs by more than ±4 LSB from the correct code
DNL
Differential
Non-Linearity
The differential non-linearity for an output code i is the difference between the measured step
size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the
maximum value of all DNL (i). A DNL error specification of less than 1 LSB guarantees that
there are no missing output codes and that the transfer function is monotonic
ENOB
Effective Number of
Bits
FPBW
Full Power Input
Bandwidth
The analog input frequency at which the fundamental component in the digitally
reconstructed output waveform has fallen by 3 dB with respect to its low frequency value
(determined by FFT analysis) for input at full-scale -1 dB (-1 dBFS)
IMD
Inter-Modulation
Distortion
The two tones intermodulation distortion (IMD) rejection is the ratio of either of the two input
tones to the worst third order intermodulation products
INL
Integral
Non-Linearity
The integral non-linearity for an output code i is the difference between the measured input
voltage at which the transition occurs and the ideal value of this transition. INL (i) is
expressed in LSBs and is the maximum value of all |INL (i)|
JITTER
Aperture
uncertainty
The sample-to-sample variation in aperture delay. The voltage error due to jitters depends on
the slew rate of the signal at the sampling point
Noise Power Ratio
The NPR is measured to characterize the ADC’s performance in response to broad
bandwidth signals. When applying a notch-filtered broadband white noise signal as the input
to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-ofnotch to the average in-notch power spectral density magnitudes for the FFT spectrum of the
ADC output sample test
NPR
A
SINAD – 1.76 + 20 log ----------Fs/2
ENOB = ----------------------------------------------------------------------------6.02
Where A is the actual input amplitude and Fs is
the full scale range of the ADC under test
47
2153C–BDC–04/04
Table 16. Definitions of Terms (Continued)
Abbreviation
Definition
Description
ORT
Overvoltage
Recovery Time
The time to recover a 0.2% accuracy at the output, after a 150% full-scale step applied on
the input is reduced to midscale
PSRR
Power Supply
Rejection Ratio
The ratio of input offset variation to a change in power supply voltage
SFDR
Spurious Free
Dynamic Range
The ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the
RMS value of the highest spectral component (peak spurious spectral component). The peak
spurious component may or may not be a harmonic. It may be reported in dB (related to the
converter -1 dB full-scale) or in dBc (related to the input signal level)
SINAD
Signal to Noise and
Distortion Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale (-1
dBFS) to the RMS sum of all other spectral components including the harmonics, except DC
SNR
Signal to Noise
Ratio
The ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale, to the
RMS sum of all other spectral components excluding the first 9 harmonics
SSBW
Small Signal Input
Bandwidth
The analog input frequency at which the fundamental component in the digitally
reconstructed output waveform has fallen by 3 dB with respect to its low frequency value
(determined by FFT analysis) for input at full-scale -10 dB (-10 dBFS)
TA
Aperture delay
The delay between the rising edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] and the time at which VIN and VINB are sampled
TC
Encoding Clock
period
TC1 = minimum clock pulse width (high)
TC = TC1 + TC2
TC2 = minimum clock pulse width (low)
TD1
Time Delay from
Data Transition to
Data Ready
The general expression is TD1 = TC1 + TDR - TDO with TC = TC1 + TC2 = 1 encoding clock
period
TD2
Time Delay from
Data Ready to
Data
The general expression is TD2 = TC2 + TDR - TDO with TC = TC1 + TC2 = 1 encoding clock
period
TDO
Digital Data Output
Delay
The delay from the rising edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] to the next point of change in the differential output data (zero crossing) with a
specified load
TDR
Data Ready Output
Delay
The delay from the falling edge of the differential clock inputs (CLK, CLKB) [zero crossing
point] to the next point of change in the differential output data (zero crossing) with a
specified load
TF
Fall Time
The time delay for the output data signals to fall from 20% to 80% of delta between the low
and high levels
THD
Total Harmonic
Distortion
The ratio expressed in dB of the RMS sum of the first 9 harmonic components to the RMS
input signal amplitude, set at 1 dB below full-scale. It may be reported in dB (related to the
converter -1 dB full-scale) or in dBc (related to the input signal level )
TPD
Pipeline Delay
The number of clock cycles between the sampling edge of an input data and the associated
output data made available (not taking into account the TDO)
TR
Rise Time
48
The time delay for the output data signals to rise from 20% to 80% of delta between the low
and high levels
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Table 16. Definitions of Terms (Continued)
Abbreviation
Definition
Description
TRDR
Data Ready Reset
Delay
The delay between the falling edge of the Data Ready output asynchronous reset signal
(DDRB) and the reset to digital zero transition of the Data Ready output signal (DR)
TS
Settling Time
The time delay to rise from 10% to 90% of the converter output when a full-scale step
function is applied to the differential analog input
VSWR
Voltage Standing
Wave Ratio
The VSWR corresponds to the ADC input insertion loss due to input power reflection. For
example, a VSWR of 1.2 corresponds to a 20 dB return loss (99% power transmitted and 1%
reflected)
49
2153C–BDC–04/04
Using the AT84AD001B Dual 8-bit 1 Gsps ADC
Decoupling, Bypassing
and Grounding of Power
Supplies
The following figures show the recommended bypassing, decoupling and grounding
schemes for the dual 8-bit 1 Gsps ADC power supplies.
Figure 53. VCCD and VCCA Bypassing and Grounding Scheme
L
PC Board 3.3V
VCCD
L
1µF
VCCA
100 pF
PC Board GND
C
C
Figure 54. VCCO Bypassing and Grounding Scheme
L
VCCO
PC Board 2.25V
1µF
100 pF
PC Board GND
C
Note:
L and C values must be chosen in accordance with the operation frequency of the application.
Figure 55. Power Supplies Decoupling Scheme
VCCA
VCCA
100 pF 10 nF
GNDA
GNDA
GNDO
VCCD
VCCO
VCCO
100 pF 10 nF
GNDO
100 pF 10 nF
GNDD
Note:
50
The bypassing capacitors (1 µF and 100 pF) should be placed as close as possible to the board connectors, whereas the
decoupling capacitors (100 pF and 10 nF) should be placed as close as possible to the device.
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Analog Input
Implementation
The analog inputs of the dual ADC have been designed with a double pad implementation as illustrated in Figure 56. The reverse pad for each input should be tied to ground
via a 50Ω resistor.
The analog inputs must be used in differential mode only.
Figure 56. Termination Method for the ADC Analog Inputs in DC Coupling Mode
50Ω
VinI
50Ω Source
VinI
Channel I
GND
GND
VinIB
50Ω
VinIB
Dual ADC
50Ω
VinQ
50Ω Source
VinQ
Channel Q
GND
VinQB
GND
50Ω
VinQB
51
2153C–BDC–04/04
Figure 57. Termination Method for the ADC Analog Inputs in AC Coupling Mode
50Ω
VinI
50Ω Source
VinI
Channel I
GND
VinIB
GND
50Ω
VinIB
Dual ADC
50Ω
VinQ
50Ω Source
VinQ
Channel Q
GND
VinQB
GND
50Ω
VinQB
Clock Implementation
The ADC features two different clocks (I or Q) that must be implemented as shown in
Figure 58. Each path must be AC coupled with a 100 nF capacitor.
Figure 58. Differential Termination Method for Clock I or Clock Q
ADC Package
CLK
50Ω
VCCD/2
100 nF
CLKB
Note:
52
50Ω
Differential Buffer
100 nF
When only clock I is used, it is not necessary to add the capacitors on the CLKQ and
CLKQN signal paths; they may be left floating.
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 59. Single-ended Termination Method for Clock I or Clock Q
VCCD
AC coupling capacitor
50Ω
Source
R1
CLK
50Ω
50Ω
AC coupling capacitor
R2
CLKB
50Ω
VCCD/2
Output Termination in
1:1 Ratio
When using the integrated DMUX in 1:1 ratio, the valid port is port A. Port B remains
unused.
Port A functions in LVDS mode and the corresponding outputs (DOAI or DOAQ) have to
be 100Ω differentially terminated as shown in Figure 60 on page 54.
The pins corresponding to Port B (DOBI or DOBQ pins) must be left floating (in high
impedance state).
Figure 60 shows the example of a 1:1 ratio of the integrated DMUX for channel I (the
same applies to channel Q).
53
2153C–BDC–04/04
Figure 60. Example of Termination for Channel I Used in DMUX 1:1 Ratio (Port B Unused)
DOBI0 / DOBI0N
DOBI1 / DOBI1N
DOBI2 / DOBI2N
Port B
DOBI3 / DOBI3N
Floating (High Z)
DOBI4 / DOBI4N
DOBI5 / DOBI5N
DOBI6 / DOBI6N
DOBI7 / DOBI7N
Dual ADC Package
DOAI0 / DOAI0N
DOAI1 / DOAI1N
VCCO
DOAI2 / DOAI2N
DOAI3 / DOAI3N
Port A
DOAI4 / DOAI4N
DOAI5 / DOAI5N
DOAI0
Z0 = 50Ω
DOAI0N
Z0 = 50Ω
LVDS In
DOAI6 / DOAI6N
DOAI7 / DOAI7N
100Ω
LVDS In
Note:
If the outputs are to be used in single-ended mode, it is recommended that the true and false signals be terminated with a 50Ω
resistor.
Using the Dual ADC With Figure 61 on page 55 illustrates the configuration of the dual ADC (1:2 DMUX mode,
independent I and Q clocks) driving an LVDS system (ASIC/FPGA) with potential addiand ASIC/FPGA Load
tional DMUXes used to halve the speed of the dual ADC outputs.
54
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 61. Dual ADC and ASIC/FPGA Load Block Diagram
Data rate = FsI/2
Port A
DEMUX
8 :16
Channel I
Data rate = FsQ/2
Data rate = FsQ/4
CLKI/CLKIN @ FsI
Dual 8-bit 1 Gsps ADC
Port A
Channel Q
DMUX
8 :16
ASIC / FPGA
Port B
Channel I
DMUX
8 :16
CLKQ/CLKQN @ FsQ
Port B
DMUX
8 :16
Channel Q
Note:
The demultiplexers may be internal to the ASIC/FPGA system.
55
2153C–BDC–04/04
Thermal Characteristics
Simplified Thermal
Model for LQFP 144
20 x 20 x 1.4 mm
The following model has been extracted from the ANSYS FEM simulations.
Assumptions: no air, no convection and no board.
Figure 62. Simplified Thermal Model for LQFP Package
Silicon Junction
355 µm silicon die
25 mm 2
λ = 0.95W/cm/˚C
0.6˚C/watt
40 µm Epoxy/Ag glue
λ = 0.02 W/cm/˚C
1.4˚C/watt
Copper paddle
λ = 2.5W/cm/˚C
Package top
Resin
λ = 0.007W/cm/˚C
0.1˚C/watt
6.1˚C/watt
1.5˚C/watt
5.5˚C/watt
Leads tip
Aluminium paddle
Resin
Copper alloy leadframe
λ = 0.007W/cm/˚C
λ = 25W/cm/˚C
Aluminium paddle
λ = 0.75W/cm/˚C
0.1˚C/watt
Resin bottom
λ = 0.007W/cm/˚C
4.3˚C/watt
Package
bottom
Assumptions:
Die 5.0 x 5.0 = 25 mm 2
40 µm thick Epoxy/Ag glue
8.3˚C/watt
100 µm air gap λ = 0.00027W/cm/˚C
11.4˚C/watt
Package bottom
connected to:
100 µm thermal grease gap diamater 12 mm
λ = 0.01W/cm/˚C
(user dependent)
Top of user board
1.5˚C/watt
Note:
The above are typical values with an assumption of uniform power dissipation over 2.5 x 2.5 mm2 of the top surface of the die.
Thermal Resistance from
Junction to Bottom of Leads
Assumptions: no air, no convection and no board.
Thermal Resistance from
Junction to Top of Case
Assumptions: no air, no convection and no board.
Thermal Resistance from
Junction to Bottom of Case
Assumptions: no air, no convection and no board.
Thermal Resistance from
Junction to Bottom of Air Gap
The thermal resistance from the junction to the bottom of the air gap (bottom of package) is 17.9° C/W typical.
56
The thermal resistance from the junction to the bottom of the leads is 15.2° C/W typical.
The thermal resistance from the junction to the top of the case is 8.3° C/W typical.
The thermal resistance from the junction to the bottom of the case is 6.4° C/W typical.
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Thermal Resistance from
Junction to Ambient
The thermal resistance from the junction to ambient is 25.2° C/W typical.
Note:
In order to keep the ambient temperature of the die within the specified limits of the
device grade (that is TA max = 70°C in commercial grade and 85°C in industrial grade)
and the die junction temperature below the maximum allowed junction temperature of
105°C, it is necessary to operate the dual ADC in air flow conditions (1m/s recommended).
In still air conditions, the junction temperature is indeed greater than the maximum
allowed TJ.
- TJ = 25.2°C/W x 1.4W + TA = 35.28 + 70 = 105.28°C for commercial grade devices
- TJ = 25.2°C/W x 1.4W + TA = 35.28 + 85 = 125.28°C for industrial grade devices
Thermal Resistance from
Junction to Board
The thermal resistance from the junction to the board is 13° C/W typical.
57
2153C–BDC–04/04
Ordering Information
Part Number
Package
Temperature Range
Screening
Comments
AT84XAD001BTD
LQFP 144
Ambient
Prototype
Prototype version
Please contact your local Atmel sales office
AT84AD001BCTD
LQFP 144
C grade
0°C < TA < 70°C
Standard
AT84AD001BITD
LQFP 144
I grade
-40°C < TA < 85°C
Standard
AT84AD001TD-EB
LQFP 144
Ambient
Prototype
58
Evaluation Kit
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Packaging Information
Figure 63. Type of Package
N
Dims.
A
A1
A2
D
D1
E
E1
L
e
b
ddd
ccc
o
1
B E1
A
E
Notes:
D
D1
Body +2.00 mm footprint
Tols. Leads
144L
max.
1.60
0.05 min./0.15 max.
+/- 0.05
1.40
+/-0.20
22.00
+/-0.10
20.00
+/-0.20
22.00
+/-0.10
20.00
+0.15/-0.10
0.60
basic
0.50
+/-0.05
0.22
0.08
max.
0.08
o
0 o- 5
1. All dimensions are in millimeters
2. Dimensions shown are nominal with tolerances as indicated
3. L/F: eftec 64T copper or equivalent
4. Foot length: "L" is measured at gauge plane
at 0.25 mm above the seating plane
D
12 o TYP.
A2
e
A1
A
o
12 TYP.
0.20 RAD max.
0.20 RAD nom.
6o
A
C
Stand off
A1
0.25
Seating plane
C
Lead coplanarity
0
0.17 max
b
L
Note:
+ o
-4
ddd e
c A-B e
De
ccc
c
Thermally enhanced package: LQFP 144, 20 x 20 x 1.4 mm.
59
2153C–BDC–04/04
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2153C–BDC–04/04
0M
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