Rohm BU9718KV Picture cell driver for stn lcd driver for low voltage power supply Datasheet

Standard ICs
Picture cell driver for STN (LCD driver)
for low voltage power supplies
BU9718KV
The BU9718KV is a driver IC designed for the character-type STN liquid crystal panels which are ideal for applications such as portable devices. The number of display segments includes 32 output segments and 3 common outputs, enabling drive of up to 96 segments. A compact 48-pin QFP package with a pitch of 0.5 mm is used, enabling
compact size for the set as a whole.
Applications
•Portable
terminals (POS, ECR, PDA, and others),
held telephone units), and others Low-voltage power
supply sets
movie projectors, cameras, telephones (cordless hand-
•1)Features
Operates on 3V power supply.
4) Up to 32 segment output pins and 3 common output
pins are provided, enabling a total display of up to
96 segments.
5) 1 / 3 duty display.
6) Either 1 / 2 or 1 / 3 bias can be selected for power supply for LCD display.
2) Low current dissipation. (0.1µA in low power mode
(actual value))
3) Compact package. (molded section is 7.0 mmⵧ)
•Absolute maximum ratings (Ta = 25°C, V
SS
Parameter
Power supply voltage∗1
Input voltage∗1
Output voltage∗1
Output current
Power dissipation
Storage temperature
= 0V)
Pin
Limits
VDD
VDD
– 0.3 ~ + 7.0
V
VIN
OSC, CS, CK, DI, RES
– 0.3 ~ VDD + 0.3
V
VOUT
OSC
– 0.3 ~ VDD + 0.3
ISO
S1 ~ S32
ICO
COM1 ~ COM3
Pd
—
400 ∗2
mW
Tstg
—
– 55 ~ + 125
°C
Symbol
Unit
V
µA
300
3
mA
∗1 Max. voltage that can be applied with a VSS pin
∗2 Reduced by 4.0mW for each increase in Ta 1°C over 25°C.
•Recommended operating conditions (Ta = 25°C, V
SS
Parameter
Power supply voltage∗
Input voltage∗
Oscillation freq., with
external input
= 0V)
Symbol
Pin
Min.
Typ.
Max.
Unit
VDD
VDD
2.7
—
3.5
V
VDD1
VDD1
0
2 / 3 VDD
VDD
V
VDD2
VDD2
0
1 / 3 VDD
VDD
V
fOSC
OSC
—
38
100
kHz
External resistance
R
OSC
—
47
—
kΩ
External capacitance
C
OSC
—
1000
—
pF
Topr
—
—
85
°C
Operating temperature
– 40
∗ Indicates the max. voltage that can be applied with a VSS pin.
1
Standard ICs
BU9718KV
•Block diagram
VDD1
VDD2
LCD Power
RES
CS
DI
CTRL Logic
Data Latch
CK
OSC
25
24
37
S22
RES
S21
VDD
S20
VDD1
S19
VDD2
S18
VQFP48
VSS
S17
OSC
S16
CS
S15
CK
S14
DI
S13
13
48
S11
S10
S9
S8
S7
S6
S5
S4
S3
S1
12
S2
1
N.C.
N.C.
2
N.C.
COM3
S12
S32
S4
S3
36
COM2
N.C.
S23
S1
S2
S24
S25
S26
S27
S28
S29
S30
S31
COM3
COM1
S32
COM2
COM1
•Pin assignments
S31
Segment Driver
Common Driver
S30
OSC
Standard ICs
BU9718KV
•Pin descriptions
Pin No.
Pin name
I/O
Function
Processing when not in use
1—11
13—23
26—35
S1—S11
S12—S22
S23—S32
O
Segment data output pin; outputs LCD drive voltage that
matches COM1 - COM3 compatible data
36
37
38
COM1
COM2
COM3
O
Common drive output; frame freq. fC = (fOSC / 384) Hz
VSS
39
RES
I
Reset input; when RES = L, resets internal data
(include. control data)
VDD
44
OSC
—
Oscillation pin (for common, segment alternation waves)
VSS
45
CS
I
Chip segment input; when CS = H, data can be transferred
VSS
46
CK
I
Synchronous clock input for serial data transfer
VSS
47
DI
I
Serial data input
VSS
OPEN
41
VDD1
—
Internal standard voltage for liquid-crystal drive; when using
1 / 2 bias mode, connects to VDD2
42
VDD2
—
Internal standard voltage for liquid-crystal drive; when using
1 / 2 bias mode, connects to VDD1
• Electrical characteristics (unless otherwise noted, Ta = 25°C, V
DD
Parameter
OPEN
OPEN
= 2.7V to 3.5V, VSS = 0V)
Symbol
Min.
Typ.
Max.
Unit
Conditions
Pin
Input high level voltage
VIH
0.8 VDD
—
VDD
V
—
CS, CK, DI, RES
Input low level voltage
VIL
0
—
0.2 VDD
V
—
CS, CK, DI, RES
Input high level current
IIH
0
—
6.0
µA
VI = VDD
CS, CK, DI, RES
Input low level current
Output high level voltage
Output low level voltage
Output medium level voltage
Power supply current
IIL
0
—
6.0
µA
VI = VSS
CS, CK, DI, RES
VSOH
—
VDD – 1.0
—
V
IO = – 20µA
S1 ~ S32
VCOH
—
VDD – 1.0
—
V
IO = – 100µA
COM1 ~ COM3
VSOL
—
1.0
—
V
IO = 20µA
S1 ~ S32
VCOL
—
1.0
—
V
IO = 100µA
COM1 ~ COM3
VCM1
—
1 / 2 VDD
± 1.0
—
V
1 / 2bias
COM1 ~ COM3
VSM1
—
2 / 3 VDD
± 1.0
—
V
1 / 3bias
S1 ~ S32
VCM2
—
2 / 3 VDD
± 1.0
—
V
1 / 3bias
COM1 ~ COM3
VSM2
—
1 / 3 VDD
± 1.0
—
V
1 / 3bias
S1 ~ S32
VCM3
—
1 / 3 VDD
± 1.0
—
V
1 / 3bias
COM1 ~ COM3
IQ
—
0.1
30
µA
Low-power mode
—
IDD
—
100
300
µA
fOSC = 38kHz
—
3
Standard ICs
BU9718KV
•AC characteristics (unless otherwise noted, Ta = 25°C, V
DD
Parameter
= 2.7V to 3.5V, VSS = 0V)
Symbol
Min.
Typ.
Max.
Unit
Conditions
Pin
Guaranteed oscillation range
fOSC
10
38
80
Operating frequency
fOSC
—
—
100
kHz
C = 1000pF R = 47kΩ
OSC
kHz
External input
OSC
Data set-up time
tDS
200
—
—
ns
—
CK, DI
Data hold time
tDH
200
—
—
ns
—
CK, DI
CS set-up time
tCS
200
—
—
ns
—
CS, CK
CS hold time
tCH
200
—
—
ns
—
CS, CK
CK "H" level pulse width
tCKH
200
—
—
ns
—
CK
CK "L" level pulse width
tCKL
200
—
—
ns
—
CK
Rise time
tr
—
—
100
ns
—
CS, CK, DI
Fall time
tf
—
—
100
ns
—
CS, CK, DI
AC timing waveform
(1) When CK is stopped at “L”
0.8VDD
tCKH
tCS
CS
tCKL
0.2VDD
0.8VDD
0.8VDD
0.5VDD
0.5VDD
0.2VDD
CK
tDS
tCH
tDH
tr
tf
DI
Fig.1
(2) When CK is stopped at “H”
0.8VDD
CS
tCKH
tCS
tCKL
0.8VDD
CK
0.5VDD
0.2VDD
tDS
0.5VDD
tDH
tr
DI
Fig.2
4
0.2VDD
tf
tCH
0.2VDD
Standard ICs
BU9718KV
Timing charts
(1) When CK is stopped at “L”
CS
CK
D1
D2
D3
D95
0
0
0
0
0
BM
LC
OE
DI
Display data
Control code
Fig.3
When CS is HIGH, data can be transferred. Data is sent to the shift register at the rising edge of CK. After all of the
DI data has been transferred, CS should be set to LOW. The voltage corresponding to the display data transferred at
the falling edge of CS is output.
(2) When CK is stopped at “H”
CS
CK
D1
D2
D3
D96
0
0
0
0
0
BM
LC
OE
DI
Display data
Control code
Fig.4
Control code table
OE
Output enable control
0
Normal operation
1
No display; all display data = 0 (internal oscillation circuit is operating)
LC
Low-power mode control
0
Normal operation
1
Low-power mode = internal oscillation circuit has stopped; segment and common output = 0
BM
Bias mode control
0
1 / 3 bias
1
1 / 2 bias
5
Standard ICs
BU9718KV
Correspondence between display data input and segments
Segment
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
6
COM3
D1
D4
D7
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
COM2
D2
D5
D8
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
COM1
D3
D6
D9
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
Segment
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
COM3
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D82
D85
D88
D91
D94
COM2
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D83
D86
D89
D92
D95
COM1
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
D84
D87
D90
D93
D96
Standard ICs
BU9718KV
•Output waveforms
fO = fOSC / 384
fO = fOSC / 384
VDD
COM1
VDD
VDD1
VDD2
VSS
VDD1, VDD2
VSS
VDD
COM2
VDD
VDD1
VDD2
VSS
VDD1, VDD2
VSS
VDD
VDD
VDD1
VDD2
VSS
VDD1, VDD2
COM3
VSS
VDD
LCD driver output, when all LCD segments for
VDD
VDD1
VDD2
VSS
VDD1, VDD2
COM1, 2 and 3 are out
VSS
VDD
LCD driver output, when only the LCD segment
VDD
VDD1
VDD2
VSS
VDD1, VDD2
for COM1 is lit up
VSS
VDD
LCD driver output, when only the LCD segment
VDD
VDD1
VDD2
VSS
VDD1, VDD2
for COM2 is lit up
VSS
VDD
LCD driver output, when the LCD segments for
VDD
VDD1
VDD2
VSS
VDD1, VDD2
COM1 and 2 are lit up
VSS
VDD
VDD1
VDD2
VSS
VDD
LCD driver output, when only the LCD segment for
VDD1, VDD2
COM3 is lit up
VSS
VDD
LCD driver output, when the LCD segments for
VDD
VDD1
VDD2
VSS
VDD1, VDD2
COM1 and 3 are lit up
VSS
VDD
LCD driver output, when the LCD segments for
VDD
VDD1
VDD2
VSS
VDD1, VDD2
COM2 and 3 are lit up
VSS
VDD
LCD driver output, when all the LCD segments
VDD
VDD1
VDD2
VSS
VDD1, VDD2
for COM1, 2 and 3 are lit up
VSS
1 / 2 bias 1 / 3 duty waveform
1 / 3 bias 1 / 3 duty waveform
Fig.5
Fig.6
7
Standard ICs
BU9718KV
•Application example 1
47kΩ
1000pF
GND
VDD
VDD
OSC
COM1
COM2
RES
COM3
VSS
S1
VDD1
VDD2
S2
BU9718KV
Controller
S3
S4
96
Segment
LCD
S5
C ⭌ 0.047µF
S6
CS
CK
DI
S32
1 / 2 bias mode
Fig.7
47kΩ
1000pF
GND
VDD
VDD
OSC
COM1
COM2
RES
COM3
VSS
S1
VDD1
VDD2
S2
BU9718KV
Controller
S3
S4
S5
C ⭌ 0.047µF
S6
CS
CK
DI
S32
1 / 3 bias mode
Fig.8
8
96
Segment
LCD
Standard ICs
BU9718KV
•Application example 2
47kΩ
1000pF
GND
VDD
VDD
OSC
COM1
COM2
RES
COM3
VSS
S1
R
∗1)
VDD1
VDD2
Controller
S2
BU9718KV
R
S3
S4
96
Segment
LCD
S5
C ⭌ 0.047µF
S6
CS
CK
DI
S32
1 / 2 bias mode
Fig.9
47kΩ
1000pF
GND
VDD
VDD
OSC
COM1
COM2
RES
COM3
VSS
∗2)
R
S1
VDD1
R
VDD2
S2
BU9718KV
Controller
S3
S4
R
96
Segment
LCD
S5
C ⭌ 0.047µF
S6
CS
CK
DI
S32
1 / 3 bias mode
Fig.10
Note: The resistance values and capacitance for ∗1 and ∗2 should be set to match the LCD panel, and should be checked using test operation.
9
Standard ICs
BU9718KV
Make sure of the following when resetting when the power is on.
• When using the external reset terminal, make RST = “L” at 1 ms or more with VDD at 2.7V or more.
• When not using the external reset terminal,VDD has to satisfy the following conditions.
Instruction receipt possible
VDD ⭌ 2.7V
tWAIT ⭌ 1ms
VDD < 0.3V
0 < tON < 10ms
•External dimensions (Units: mm)
9.0 ± 0.3
7.0 ± 0.2
24
48
13
1
1.425 ± 0.1
0.10
25
0.5
12
0.125 ± 0.1
0.2 ± 0.1
0.10
VQFP48
10
0.5
7.0 ± 0.2
9.0 ± 0.3
36
37
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