Allegro A6812EA Dabic-iv, 20-bit serial-input, latched source driver Datasheet

Data Sheet
26182.126A
6812
DABiC-IV, 20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6812xA
28
LOGIC
SUPPLY
2
27
SERIAL
DATA IN
OUT 20
3
26
OUT 1
OUT 19
4
25
OUT 2
OUT 18
5
24
OUT 3
OUT 17
6
23
OUT 4
OUT 16
7
22
OUT 5
OUT 15
8
21
OUT 6
OUT 14
9
20
OUT 7
OUT 13
10
19
OUT 8
OUT 12
11
18
OUT 9
OUT 11
12
17
OUT 10
BLANKING
13
ST
28
16
STROBE
GROUND
14
CLK
27
15
CLOCK
BLNK
LATCHES
VDD
REGISTER
SERIAL
DATA OUT
VBB
LATCHES
1
REGISTER
LOAD
SUPPLY
Dwg. PP-029-7
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ................... 7.0 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current Range,
IOUT ......................... -40 mA to +15 mA
Input Voltage Range,
VIN ....................... -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD ........................................ See Graph
Operating Temperature Range, TA
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20°C to +85°C
Storage Temperature Range,
TS ............................... -55°C to +125°C
Caution: These CMOS devices have input static
protection (Class 2) but are still susceptible to
damage if exposed to extremely high static
electrical charges.
The A6812– devices combine a 20-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar sourcing
outputs and pnp active pull downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also
allow these devices to be used in many other peripheral power driver
applications. The A6812– features an increased data input rate (compared with the older UCN/UCQ5812-F) and a controlled output slew
rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply, they
will operate to at least 10 MHz.
A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as
the A6809– and A6810– (10 bits), A6811– (12 bits), and A6818– (32
bits).
The A6812– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA.
Two temperature ranges are available for optimum performance in
commercial (suffix S-) or industrial (suffix E-) applications. Package
styles are provided for through-hole DIP (suffix -A), surface-mount
SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix
-EP). Copper lead frames, low logic-power dissipation, and low
output-saturation voltages allow these drivers to source 25 mA from all
outputs continuously to more than +43°C (suffix -LW), +61°C (suffix
-EP), or +77°C (suffix -A).
FEATURES
■ Controlled Output Slew Rate ■ Low Output-Saturation Voltages
■ High-Speed Data Storage
■ Low-Power CMOS Logic
■ 60 V Minimum
and Latches
Output Breakdown
■ Improved Replacements
■ High Data Input Rate
for TL5812–, UCN5812–,
■ PNP Active Pull-Downs
and UCQ5812–
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A, -EP, or -LW).
Always order by complete part number, e.g., A6812SLW .
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
OUT20
SERIAL
DATA OUT
LOAD
SUPPLY
LOGIC
SUPPLY
SERIAL
DATA IN
OUT 1
3
2
1
V DD 28
27
26
VBB
OUT19
LOGIC
SUPPLY
2
27
SERIAL
DATA IN
OUT 20
3
26
OUT 1
OUT 19
4
25
OUT 2
1
SERIAL
DATA OUT
VBB
VDD
OUT 3
7
23
OUT 17
6
23
OUT 4
22
OUT 16
7
22
OUT 5
9
21
OUT 15
8
21
OUT 6
10
20
OUT 14
9
20
OUT 7
11
19
OUT 13
10
19
OUT 8
OUT 12
11
18
OUT 9
OUT 11
12
17
OUT 10
BLANKING
13
ST
28
16
STROBE
GROUND
14
CLK
27
15
CLOCK
REGISTER
18
OUT9
17
OUT10
REGISTER
ST
16
STROBE
CLK
15
CLOCK
14
GROUND
13
12
OUT11
OUT 8
LATCHES
24
LATCHES
5
OUT 2
REGISTER
OUT 18
LATCHES
24
REGISTER
6
LATCHES
25
8
BLNK
Dwg. PP-059-1
TYPICAL INPUT CIRCUIT
Dwg. PP-029-8
VDD
θJ
A
55
°C
/W
'LW
', R
θJ
1.0
/W
°C
45
SU
FF
IX
1.5
=
=
OUTN
'E
P'
,R
A
V BB
2.0
θJ
TYPICAL OUTPUT DRIVER
SU
FF
IX
', R
'A
Dwg. EP-010-5
2.5
IX
FF
SU
IN
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
OUT12
28
LOAD
SUPPLY
5
BLANKING
OUT18
A6812xLW
4
A6812xEP
A =
66
°C
/W
0.5
0
25
50
75
100
125
AMBIENT TEMPERATURE IN °C
150
Dwg. GP-024-2
Dwg. EP-021-19
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
V DD
CLOCK
SERIAL
DATA IN
SERIAL-PARALLEL SHIFT REGISTER
STROBE
LATCHES
SERIAL
DATA OUT
BLANKING
MOS
BIPOLAR
LOAD
SUPPLY
VBB
GROUND
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
...
IN-1
Output Contents
IN Blanklng
I1 I2 I3 ... IN-1 IN
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
PN-1 PN
L
P1 P2 P3 ... PN-1 PN
X
X
H
L
X
X
...
P1 P2 P3 ...
L = Low Logic Level
X
PN-1 PN
H = High Logic Level
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X = Irrelevant
X
P = Present State
X
...
X
R = Previous State
L
L
... L
L
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6812S-) or over operating temperature
range (A6812E-), VBB = 60 V unless otherwise noted.
Limits @ VDD = 3.3 V
Characteristic
Output Leakage Current
Symbol
ICEX
Test Conditions
VOUT = 0 V
Limits @ VDD = 5 V
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
—
<-0.1
-15
—
<-0.1
-15
µA
57.5
58.3
—
57.5
58.3
—
V
VOUT(1)
IOUT = -25 mA
VOUT(0)
IOUT = 1 mA
—
1.0
1.5
—
1.0
1.5
V
Output Pull-Down Current
IOUT(0)
VOUT = 5 V to VBB
2.5
5.0
—
2.5
5.0
—
mA
Input Voltage
VIN(1)
2.2
—
—
3.3
—
—
V
VIN(0)
—
—
1.1
—
—
1.7
V
Output Voltage
Input Current
Input Clamp Voltage
Serial Data Output Voltage
Maximum Clock Frequency
Logic Supply Current
IIN(1)
VIN = VDD
—
<0.01
1.0
—
<0.01
1.0
µA
IIN(0)
VIN = 0 V
—
<-0.01
-1.0
—
<-0.01
-1.0
µA
IIN = -200 µA
—
-0.8
-1.5
—
-0.8
-1.5
V
VOUT(1)
IOUT = -200 µA
2.8
3.05
—
4.5
4.75
—
V
VOUT(0)
IOUT = 200 µA
—
0.15
0.3
—
0.15
0.3
V
10*
—
—
10*
—
—
MHz
VIK
fc
IDD(1)
All Outputs High
—
0.25
0.75
—
0.3
1.0
mA
IDD(0)
All Outputs Low
—
0.25
0.75
—
0.3
1.0
mA
IBB(1)
All Outputs High, No Load
—
3.0
6.0
—
3.0
6.0
mA
IBB(0)
All Outputs Low
—
0.2
20
—
0.2
20
µA
tdis(BQ)
CL = 30 pF, 50% to 50%
—
0.7
2.0
—
0.7
2.0
µs
ten(BQ)
CL = 30 pF, 50% to 50%
—
1.8
3.0
—
1.8
3.0
µs
tp(STH-QL)
RL = 2.3 kΩ, CL ≤ 30 pF
—
0.7
2.0
—
0.7
2.0
µs
tp(STH-QH)
RL = 2.3 kΩ, CL ≤ 30 pF
—
1.8
3.0
—
1.8
3.0
µs
Output Fall Time
tf
RL = 2.3 kΩ, CL ≤ 30 pF
2.4
—
12
2.4
—
12
µs
Output Rise Time
tr
RL = 2.3 kΩ, CL ≤ 30 pF
2.4
—
12
2.4
—
12
µs
Output Slew Rate
dV/dt
RL = 2.3 kΩ, CL ≤ 30 pF
4.0
—
20
4.0
—
20
V/µs
IOUT = ±200 µA
—
50
—
—
50
—
ns
Load Supply Current
Blanking-to-Output Delay
Strobe-to-Output Delay
Clock-to-Serial Data Out Delay tp(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
* Operation at a clock frequency greater than the specified minimum is possible but not warranteed.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
SERIAL
DATA IN
B
DATA
50%
t p(CH-SQX)
SERIAL
DATA OUT
DATA
50%
D
E
50%
STROBE
BLANKING
LOW = ALL OUTPUTS ENABLED
t p(STH-QH)
t p(STH-QL)
90%
DATA
OUT N
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
BLANKING
50%
t dis(BQ)
t en(BQ)
tr
tf
90%
OUT N
10%
DATA
Dwg. WP-030
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ...................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................ 25 ns
C. Clock Pulse Width, tw(CH) ............................................ 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) .... 100 ns
E. Strobe Pulse Width, tw(STH) .......................................... 50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable with increased supply voltage;
operation at high temperatures will reduce the specified
maximum clock frequency.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
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data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6812EA & A6812SA
Dimensions in Inches
(controlling dimensions)
28
0.015
0.008
15
0.700
MAX
0.580
0.485
0.600
BSC
1
2
0.070
0.030
3
14
0.100
4
1.565
1.380
0.005
MIN
BSC
0.250
MAX
0.200
0.115
0.015
MIN
0.022
0.014
Dwg. MA-003-28 in
Dimensions in Millimeters
(for reference only)
28
0.381
0.204
15
17.78
MAX
14.73
12.32
15.24
BSC
1
2
1.77
0.77
3
14
2.54
4
39.7
35.1
BSC
0.13
MIN
6.35
MAX
0.39
5.08
2.93
MIN
0.558
0.356
NOTES: 1.
2.
3.
4.
Dwg. MA-003-28 mm
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Lead thickness is measured at seating plane or below.
Supplied in standard sticks/tubes of 12 devices.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6812EEP & A6812SEP
(add “TR” to part number for tape and reel)
Dimensions in Inches
(controlling dimensions)
18
0.013
0.021
12
19
0.219
0.191
11
0.026
0.032
0.456
0.450
INDEX AREA
0.495
0.485
0.050
BSC
0.219
0.191
25
5
26
0.020
28
1
4
0.456
0.450
0.495
0.485
MIN
0.165
0.180
Dwg. MA-005-28A in
Dimensions in Millimeters
(for reference only))
18
0.331
0.533
12
19
5.56
4.85
11
0.812
0.661
11.58
11.43
12.57
12.32
1.27
INDEX AREA
BSC
5.56
4.85
25
5
26
0.51
MIN
4.57
4.20
28
1
4
11.582
11.430
12.57
12.32
Dwg. MA-005-28A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 38 devices or add “TR” to part number for tape and reel.
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6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6812ELW & A6812SLW
(add “TR” to part number for tape and reel)
Dimensions in Inches
(for reference only)
28
15
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
0.7125
0.6969
0° TO 8°
BSC
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-28A in
Dimensions in Millimeters
(controlling dimensions)
28
15
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
18.10
17.70
BSC
0° TO 8°
2.65
2.35
0.10 MIN.
Dwg. MA-008-28A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
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6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
POWER
INTERFACE DRIVERS
Function
Output Ratings*
Part Number†
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers)
8-Bit
8-Bit
8-Bit
8-Bit
8-Bit (constant-current LED driver)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
-120 mA
350 mA
350 mA
350 mA
350 mA
75 mA
250 mA
350 mA
100 mA
50 V‡
50 V
80 V
50 V‡
80 V‡
17 V
50 V
50 V‡
50 V
5895
5821
5822
5841
5842
6275
6595
6A595
6B595
10-Bit (active pull-downs)
-25 mA
60 V
5810-F and 6809/10
12-Bit (active pull-downs)
-25 mA
60 V
5811 and 6811
75 mA
17 V
6276
20-Bit (active pull-downs)
-25 mA
60 V
5812-F and 6812
32-Bit (active pull-downs)
32-Bit
32-Bit (saturated drivers)
-25 mA
100 mA
100 mA
60 V
30 V
40 V
5818-F and 6818
5833
5832
16-Bit (constant-current LED driver)
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V‡
5800
8-Bit
8-Bit
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
-25 mA
350 mA
100 mA
250 mA
60 V
50 V‡
50 V
50 V
5815
5801
6B273
6273
SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 28-Line Decoder/Driver
1.25 A
250 mA
350 mA
100 mA
450 mA
50 V‡
50 V
50 V‡
50 V
30 V
5804
6259
6A259
6B259
6817
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
†
Complete part number includes additional characters to indicate operating temperature range and package style.
‡
Internal transient-suppression diodes included for inductive-load protection.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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