Intersil ACS240K Radiation hardened inverting, octal, three-state buffer/line driver Datasheet

ACS240MS
Radiation Hardened
Inverting, Octal, Three-State Buffer/Line Driver
March 1998
Features
Description
• QML Qualified Per MIL-PRF-38535 Requirements
The Radiation Hardened ACS240MS is an Inverting, Octal,
Three-State Buffer/Line Driver with two active-LOW Enable
inputs (AE and BE). Each Enable input controls four outputs.
When an Enable input is LOW, the corresponding outputs
are active and input signals are inverted. A HIGH on an
Enable input causes the corresponding outputs to be high
impedance, regardless of the input levels.
• 1.25Micron Radiation Hardened SOS CMOS
• Radiation Environment
- Latch-up Free Under any Conditions
- Total Dose . . . . . . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)
- SEU Immunity . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm2)
The ACS240MS is fabricated on a CMOS Silicon on Sapphire (SOS) process, which provides an immunity to Single
Event Latch-up and the capability of highly reliable performance in any radiation environment. These devices offer
significant power reduction and faster performance when
compared to ALSTTL types.
• Input Logic Levels VIL = (0.3V)(VCC), VIH = (0.7V)(VCC)
• Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16mA
• Quiescent Supply Current. . . . . . . . . . . . . . . . . . . .20µA
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . 11.5ns
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Applications
Detailed Electrical Specifications for the ACS240 are
contained in SMD 5962-98540. A “hot-link” is provided
on our homepage with instructions for downloading.
http://www.intersil.com/data/sm/index.htm
• Databus Driving
• Data Routing
• Redundant Data Control Circuitry
Ordering Information
SMD PART NUMBER
TEMP. RANGE (oC)
INTERSIL PART NUMBER
5962F9854001VRC
ACS240DMSR-02
N/A
ACS240D/Sample-02
5962F9854001VXC
ACS240KMSR-02
N/A
N/A
PACKAGE
CASE OUTLINE
-55 to 125
20 Ld SBDIP
CDIP2-T20
25
20 Ld SBDIP
CDIP2-T20
-55 to 125
20 Ld Flatpack
CDFP4-F20
ACS240K/Sample-02
25
20 Ld Flatpack
CDFP4-F20
ACS240HMSR-02
25
Die
N/A
Pinouts
ACS240 (SBDIP)
TOP VIEW
ACS240 (FLATPACK)
TOP VIEW
AE
1
1
20
VCC
2
20 VCC
19 BE
AE
AI1
AI1
2
19
BE
BO4
3
18 AO1
BO4
3
18
AO1
17 BI4
AI2
4
17
BI4
BO3
5
16
AO2
AI3
6
15
BI3
BO2
7
14
AO3
AI4
8
13
BI2
AI2
BO3
4
5
16 AO2
AI3
6
BO2
7
14 AO3
AI4
8
13 BI2
BO1
9
12
AO4
BO1
9
12 AO4
GND
10
11
BI1
GND 10
15 BI3
11 BI1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
File Number
4478
ACS240MS
Die Characteristics
PASSIVATION
DIE DIMENSIONS:
Type: Phosphorous Silicon Glass (PSG)
Thickness: 1.30µm ±0.15µm
Size: 2540µm x 2540µm (100 mils x 100mils)
Thickness: 525µm ±25µm (20.6 mils ±1 mil)
Bond Pad: 110µm x 110µm (4.3 x 4.3 mils)
SPECIAL INSTRUCTIONS:
METALLIZATION: Al
Metal 1 Thickness: 0.7µm ±0.1µm
Metal 2 Thickness: 1.0µm ±0.1µm
Bond VCC First
ADDITIONAL INFORMATION:
Worst Case Density: <2.0 x 105 A/cm2
Transistor Count: 198
SUBSTRATE POTENTIAL:
Unbiased Insulator
Metallization Mask Layout
ACS240MS
AI1
(2)
VCC
(20)
AE
(1)
VCC
(20)
BE
(19)
(18) AO1
BO4 (3)
(17) BI4
AI2 (4)
(16) AO2
BO3 (5)
(15) BI3
AI3 (6)
(14) AO3
BO2 (7)
(13) BI2
AI4 (8)
BO1 (9)
AO4 (12)
(10) (10)
GND GND
(11)
BI1
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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