AD ADN4665ARZ 3 v, lvds, quad, cmos differential line driver Datasheet

3 V, LVDS, Quad, CMOS
Differential Line Driver
ADN4665
±15 kV ESD protection on output pins
400 Mbps (200 MHz) switching rates
100 ps typical differential skew
400 ps maximum differential skew
2 ns maximum propagation delay
3.3 V power supply
±350 mV differential signaling
Low power dissipation (13 mW typical)
Interoperable with existing 5 V LVDS receivers
High impedance on LVDS outputs on power-down
Conforms to TIA/EIA-644 LVDS standards
Industrial operating temperature range: −40°C to +85°C
Available in surface-mount SOIC package and low profile
TSSOP package
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
ADN4665
VCC
DIN4
DIN1
D1
D4
DOUT1+
DOUT4+
DOUT1–
DOUT4–
EN
EN
DOUT2–
DOUT3–
DOUT2+
DOUT3+
D2
D3
DIN2
DIN3
GND
08085-001
FEATURES
Figure 1.
Backplane data transmission
Cable data transmission
Clock distribution
GENERAL DESCRIPTION
The ADN4665 is a quad-channel, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically ±3.5 mA
for driving a transmission medium such as a twisted pair cable.
The transmitted signal develops a differential voltage of typically ±350 mV across a termination resistor at the receiving end.
This voltage is converted back to a TTL/CMOS logic level by an
LVDS receiver.
The ADN4665 also offers active high and active low enable/
disable inputs (EN and EN). These inputs control all four drivers
and turn off the current outputs in the disabled state to reduce
the quiescent power consumption to typically 10 mW.
The ADN4665 offers a new solution to high speed, point-to-point
data transmission and offers a low power alternative to emittercoupled logic (ECL) or positive emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADN4665
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................7
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ..............................................8
General Description ......................................................................... 1
Theory of Operation .........................................................................9
Revision History ............................................................................... 2
Enable Inputs .................................................................................9
Specifications..................................................................................... 3
Applications Information .............................................................9
Timing Characteristics ................................................................ 4
Outline Dimensions ....................................................................... 10
Absolute Maximum Ratings............................................................ 6
Ordering Guide .......................................................................... 10
REVISION HISTORY
5/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADN4665
SPECIFICATIONS
VCC = 3.0 V to 3.6 V, RL = 100 Ω, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. All typical values are given
for VCC = 3.3 V, TA = 25°C.
Table 1.
Parameter
LVDS OUTPUTS (DOUTx+, DOUTx−)
Differential Output Voltage
Change in Magnitude of VOD for Complementary Output States
Offset Voltage
Change in Magnitude of VOS for Complementary Output States
Output High Voltage
Output Low Voltage
INPUTS (DINx, EN, EN)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Clamp Voltage
LVDS OUTPUT PROTECTION (DOUTx+, DOUTx−)
Output Short-Circuit Current 3
Symbol
Min
Typ
Max
Unit
Conditions/Comments 1, 2
VOD
ΔVOD
VOS
ΔVOS
VOH
VOL
250
350
4
1.25
5
1.38
1.03
450
35
1.375
25
1.6
mV
|mV|
V
|mV|
V
V
See Figure 2 and Figure 4
See Figure 2 and Figure 4
See Figure 2 and Figure 4
See Figure 2 and Figure 4
See Figure 2 and Figure 4
See Figure 2 and Figure 4
VCC
0.8
+10
+10
V
V
μA
μA
V
VIN = VCC or 2.5 V
VIN = GND or 0.4 V
ICL = −18 mA
IOS
−6.0
−9.0
mA
Differential Output Short-Circuit Current3
LVDS OUTPUT LEAKAGE (DOUTx+, DOUTx−)
Power-Off Leakage
IOSD
−6.0
−9.0
mA
Output Three-State Current
VIH
VIL
IIH
IIL
VCL
1.125
0.90
2.0
GND
−10
−10
−1.5
+1
+1
−0.8
IOFF
−20
±1
+20
μA
IOZ
−10
±1
+10
μA
POWER SUPPLY
No Load Supply Current, Drivers Enabled
Loaded Supply Current, Drivers Enabled
ICC
ICCL
5.0
23
8.0
30
mA
mA
No Load Supply Current, Drivers Disabled
ICCZ
2.6
6.0
mA
ESD PROTECTION
DOUTx+, DOUTx− Pins
All Pins Except DOUTx+, DOUTx−
±15
±4.5
1
kV
kV
Enabled, DINx = VCC, DOUTx+ = 0 V
or DINx = GND, DOUTx− = 0 V
Enabled, VOD = 0 V
VOUT = 0 V or 3.6 V, VCC = 0 V or
open
EN = 0.8 V, EN = 2.0 V,
VOUT = 0 V or VCC
DINx = VCC or GND
RL = 100 Ω all channels,
DINx = VCC or GND (all inputs)
DINx = VCC or GND, EN = GND,
EN = VCC
Human body model
Human body model
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS.
The ADN4665 is a current-mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is
90 Ω to 110 Ω.
3
Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
2
Rev. 0 | Page 3 of 12
ADN4665
TIMING CHARACTERISTICS
VCC = 3.0 V to 3.6 V, RL = 100 Ω, CL 1 = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. All typical values are given
for VCC = 3.3 V, TA = 25°C.
Table 2.
Parameter 2
AC CHARACTERISTICS
Differential Propagation Delay, High to Low
Differential Propagation Delay, Low to High
Differential Pulse Skew |tPHLD − tPLHD|
Channel-to-Channel Skew
Differential Part-to-Part Skew
Differential Part-to-Part Skew
Rise Time
Fall Time
Disable Time High to Inactive
Disable Time Low to Inactive
Enable Time Inactive to High
Enable Time Inactive to Low
Maximum Operating Frequency
Symbol
Min
Typ
Max
Unit
Conditions/Comments 3, 4
tPHLD
tPLHD
tSKD1 5
tSKD2 6
tSKD3 7
tSKD4 8
tTLH
tTHL
tPHZ
tPLZ
tPZH
tPZL
fMAX 9
0.8
0.8
0
0
0
0
1.18
1.25
0.07
0.1
2.0
2.0
0.4
0.5
1.0
1.2
1.5
1.5
5
5
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 5 and Figure 6
See Figure 5 and Figure 6
See Figure 5 and Figure 6
See Figure 5 and Figure 6
See Figure 5 and Figure 6
0.38
0.4
200
250
1
CL includes probe and jig capacitance.
AC parameters are guaranteed by design and characterization.
3
Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
4
All input voltages are for one channel, unless otherwise specified. Other inputs are set to GND.
5
tSKD1 = |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive-going edge and the negative-going edge of the
same channel.
6
tSKD2 is the differential channel-to-channel skew of any event on the same device.
7
tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
8
tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating
temperature and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay.
9
fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching.
2
Test Circuits and Timing Diagrams
DOUTx+
VCC
RL/2
DINx
V VOS
V VOD
08085-002
RL/2
DOUTx–
NOTES
1. DRIVER IS ENABLED.
Figure 2. Test Circuit for Driver VOD and VOS
VCC
DOUTx+
CL
SIGNAL
GENERATOR
DINx
DOUTx–
50Ω
DRIVER IS
ENABLED
NOTES
1. CL INCLUDES PROBE AND JIG CAPACITANCE.
08085-003
CL
Figure 3. Test Circuit for Driver Propagation Delay and Transition Time
Rev. 0 | Page 4 of 12
ADN4665
3V
DINx
1.5V
0V
tPLHD
tPHLD
VOD
DOUTx–
VOH
0V (DIFFERENTIAL)
VOL
DOUTx+
80%
0V
VDIFF
20%
tTLH
08085-004
VDIFF = DOUTx+ – DOUTx–
tTHL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
VCC
DOUTx+
CL
VCC
50Ω
1.2V
DINx
50Ω
S1
DOUTx–
CL
EN
SIGNAL
GENERATOR
50Ω
EN
08085-005
NOTES
1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
2. S1 CONNECTED TO VCC FOR tPHZ AND tPZH TEST.
3. S1 CONNECTED TO GND FOR tPLZ AND tPZL TEST.
Figure 5. Test Circuit for Driver Three-State Delay
3V
EN WITH EN = GND
OR OPEN CIRCUIT
1.5V
0V
3V
EN WITH EN = VCC
1.5V
0V
tPHZ
tPZH
VOH
DOUTx+ WITH DINx = VCC
OR DOUTx– WITH DINx = GND
50%
1.2V
1.2V
VOL
tPLZ
Figure 6. Driver Three-State Delay Waveforms
Rev. 0 | Page 5 of 12
tPZL
08085-006
50%
DOUTx+ WITH DINx = GND
OR DOUTx– WITH DINx = VCC
ADN4665
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VCC to GND
Input Voltage (DINx) to GND
Enable Input Voltage (EN, EN) to GND
Output Voltage (DOUTx+, DOUTx−) to GND
Short-Circuit Duration (DOUTx+, DOUTx−) to GND
Industrial Operating Temperature Range
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
θJA Thermal Impedance
TSSOP Package
SOIC Package
Reflow Soldering Peak Temperature (10 sec)
Rating
−0.3 V to +4 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
Continuous
−40°C to +85°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
150.4°C/W
125°C/W
260°C max
Rev. 0 | Page 6 of 12
ADN4665
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DIN1 1
16
VCC
DOUT1+ 2
15
DIN4
DOUT1– 3
14
DOUT4+
ADN4665
13 DOUT4–
TOP VIEW
DOUT2– 5 (Not to Scale) 12 EN
DOUT2+ 6
11 DOUT3–
DIN2 7
10
DOUT3+
GND 8
9
DIN3
08085-007
EN 4
Figure 7. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
Mnemonic
DIN1
DOUT1+
3
DOUT1−
4
EN
5
DOUT2−
6
DOUT2+
7
8
9
10
DIN2
GND
DIN3
DOUT3+
11
DOUT3−
12
EN
13
DOUT4−
14
DOUT4+
15
16
DIN4
VCC
Description
Driver Channel 1 Logic Input.
Channel 1 Noninverting Output Current Driver. When DIN1 is high, current flows out of DOUT1+. When DIN1 is low,
current flows into DOUT1+.
Channel 1 Inverting Output Current Driver. When DIN1 is high, current flows into DOUT1−. When DIN1 is low, current
flows out of DOUT1−.
Active High Enable and Power-Down Input (3 V TTL/CMOS). If EN is held low or open circuit, EN enables the
drivers when high and disables the drivers when low.
Channel 2 Inverting Output Current Driver. When DIN2 is high, current flows into DOUT2−. When DIN2 is low, current
flows out of DOUT2−.
Channel 2 Noninverting Output Current Driver. When DIN2 is high, current flows out of DOUT2+. When DIN2 is low,
current flows into DOUT2+.
Driver Channel 2 Logic Input.
Ground Reference Point for All Circuitry on the Part.
Driver Channel 3 Logic Input.
Channel 3 Noninverting Output Current Driver. When DIN3 is high, current flows out of DOUT3+. When DIN3 is low,
current flows into DOUT3+.
Channel 3 Inverting Output Current Driver. When DIN3 is high, current flows into DOUT3−. When DIN3 is low, current
flows out of DOUT3−.
Active Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). If EN is held high, EN enables the
drivers when low or open circuit and disables the drivers and powers down the device when high.
Channel 4 Inverting Output Current Driver. When DIN4 is high, current flows into DOUT4−. When DIN4 is low, current
flows out of DOUT4−.
Channel 4 Noninverting Output Current Driver. When DIN4 is high, current flows out of DOUT4+. When DIN4 is low,
current flows into DOUT4+.
Driver Channel 4 Logic Input.
Power Supply Input. This part can be operated from 3.0 V to 3.6 V. The supply should be decoupled with a 10 μF
solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND.
Rev. 0 | Page 7 of 12
ADN4665
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.0
VCC = 3.3V
TA = 25°C
VCC = 3.0V TO 3.6V
TA = 25°C
1.8
DOUTx+ = +3.3V
2.5
1.6
DOUTx+
DOUT (V)
DOUT (V)
2.0
1.5
DOUT = +3.0V
DOUT = +3.3V
DOUT = +3.6V
DOUT = –3.0V
DOUT = –3.3V
DOUT = –3.6V
1.4
1.2
DOUTx–
1.0
1.0
0.5
0
1
2
3
4
5
6
7
RL (kΩ)
0.6
08085-008
0
0
Figure 8. Single-Ended Driver Output Voltage vs. Load Resistance
50
100
150
200
RL (Ω)
250
300
Figure 9. Driver Output vs. Load Resistance
Rev. 0 | Page 8 of 12
350
400
08085-009
0.8
DOUTx– = –3.3V
ADN4665
THEORY OF OPERATION
The ADN4665 is a quad line driver for low voltage differential
signaling. It takes a single-ended 3 V logic signal and converts
it to a differential current output. The data can then be transmitted for considerable distances, over media such as a twisted pair
cable or PCB backplane, to an LVDS receiver such as the ADN4666,
where it develops a voltage across a termination resistor, RT. This
resistor is chosen to match the characteristic impedance of the
medium, typically around 100 Ω. The differential voltage is
detected by the receiver and converted back into a single-ended
logic signal.
This is similar to emitter-coupled logic (ECL) and positive
emitter-coupled logic (PECL), but without the high quiescent
current of ECL and PECL.
When DINx is high (Logic 1), current flows out of the DOUTx+
pin (current source) through RT and back into the DOUTx− pin
(current sink). At the receiver, this current develops a positive
differential voltage across RT (with respect to the inverting input)
and results in a Logic 1 at the receiver output. When DINx is low,
DOUTx+ sinks current and DOUTx− sources current; a negative differential voltage across RT results in a Logic 0 at the receiver output.
Table 5. Enable Inputs Truth Table
Current-mode drivers offer considerable advantages over voltagemode drivers such as RS-422 drivers. The operating current
remains fairly constant with increased switching frequency,
whereas the operating current of voltage-mode drivers increases
exponentially in most cases. This is caused by the overlap current as
internal gates switch between high and low, which causes currents
to flow from the device power supply to ground. A current-mode
device simply reverses a constant current between its two outputs,
with no significant overlap currents.
The active high and active low enable inputs deactivate all the
current drivers when the drivers are in the disabled state. This
also powers down the device and reduces the current consumption
from typically 23 mA to typically 2.6 mA. A truth table for the
enable inputs is shown in Table 5.
Pin Logic Level
DINx
EN
EN
Low
Low
Low
High
High
1
1
High
Low
Low
Low
Low
X
Low
High
Low
High
DOUTx+
DOUTx−
Inactive
ISINK
ISOURCE
ISINK
ISOURCE
Inactive
ISOURCE
ISINK
ISOURCE
ISINK
X = don’t care.
APPLICATIONS INFORMATION
Figure 10 shows a typical application for point-to-point data
transmission using the ADN4665 as the driver.
1/4 ADN4665
RECEIVER
EN
EN
EN
EN
DOUTx+
RT
100Ω
DINx
Rev. 0 | Page 9 of 12
RINy+
DOUTx–
GND
ROUTy
RINy–
GND
Figure 10. Typical Application Circuit
08085-010
The output drive current is between ±2.5 mA and ±4.5 mA
(typically ±3.5 mA), developing between ±250 mV and ±450 mV
across a 100 Ω termination resistor. The received voltage is centered
around the receiver offset of 1.25 V. Therefore, the noninverting
receiver input is typically 1.375 V (that is, 1.2 V + [350 mV/2]) and
the inverting receiver input is 1.025 V (that is, 1.2 V − [350 mV/2])
for Logic 1. For Logic 0, the inverting and noninverting output
voltages are reversed. Note that because the differential voltage
reverses polarity, the peak-to-peak voltage swing across RT is
twice the differential voltage.
ENABLE INPUTS
ADN4665
OUTLINE DIMENSIONS
10.00 (0.3937)
9.80 (0.3858)
9
16
4.00 (0.1575)
3.80 (0.1496)
1
6.20 (0.2441)
5.80 (0.2283)
8
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 11. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 12. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADN4665ARZ 1
ADN4665ARZ-REEL71
ADN4665ARUZ1
ADN4665ARUZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
Z = RoHS Compliant Part.
Rev. 0 | Page 10 of 12
Package Option
R-16
R-16
RU-16
RU-16
ADN4665
NOTES
Rev. 0 | Page 11 of 12
ADN4665
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08085-0-5/09(0)
Rev. 0 | Page 12 of 12
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