Cypress CY7C1482V33 72-mbit (2 m x 36/4 m x 18/1 m x 72) pipelined sync sram Datasheet

CY7C1480V33
CY7C1482V33
CY7C1486V33
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined Sync SRAM
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM
Features
Functional Description[1]
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250, 200, and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
3.3V core power supply
■
2.5V/3.3V I/O operation
■
Fast clock-to-output times
❐ 3.0 ns (for 250 MHz device)
■
Provide high performance 3-1-1-1 access rate
■
User selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed writes
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1480V33, CY7C1482V33 available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA
package. CY7C1486V33 available in Pb-free and non-Pb-free
209-ball FBGA package
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
“ZZ” Sleep Mode option
The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM
integrates 2 M × 36/4 M × 18/1 M × 72 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at the rising edge of
the clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see Pin Definitions on page 8 and Truth Table on
page 11 for further details). Write cycles can be one to two or four
bytes wide as controlled by the byte write control inputs. GW
when active LOW causes all bytes to be written.
The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates
from a +3.3 V core power supply while all outputs may operate
with either a +2.5 or +3.3 V supply. All inputs and outputs are
JEDEC standard JESD8-5 compatible.
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
3.0
3.0
3.4
ns
Maximum Operating Current
500
500
450
mA
Maximum CMOS Standby Current
120
120
120
mA
Note
1. For best practices recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document Number: 38-05283 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 14, 2011
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Logic Block Diagram – CY7C1480V33 (2 M × 36)
A 0, A1, A
ADDRESS
REGISTER
2
A [1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
LOGIC
ADSC
Q0
ADSP
BW D
DQ D ,DQP D
BYTE
WRITE REGISTER
DQ D ,DQPD
BYTE
WRITE DRIVER
BW C
DQ C ,DQP C
BYTE
WRITE REGISTER
DQ C ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE DRIVER
BW B
BW A
BWE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
DQ A ,DQP A
BYTE
WRITE DRIVER
DQ A ,DQP A
BYTE
WRITE REGISTER
GW
CE 1
CE 2
CE 3
OE
MEMORY
ARRAY
ENABLE
REGISTER
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Logic Block Diagram – CY7C1482V33 (4 M × 18)
A0, A1, A
ADDRESS
REGISTER
2
MODE
A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BW B
DQ B, DQP B
WRITE DRIVER
DQ B, DQP B
WRITE REGISTER
MEMORY
ARRAY
BW A
DQ A, DQP A
WRITE DRIVER
DQ A, DQP A
WRITE REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
E
BWE
GW
CE 1
CE2
CE3
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document Number: 38-05283 Rev. *K
Page 2 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Logic Block Diagram – CY7C1486V33 (1 M × 72)
ADDRESS
REGISTER
A 0, A1,A
A[1:0]
MODE
Q1
BINARY
COUNTER
CLR
Q0
ADV
CLK
ADSC
ADSP
BW H
DQ H , DQPH
WRITE DRIVER
DQ H , DQPH
WRITE DRIVER
BW G
DQ F, DQPF
WRITE DRIVER
DQ G , DQPG
WRITE DRIVER
BW F
DQ F, DQPF
WRITE DRIVER
DQ F, DQPF
WRITE DRIVER
BW E
DQ E , DQPE
WRITE DRIVER
DQ
E , DQP
BYTE
“a” E
WRITE DRIVER
BW D
DQ D , DQPD
WRITE DRIVER
DQ D , DQPD
WRITE DRIVER
BW C
DQ C, DQPC
WRITE DRIVER
DQ C, DQPC
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ZZ
DQ B , DQPB
WRITE DRIVER
DQ B , DQPB
WRITE DRIVER
OUTPUT
BUFFERS
E
DQ A , DQPA
WRITE DRIVER
DQ A , DQPA
WRITE DRIVER
ENABLE
REGISTER
OUTPUT
REGISTERS
PIPELINED
ENABLE
INPUT
REGISTERS
DQs
DQP A
DQP B
DQP C
DQP D
DQP E
DQP F
DQP G
DQP H
SLEEP
CONTROL
Document Number: 38-05283 Rev. *K
Page 3 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Single Write Accesses Initiated by ADSP ................... 9
Single Write Accesses Initiated by ADSC ................. 10
Burst Sequences ....................................................... 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table
(MODE = Floating or VDD) ............................................. 10
Linear Burst Address Table
(MODE = GND) ................................................................ 10
ZZ Mode Electrical Characteristics ............................... 10
Truth Table ...................................................................... 11
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
TAP Controller State Diagram ....................................... 14
Test Access Port (TAP) ............................................. 14
TAP Controller Block Diagram ...................................... 14
PERFORMING A TAP RESET .................................. 14
TAP REGISTERS ...................................................... 14
TAP Instruction Set ................................................... 15
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 17
3.3 V TAP AC Output Load Equivalent ......................... 17
2.5 V TAP AC Test Conditions ....................................... 17
2.5 V TAP AC Output Load Equivalent ......................... 17
Document Number: 38-05283 Rev. *K
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 17
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 18
Identification Codes ....................................................... 18
Boundary Scan Exit Order (2 M × 36) ........................... 19
Boundary Scan Exit Order (4 M × 18) ........................... 19
Boundary Scan Exit Order (1 M × 72) ........................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 25
Read Cycle Timing .................................................... 25
Write Cycle Timing .................................................... 26
Read/Write Cycle Timing ........................................... 27
ZZ Mode Timing ........................................................ 28
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Package Diagrams .......................................................... 30
Acronyms ........................................................................ 33
Document Conventions ................................................. 33
Units of Measure ....................................................... 33
Document History Page ................................................. 34
Sales, Solutions, and Legal Information ...................... 36
Worldwide Sales and Design Support ....................... 36
Products .................................................................... 36
PSoC Solutions ......................................................... 36
Page 4 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Pin Configurations
NC
NC
NC
CY7C1482V33
(4 M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document Number: 38-05283 Rev. *K
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1480V33
(2 M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP Pinout
Page 5 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Pin Configurations (continued)
165-ball FBGA (15 × 17 × 1.4 mm) Pinout
CY7C1480V33 (2 M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
2
3
4
5
6
7
8
9
10
11
BWE
ADSC
ADV
A
NC
NC/576M
CE1
BWC
BWB
CE3
NC/144M
A
CE2
BWD
BWA
CLK
GW
ADSP
DQPC
DQC
NC
DQC
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VDD
OE
VSS
VDD
A
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
DQC
NC
DQD
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
TCK
A
A
A
A
A
A0
CY7C1482V33 (4 M × 18)
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
R
3
4
5
6
BWB
NC
CE3
NC
BWA
VSS
VDD
VSS
VSS
NC/144M
A
CE1
CE2
NC
NC
NC
DQB
VDDQ
VDDQ
7
8
9
10
11
A
CLK
BWE
GW
ADSC
OE
ADV
ADSP
A
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC/1G
NC
A
NC/576M
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
DQB
DQB
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document Number: 38-05283 Rev. *K
Page 6 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Pin Configurations (continued)
209-ball FBGA (14 × 22 × 1.76 mm) Pinout
CY7C1486V33 (1 M × 72)
1
2
3
4
5
6
7
8
9
10
11
A
DQG
DQG
A
CE2
ADSP
ADSC
ADV
CE3
A
DQB
DQB
B
DQG
DQG
BWSC
BWSG NC/288M
BWE
A
BWSB
BWSF
DQB
DQB
C
DQG
DQG
BWSH
BWSD NC/144M
CE1
NC/576M BWSE
BWSA
DQB
DQB
D
DQG
DQG
VSS
NC
NC/1G
OE
GW
NC
VSS
DQB
DQB
E
DQPG
DQPC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPF
DQPB
F
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
G
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
H
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
J
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
K
NC
NC
CLK
NC
VSS
VSS
VSS
NC
NC
NC
NC
L
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
M
DQH
DQH
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQA
DQA
N
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
P
DQH
DQH
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQA
DQA
R
DQPD
DQPH VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPA
T
DQD
DQD
VSS
NC
NC
MODE
NC
NC
VSS
DQE
DQE
U
DQD
DQD
A
A
A
A
A
A
A
DQE
DQE
V
DQD
DQD
A
A
A
A1
A
A
A
DQE
DQE
W
DQD
DQD
TMS
TDI
A
A0
A
TCK
DQE
DQE
Document Number: 38-05283 Rev. *K
TDO
DQPE
Page 7 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Pin Definitions
Pin Name
I/O
Description
A0, A1, A
InputSynchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
active. A1: A0 are fed to the two-bit counter.
BWA,BWB,BWC,BWD,
BWE,BWF,BWG,BWH
InputSynchronous
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (all bytes are written, regardless of the values on BWX and
BWE).
BWE
InputSynchronous
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW during a burst operation.
CE1
InputSynchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is
HIGH. CE1 is sampled only when a new external address is loaded.
CE2
InputSynchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only when
a new external address is loaded.
CE3
InputSynchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when
a new external address is loaded.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins.
Asynchronous When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
ADV
InputSynchronous
Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
InputZZ “Sleep” Input, Active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPs
I/OSynchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
VDD
Power Supply
Power supply inputs to the core of the device.
Ground
VSS
VSSQ
[2]
VDDQ
IO Ground
Ground for the core of the device.
Ground for the I/O circuitry.
IO Power Supply Power supply for the I/O circuitry.
Note
2. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry.
Document Number: 38-05283 Rev. *K
Page 8 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Pin Definitions (continued)
Pin Name
I/O
Description
Input Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and must remain
static during device operation. Mode Pin has an internal pull up.
TDO
JTAG Serial
Output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not used, this pin must be disconnected. This pin is not available on TQFP
packages.
TDI
JTAG Serial
Input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TMS
JTAG Serial
Input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TCK
JTAG Clock
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
connected to VSS. This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
MODE
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.0 ns (250 MHz device).
The CY7C1480V33/CY7C1482V33/CY7C1486V33 supports
secondary cache in systems using either a linear or interleaved
burst sequence. The interleaved burst order supports Pentium
and i486 processors. The linear burst sequence is suited for
processors that use a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is controlled
by the ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs (A) is stored
into the address advancement logic and the Address Register
while being presented to the memory array. The corresponding
data is allowed to propagate to the input of the Output Registers.
At the rising edge of the next clock the data is allowed to
propagate through the output register and onto the data bus
Document Number: 38-05283 Rev. *K
within 3.0 ns (250-MHz device) if OE is active LOW. The only
exception occurs when the SRAM is emerging from a deselected
state to a selected state, its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive single
read cycles are supported. After the SRAM is deselected at clock
rise by the chip select and either ADSP or ADSC signals, its
output tri-states immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The write signals
(GW, BWE, and BWX) and ADV inputs are ignored during this
first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals.
The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides
byte write capability that is described in the Truth Table for
Read/Write on page 12. Asserting the Byte Write Enable input
(BWE) with the selected Byte Write (BWX) input, will selectively
write to only the desired bytes. Bytes not selected during a Byte
Write operation will remain unaltered. A synchronous self-timed
Write mechanism has been provided to simplify the Write
operations.
Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a
common I/O device, the Output Enable (OE) must be deasserted
HIGH before presenting data to the DQs inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a Write cycle is detected,
regardless of the state of OE.
Page 9 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Single Write Accesses Initiated by ADSC
Sleep Mode
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a Byte Write is conducted, only the selected
bytes are written. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed Write
mechanism has been provided to simplify the Write operations.
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a
common I/O device, the Output Enable (OE) must be deasserted
HIGH before presenting data to the DQs inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a Write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides a
two-bit wraparound counter, fed by A1: A0, that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00
01
10
11
01
10
11
00
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.
Fourth
Address
A1: A0
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ Active to Sleep current
tRZZI
ZZ Inactive to exit Sleep current
Document Number: 38-05283 Rev. *K
Min
Max
Unit
–
120
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
This parameter is sampled
0
–
ns
Page 10 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Truth Table
The Truth Table for CY7C1480V33, CY7C1482V33, and CY7C1486V33 follows.[3, 4, 5, 6, 7]
Operation
Add. Used
Deselect Cycle, Power Down
None
CE1 CE2 CE3
H
X
X
ZZ
ADSP
ADSC
ADV
WRITE
OE
CLK
DQ
L
X
L
X
X
X
L–H
Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L–H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L–H
Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L–H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
X
X
L–H
Tri-State
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H
Tri-State
WRITE Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H
D
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H
Tri-State
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tri-State
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tri-State
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tri-State
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tri-State
WRITE Cycle,Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
WRITE Cycle,Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tri-state. OE is a “don't care”
for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05283 Rev. *K
Page 11 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Truth Table for Read/Write
The following is a Truth Table for Read/Write for the CY7C1480V33.[8]
Function
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – (DQA and DQPA)
H
L
H
H
H
L
Write Byte B – (DQB and DQPB)
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – (DQC and DQPC)
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – (DQD and DQPD)
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Truth Table for Read/Write
The following is a Truth Table for Read/Write for the CY7C1482V33.[8]
Function
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
H
L
H
L
H
L
L
H
Write Bytes B, A
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Note
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Document Number: 38-05283 Rev. *K
Page 12 of 36
[+] Feedback
CY7C1480V33
CY7C1482V33
CY7C1486V33
Truth Table for Read/Write
The following is a Truth Table for Read/Write for the CY7C1486V33.[9]
Function
GW
BWE
Read
H
H
X
Read
H
L
All BW = H
Write Byte x – (DQx and DQPx)
H
L
L
Write All Bytes
H
L
All BW = L
Write All Bytes
L
X
X
BWX
Note
9. BWx represents any byte write signal BW[0..7].To enable any byte write BWx, a Logic LOW signal should be applied at clock rise. Any number of bye writes can be
enabled at the same time for any given write.
Document Number: 38-05283 Rev. *K
Page 13 of 36
[+] Feedback
CY7C1480V33
CY7C1482V33
CY7C1486V33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The
CY7C1480V33/CY7C1482V33/CY7C1486V33
incorporates a serial boundary scan test access port (TAP).
This port operates in accordance with IEEE Standard
1149.1-1990 but does not have the set of functions required
for full 1149.1 compliance. These functions from the IEEE
specification are excluded because their inclusion places an
added delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 3.3 V or 2.5 V
I/O logic levels.
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The CY7C1480V33/CY7C1482V33/CY7C1486V33 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
The TDI ball serially inputs information into the registers and
can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction
that is loaded into the TAP instruction register. For information
about loading the instruction register, see the TAP Controller
State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See TAP Controller Block Diagram.)
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be
connected to VDD through a pull up resistor. TDO must be left
unconnected. At power up, the device comes up in a reset
state, which will not interfere with the operation of the device.
The TDO output ball serially clocks data-out from the registers.
The output is active depending upon the current state of the
TAP state machine. The output changes on the falling edge of
TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
0
Bypass Register
2 1 0
0
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
1
0
TDO
x . . . . . 2 1 0
SHIFT-IR
1
Selection
Circuitry
Identification Register
0
SHIFT-DR
Instruction Register
31 30 29 . . . 2 1 0
CAPTURE-IR
0
Boundary Scan Register
0
1
EXIT1-DR
1
EXIT1-IR
0
1
0
PAUSE-DR
0
TCK
PAUSE-IR
1
0
TM S
TAP CONTROLLER
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
TDI
Selection
Circuitry
0
CAPTURE-DR
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document Number: 38-05283 Rev. *K
Performing a TAP Reset
Perform a RESET by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Page 14 of 36
[+] Feedback
CY7C1480V33
CY7C1482V33
CY7C1486V33
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. At power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The ×36 configuration has a
73-bit-long register, and the ×18 configuration has a 54-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Identification
Codes on page 18. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
Document Number: 38-05283 Rev. *K
rather, it performs a capture of the IO ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction, which is to be
executed whenever the instruction register is loaded with all
zeros. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-zero instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is in a test logic reset
state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
Be aware that the TAP controller clock can only operate at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured. Repeatable
results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
Page 15 of 36
[+] Feedback
CY7C1480V33
CY7C1482V33
CY7C1486V33
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
After the data is captured, the data can be shifted out by putting
the TAP into the Shift-DR state. This places the boundary scan
register between the TDI and TDO balls.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
TAP Timing
1
2
3
Test Clock
(TCK )
t TH
t TM SS
t TM SH
t TDIS
t TDIH
t
TL
4
5
6
t CY C
Test M ode Select
(TM S)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CA RE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range[10, 11]
Parameter
Description
Min
Max
Unit
50
–
ns
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH Time
20
–
ns
tTL
TCK Clock LOW Time
20
–
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
5
–
ns
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
Hold Times
Notes
10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 38-05283 Rev. *K
Page 16 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input pulse levels................................................ VSS to 2.5 V
Input rise and fall times ...................................................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels ......................................... 1.5 V
Input timing reference levels........................................ 1.25 V
Output reference levels ................................................ 1.5 V
Output reference levels ............................................... 1.25 V
Test load termination supply voltage ............................ 1.5 V
Test load termination supply voltage ........................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
20pF
Z O= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 to 3.6 V unless otherwise noted)[12]
Parameter
Description
Min
Max
Unit
IOH = –4.0 mA, VDDQ = 3.3 V
Test Conditions
2.4
–
V
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VOH1
Output HIGH Voltage
VOH2
Output HIGH Voltage
VOL1
Output LOW Voltage
VOL2
Output LOW Voltage
VDDQ = 2.5 V
–
0.2
V
VIH
Input HIGH Voltage
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
IX
Input Load Current
–5
5
µA
GND < VIN < VDDQ
Identification Register Definitions
Instruction Field
CY7C1480V33 CY7C1482V33 CY7C1486V33
(2 M × 36)
(4 M × 18)
(1 M × 72)
Revision Number (31:29)
000
Device Depth (28:24)
Architecture/Memory Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
000
Describes the version number
01011
01011
01011
000000
000000
000000
Defines memory type and architecture
110100
Defines width and density
100100
010100
00000110100
00000110100
1
1
ID Register Presence Indicator (0)
000
Description
Reserved for internal use
00000110100 Enables unique identification of SRAM
vendor
1
Indicates the presence of an ID register
Notes
12. All voltages referenced to VSS (GND).
Document Number: 38-05283 Rev. *K
Page 17 of 36
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CY7C1482V33
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Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 18)
Bit Size (× 72)
3
3
3
Instruction
Bypass
1
1
1
ID
32
32
32
Boundary Scan Order – 165-ball FBGA
73
54
–
Boundary Scan Order – 209-ball BGA
–
–
112
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the IO ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document Number: 38-05283 Rev. *K
Page 18 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Boundary Scan Exit Order (2 M × 36)
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
1
C1
21
R3
41
L10
61
B8
2
D1
22
P2
42
K11
62
A7
3
E1
23
R4
43
J11
63
B7
4
D2
24
P6
44
K10
64
B6
5
E2
25
R6
45
J10
65
A6
6
F1
26
N6
46
H11
66
B5
7
G1
27
P11
47
G11
67
A5
8
F2
28
R8
48
F11
68
A4
9
G2
29
P3
49
E11
69
B4
10
J1
30
P4
50
D10
70
B3
11
K1
31
P8
51
D11
71
A3
12
L1
32
P9
52
C11
72
A2
73
B2
13
J2
33
P10
53
G10
14
M1
34
R9
54
F10
15
N1
35
R10
55
E10
16
K2
36
R11
56
A10
17
L2
37
N11
57
B10
18
M2
38
M11
58
A9
19
R1
39
L11
59
B9
20
R2
40
M10
60
A8
Boundary Scan Exit Order (4 M × 18)
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
1
D2
19
R8
37
C11
2
E2
20
P3
38
A11
3
F2
21
P4
39
A10
4
G2
22
P8
40
B10
5
J1
23
P9
41
A9
6
K1
24
P10
42
B9
7
L1
25
R9
43
A8
8
M1
26
R10
44
B8
9
N1
27
R11
45
A7
10
R1
28
M10
46
B7
11
R2
29
L10
47
B6
12
R3
30
K10
48
A6
13
P2
31
J10
49
B5
14
R4
32
H11
50
A4
15
P6
33
G11
51
B3
16
R6
34
F11
52
A3
17
N6
35
E11
53
A2
18
P11
36
D11
54
B2
Document Number: 38-05283 Rev. *K
Page 19 of 36
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CY7C1482V33
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Boundary Scan Exit Order (1 M × 72)
Bit #
209-ball ID
Bit #
209-ball ID
Bit #
209-ball ID
Bit #
209-ball ID
1
A1
29
T1
57
V10
85
C11
2
A2
30
T2
58
U11
86
C10
3
B1
31
U1
59
U10
87
B11
4
B2
32
U2
60
T11
88
B10
5
C1
33
V1
61
T10
89
A11
6
C2
34
V2
62
R11
90
A10
7
D1
35
W1
63
R10
91
A9
8
D2
36
W2
64
P11
92
U8
9
E1
37
T6
65
P10
93
A7
10
E2
38
V3
66
N11
94
A5
11
F1
39
V4
67
N10
95
A6
12
F2
40
U4
68
M11
96
D6
13
G1
41
W5
69
M10
97
B6
14
G2
42
V6
70
L11
98
D7
15
H1
43
W6
71
L10
99
K3
16
H2
44
U3
72
P6
100
A8
17
J1
45
U9
73
J11
101
B4
18
J2
46
V5
74
J10
102
B3
19
L1
47
U5
75
H11
103
C3
20
L2
48
U6
76
H10
104
C4
21
M1
49
W7
77
G11
105
C8
22
M2
50
V7
78
G10
106
C9
23
N1
51
U7
79
F11
107
B9
24
N2
52
V8
80
F10
108
B8
25
P1
53
V9
81
E10
109
A4
26
P2
54
W11
82
E11
110
C6
27
R2
55
W10
83
D11
111
B7
28
R1
56
V11
84
D10
112
A3
Document Number: 38-05283 Rev. *K
Page 20 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Maximum Ratings
DC Input Voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage......................................... > 2001 V
(MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Operating Range
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Ambient
Temperature
Commercial 0 C to +70 C
Industrial
–40 C to +85C
Range
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tri-State .........................................–0.5 V to VDDQ + 0.5 V
VDD
VDDQ
3.3 V– 5% /
+ 10%
2.5 V – 5%
to VDD
Electrical Characteristics
Over the Operating Range[13, 14]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
IO Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
VIL
IX
Input HIGH
Input LOW
Voltage[13]
Voltage[13]
Input Leakage Current
except ZZ and MODE
Test Conditions
3.135
3.6
V
VDD
V
For 2.5 V IO
2.375
2.625
V
For 3.3 V IO, IOH = –4.0 mA
2.4
–
V
For 2.5 V IO, IOH = –1.0 mA
2.0
–
V
For 3.3 V IO, IOL = 8.0 mA
–
0.4
V
For 2.5 V IO, IOL = 1.0 mA
–
0.4
V
For 3.3 V IO
2.0
VDD + 0.3 V
V
For 2.5 V IO
1.7
VDD + 0.3 V
V
For 3.3 V IO
–0.3
0.8
V
For 2.5 V IO
–0.3
0.7
V
–5
5
A
GND  VI  VDDQ
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
–
30
A
–5
5
A
4.0-ns cycle, 250 MHz
–
500
mA
5.0-ns cycle, 200 MHz
–
500
mA
6.0-ns cycle, 167 MHz
–
450
mA
4.0-ns cycle, 250 MHz
–
245
mA
5.0-ns cycle, 200 MHz
–
245
mA
Input = VDD
Output Leakage Current GND  VI  VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN  VIH or VIN  VIL,
f = fMAX = 1/tCYC
ISB2
Unit
3.135
IOZ
ISB1
Max
For 3.3 V IO
Input Current of MODE Input = VSS
Input Current of ZZ
Min
6.0-ns cycle, 167 MHz
VDD = Max, Device Deselected,
Automatic CE
All speeds
Power Down
VIN  0.3 V or VIN > VDDQ – 0.3 V, f = 0
Current—CMOS Inputs
–
245
mA
–
120
mA
Notes
13. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2). Undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
14. Power up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05283 Rev. *K
Page 21 of 36
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CY7C1482V33
CY7C1486V33
Electrical Characteristics (continued)
Over the Operating Range[13, 14]
Parameter
ISB3
ISB4
Min
Max
Unit
Automatic CE
VDD = Max, Device Deselected, or
Power Down
VIN  0.3 V or VIN > VDDQ – 0.3 V,
Current—CMOS Inputs f = fMAX = 1/tCYC
Description
Test Conditions
4.0-ns cycle, 250 MHz
–
245
mA
5.0-ns cycle, 200 MHz
–
245
mA
6.0-ns cycle, 167 MHz
–
245
mA
Automatic CE
Power Down
Current—TTL Inputs
All speeds
–
135
mA
VDD = Max, Device Deselected,
VIN  VIH or VIN  VIL, f = 0
Capacitance[15]
Parameter
Description
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
100-pin TQFP 165-ball FBGA 209-ball FBGA Unit
Max
Max
Max
6
6
6
pF
5
5
5
pF
Control Input Capacitance
8
8
8
pF
Clock Input Capacitance
6
6
6
pF
Input/Output Capacitance
5
5
5
pF
CADDRESS
Address Input Capacitance
CDATA
Data Input Capacitance
CCTRL
CCLK
CI/O
Thermal Resistance[15]
Parameter
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance,
according to EIA/JESD51.
100-pin TQFP 165-ball FBGA 209-ball FBGA Unit
Package
Package
Package
24.63
16.3
15.2
C/W
2.28
2.1
1.7
C/W
Note
15. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05283 Rev. *K
Page 22 of 36
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CY7C1482V33
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AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
R = 351 
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
GND
5 pF
VL = 1.5 V
(a)
ALL INPUT PULSES
VDDQ
 1 ns
 1 ns
(c)
(b)
2.5 V I/O Test Load
R = 1667 
2.5V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
R = 1538 
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
GND
5 pF
VL = 1.25 V
(a)
ALL INPUT PULSES
VDDQ
 1 ns
 1 ns
(c)
(b)
Switching Characteristics
Over the Operating Range[16, 17]
Description
Parameter
tPOWER
VDD(Typical) to the First Access[18]
250 MHz
200 MHz
167 MHz
Unit
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
ms
Clock
tCYC
Clock Cycle Time
4.0
–
5.0
–
6.0
–
ns
tCH
Clock HIGH
2.0
–
2.0
–
2.4
–
ns
tCL
Clock LOW
2.0
–
2.0
–
2.4
–
ns
Output Times
tCO
Data Output Valid After CLK Rise
–
3.0
–
3.0
–
3.4
ns
tDOH
Data Output Hold After CLK Rise
1.3
–
1.3
–
1.5
–
ns
Z[19, 20, 21]
tCLZ
Clock to Low
1.3
–
1.3
–
1.5
–
ns
tCHZ
Clock to High Z[19, 20, 21]
–
3.0
–
3.0
–
3.4
ns
tOEV
OE LOW to Output Valid
–
3.0
–
3.0
–
3.4
ns
0
–
0
–
0
–
ns
–
3.0
–
3.0
–
3.4
ns
tOELZ
tOEHZ
OE LOW to Output Low
Z[19, 20, 21]
OE HIGH to Output High
Z[19, 20, 21]
Notes
16. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
17. Test conditions shown in (a) of AC Test Loads and Waveforms unless otherwise noted.
18. This part has an internal voltage regulator; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
19. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 23. Transition is measured ±200 mV
from steady-state voltage.
20. At any possible voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z before Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document Number: 38-05283 Rev. *K
Page 23 of 36
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CY7C1482V33
CY7C1486V33
Switching Characteristics (continued)
Over the Operating Range[16, 17]
Parameter
Description
250 MHz
200 MHz
167 MHz
Min
Max
Min
Max
Min
Max
Unit
Setup Times
tAS
Address Setup Before CLK Rise
1.4
–
1.4
–
1.5
–
ns
tADS
ADSC, ADSP Setup Before CLK Rise
1.4
–
1.4
–
1.5
–
ns
tADVS
ADV Setup Before CLK Rise
1.4
–
1.4
–
1.5
–
ns
tWES
GW, BWE, BWX Setup Before CLK Rise
1.4
–
1.4
–
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.4
–
1.4
–
1.5
–
ns
tCES
Chip Enable Setup Before CLK Rise
1.4
–
1.4
–
1.5
–
ns
tAH
Address Hold After CLK Rise
0.4
–
0.4
–
0.5
–
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.4
–
0.4
–
0.5
–
ns
tADVH
ADV Hold After CLK Rise
0.4
–
0.4
–
0.5
–
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.4
–
0.4
–
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.4
–
0.4
–
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.4
–
0.4
–
0.5
–
ns
Hold Times
Document Number: 38-05283 Rev. *K
Page 24 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Switching Waveforms
Read Cycle Timing[22]
t CYC
CLK
t
t
ADS
CH
t
CL
t
ADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t WES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
t CES
Deselect
cycle
tCEH
CE
t ADVS
tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
Document Number: 38-05283 Rev. *K
Page 25 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Switching Waveforms (continued)
Write Cycle Timing[23, 24]
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t WES tWEH
GW
t CES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
24. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW.
Document Number: 38-05283 Rev. *K
Page 26 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Switching Waveforms (continued)
Read/Write Cycle Timing[25, 26, 27]
tCYC
CLK
tCL
tCH
t ADS
tADH
t AS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
t WES tWEH
BWE,
BW X
t CES
tCEH
CE
ADV
OE
t DS
tCO
tDH
t OELZ
Data In (D)
High-Z
tOEHZ
tCLZ
Data Out (Q)
High-Z
Q(A1)
D(A5)
D(A3)
Q(A4)
Q(A2)
Back-to-Back READs
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
26. The data bus (Q) remains in high Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
27. GW is HIGH.
Document Number: 38-05283 Rev. *K
Page 27 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Switching Waveforms (continued)
ZZ Mode Timing[28, 29]
CLK
t
ZZ
I
t ZZREC
ZZ
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
28. Device must be deselected when entering ZZ mode. See Truth Table on page 11 for all possible signal conditions to deselect the device.
29. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05283 Rev. *K
Page 28 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Ordering Information
Speed
(MHz)
Ordering Code
Package
Diagram
Part and Package Type
Operating
Range
167
CY7C1480V33-167AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
200
CY7C1480V33-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY 7C 1480 V33 - XXX AX C
Temperature Range:
C = Commercial
Package Type:
AX = 100-pin TQFP (Pb-free)
Frequency Range: XXX = 167 MHz or 200 MHz
VDD = 3.3 V
1480 = SCD, 2 Mb × 36 (72 Mb)
Marketing Code: 7C = SRAMs
Company ID: CY = Cypress
Document Number: 38-05283 Rev. *K
Page 29 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Package Diagrams
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050
51-85050 *D
Document Number: 38-05283 Rev. *K
Page 30 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Package Diagrams (continued)
Figure 2. 165-Ball FBGA (15 × 17 × 1.4 mm), 51-85165
51-85165 *B
Document Number: 38-05283 Rev. *K
Page 31 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Package Diagrams (continued)
Figure 3. 209-ball FBGA (14 × 22 × 1.76 mm), 51-85167
51-85167 *A
Document Number: 38-05283 Rev. *K
Page 32 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Acronyms
Document Conventions
Acronym
Description
Units of Measure
BGA
ball grid array
CMOS
complementary metal oxide semiconductor
°C
degree Celcius
FBGA
fine-pitch ball grid array
µA
micro Amperes
I/O
input/output
mA
milli Amperes
JTAG
Joint Test Action Group
mm
milli meter
LSB
least significant bit
ms
milli seconds
MSB
most significant bit
MHz
Mega Hertz
OE
output enable
ns
nano seconds
SRAM
static random access memory

Ohms
TAP
test access port
%
percent
TCK
test clock
pF
pico Farad
TDI
test data-in
V
Volts
TDO
test data-out
W
Watts
TMS
test mode select
TQFP
thin quad flat pack
TTL
transistor transistor logic
WE
write enable
Document Number: 38-05283 Rev. *K
Symbol
Unit of Measure
Page 33 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Document History Page
Document Title: CY7C1480V33/CY7C1482V33/CY7C1486V33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM
Document Number: 38-05283
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
**
114670
08/06/02
PKS
New Data Sheet
*A
118281
01/21/03
HGK
Changed tCO from 2.4 to 2.6 ns for 250 MHz
Updated features on page 1 for package offering
Removed 30-MHz offering
Updated Ordering Information
Changed Advanced Information to Preliminary
*B
233368
See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 250-MHz speed grade offering and included 225-MHz speed bin
Changed package outline for 165FBGA package and 209-ball BGA
package
Removed 119-BGA package offering
*C
299452
See ECN
SYT
Removed 225-MHz offering and included 250-MHz speed bin
Changed tCYC from 4.4 ns to 4.0 ns for 250-MHz Speed Bin
Changed JA from 16.8 to 24.63 C/W and JC from 3.3 to 2.28 C/W for
100 TQFP Package on Page # 20
Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages
Added comment of ‘Lead-free BG packages availability’ below the
Ordering Information
*D
323080
See ECN
PCI
Unshaded 200 and 167 MHz speed bin in the AC/DC Table and Selection
Guide
Address expansion pins/balls in the pinouts for all packages are modified
as per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Added Truth Table and Note# 7 for CY7C1486V33 on page# 11
Added Industrial Operating Range
Modified VOL, VOH test conditions
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
*E
416193
See ECN
NXR
Converted Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1
from “3901 North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 19
Changed the IX current values of MODE on page # 19 from -5 A and 30 A
to -30 A and 5 A
Changed the IX current values of ZZ on page # 19 from -30 A and 5 A
to -5 A and 30 A
Changed VIH < VDD to VIH < VDD on page # 19
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the Ordering Information Table
Document Number: 38-05283 Rev. *K
Page 34 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Document History Page (continued)
Document Title: CY7C1480V33/CY7C1482V33/CY7C1486V33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM
Document Number: 38-05283
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
*F
470723
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH,tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table
Updated the Ordering Information table
*G
486690
See ECN
VKN
Corrected the typo in the 209-Ball FBGA pinout.
(Corrected the ball name H9 to VSS from VSSQ).
*H
1026720
See ECN
VKN
Added footnote #2 related to VSSQ
*I
2898501
03/24/2010
NJY
Removed inactive parts from Ordering Information table; Updated
package diagram.
*J
3067398
10/20/10
NJY
The part CY7C1480V33-250AXC found to be in “EOL Prune” state in
Oracle PLM is removed from the ordering information table.
Added ordering code definitions.
*K
3257192
05/14/2011
NJY
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
Document Number: 38-05283 Rev. *K
Page 35 of 36
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CY7C1480V33
CY7C1482V33
CY7C1486V33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05283 Rev. *K
Revised May 14, 2011
Page 36 of 36
i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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