TC94A14F/FA/FB TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC94A14F,TC94A14FA,TC94A14FB Digital Servo Single-Chip Processor for Use in CD Player TC94A14F/FA/FB is a single-chip processor which incorporates the following functions: sync separation protection, interpolation, EFM decoder, error correction, micro controller interface, digital equalizer for use in servo LSI, and servo control circuit. TC94A14F/FA/FB also incorporates a 1-bit DA converter. Combining TC94A14F/FA/FB with digital servo head amp TA2157F/FN enables very simple and completely adjustment-free CD player systems. TC94A14F Features · Capable of decoding the text data. · Sync pattern detection, sync signal protection, and synchronization can be made correctly. · Built-in EFM demodulation circuit and sub code demodulation. · Capable of correcting dual C1 correction and quadruple C2 correction using the CIRC correction theoretical format. · The TC94A14F/FA/FB respond to variable playback system. · Jitter absorbing capacity of ±6 frame. · Built-in 16 KB RAM. · Built-in digital out circuit. · Built-in L/R independent digital attenuator. · Audio output responds to bilingual function. · Output format for audio out can be selected 32fs, 48fs or 64fs modes. · Read-timing-free sub code Q data and capable of synchronous output with audio data. · Built-in data slicer and analog PLL (adjustment-free VCO). · Capable of automatic adjustment function of focus and tracking servos for loop gain, offset and balance. · Built-in RF gain automatic adjustment circuit. · Built-in digital equalizer for phase compensation. · Built-in RAM for digital equalizer for coefficient, and capable of variable pickup. · Built-in focus and tracking servo control circuit. · Search control corresponds to every mode and can realize high speed and stable search. · Lens-kick and feed-kick are using speed-controlled form. · Built-in AFC and APC circuits for CLV servo of disc motor. · Built-in anti-defect and anti-shock circuit. · Built-in 8 times over sampling digital filter and 1-bit DA converter. · Built-in analog filter for 1-bit DA converter. · Built-in zero data detection output circuit. · The TC94A14F/FA capable of 4 times speed operation. · Built-in micro controller interface circuit. · CMOS silicon structure and high speed, low power consumption. · 64-pin flat package. TC94A14FA TC94A14FB 1 Weight QFP64-P-1414-0.80A: 0.5 g (typ.) LQFP64-P-1010-0.50: 0.4 g (typ.) QFP64-P-1212-0.65: 0.45 g (typ.) 2002-11-18 TC94A14F/FA/FB XVDD3 XO XI XVSS3 TESIN VDD3 VSS3 DMO FMO AVDD3 SEL TEBC RFGC VREF TRO FOO Block Diagram (top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DVSS3 49 32 TEZI Clock generator RO 50 DVDD3 51 31 TEI PWM D/A 30 SBAD LPF DVR 52 29 FEI 1-bit DAC A/D Servo control LO 53 28 RFRP DVSS3 54 27 RFZI ZDET 55 ROM Address circuit VSS5 56 Correction circuit BUS0 57 BUS1 58 RAM Synchronous guarantee EFM decoder BUS2 59 BUS3 60 Audio out circuit BUCK 61 24 RFI 23 SLCO 22 AVSS3 VCO 21 VCOF Digital output 20 PVREF Microcontroller interface /CCE 62 25 AVDD3 Data slicer CLV servo 16 k RAM 26 RFCT Digital equalizer automatic adjustment circuit Sub code decoder 19 LPFO PLL TMAX 2 IPF VDD3 VSS3 SBOK 9 10 11 12 13 14 15 16 PDO 8 PVDD3 7 IO1 6 IO0 5 SBSY 4 SFSY 3 DATA 2 CLCK 1 DOUT 17 TMAX AOUT VDD5 64 LRCK 18 LPFN BCK /RST 63 2002-11-18 TC94A14F/FA/FB Pin Functions Pin No. Symbol I/O Function Description Remarks 1 BCK O 3-5I/F Bit clock output pin. 32fs, 48fs, or 64fs selectable by command. Normal speed: 32fs = 1.4112 MHz 2 LRCK O 3-5I/F L/R channel clock output pin. “L” for L channel and “H” for R channel. Output polarity can be inverted by command. Normal speed: 44.1 kHz 3 AOUT O 3-5I/F Audio data output pin. MSB-first or LSB-first selectable by command. 4 DOUT O 3-5I/F Digital data output pin. Outputs up to double-speed playback. 5 IPF O 3-5I/F Correction flag output pin. When set to “H”, AOUT output cannot Alias: C2PO be corrected by C2 correction processing. 6 VDD3 ¾ Digital 3.3 V power supply voltage pin. ¾ 7 VSS3 ¾ Digital GND pin. ¾ 8 SBOK O 3-5I/F Subcode Q data CRCC result output pin. “H” level when result is OK. ¾ 9 CLCK I/O 3-5I/F Subcode P-W data read clock I/O pin. I/O polarity selectable by command. 10 DATA O 3-5I/F Subcode P-W data output pin. ¾ 11 SFSY O 3-5I/F Playback frame sync signal output pin. ¾ 12 SBSY O 3-5I/F Subcode block sync signal output pin. “H” level at S1 when subcode sync is detected. ¾ 13 IO0 14 IO1 I/O 3-5I/F General-purpose input / output pins. Input port at reset. 15 PVDD3 ¾ 16 PDO O AI/F ¾ Based on CP-1201 Schmitt input Schmitt at input ¾ PLL-only 3.3 V power supply voltage pin. EFM and PLCK phase difference signal output pin. 4-state output (PVDD3, HiZ, PVREF, AVSS3) TMAX detection result output pin. 17 TMAX O AI/F TMAX Detection Result TMAX Output Longer than fixed period “PVDD3” Within fixed period “HiZ” Shorter than fixed period “AVSS3” 3-state output (PVDD3, HiZ, AVSS3) 18 LPFN I AI/F Inverted input pin for PLL LPF amp. Analog input 19 LPFO O AI/F Output pin for PLL LPF amp. Analog output 20 PVREF ¾ 21 VCOF O AI/F 22 AVSS3 ¾ 23 SLCO O AI/F DAC output pin for data slice level generation. Analog output 24 RFI I AI/F RF signal input pin. Zin selectable by command. Analog input 25 AVDD3 ¾ ¾ PLL-only VREF pin. VCO filter pin. Analog output ¾ Analog GND pin. Analog 3.3 V power supply voltage pin. 3 ¾ 2002-11-18 TC94A14F/FA/FB Pin No. Symbol I/O Function Description Remarks 26 RFCT I AI/F RFRP signal center level input pin. Analog input: Zin = 33 kW 27 RFZI I AI/F RFRP signal zero-cross input pin. Analog input 28 RFRP I AI/F RF ripple signal input pin. Analog input 29 FEI I AI/F Focus error signal input pin. Analog input 30 SBAD I AI/F Sub-beam adder signal input pin. Analog input 31 TEI I AI/F Tracking error input pin. Inputs when tracking servo is on. Analog input 32 TEZI I AI/F Tracking error signal zero-cross input pin. Analog input: Zin = 10 kW 33 FOO O AI/F Focus equalizer output pin. 34 TRO O AI/F Tracking equalizer output pin. 35 VREF ¾ 36 RFGC O AI/F RF amplitude adjustment control signal output pin. 37 TEBC O AI/F Tracking balance control signal output pin. 38 SEL O AI/F APC circuit ON/OFF signal output pin. At laser on, high impedance with UHS = “L”, H output with UHS = “H”. 39 AVDD3 ¾ 40 FMO O AI/F Feed equalizer output pin. 41 DMO O AI/F Disc equalizer output pin. 42 VSS3 ¾ Digital GND pin. ¾ 43 VDD3 ¾ Digital 3.3 V power supply voltage pin. ¾ 44 TESIN I 3I/F Test input pin. Normally, fixed to “L”. ¾ 45 XVSS3 ¾ System clock oscillator GND pin. ¾ 46 XI I AI/F System clock oscillator input pin. ¾ 47 XO O AI/F System clock oscillator output pin. ¾ 48 XVDD3 ¾ System clock oscillator 3.3 V power supply voltage pin. ¾ 49 DVSS3 ¾ DA converter GND pin. ¾ 50 RO O AI/F R-channel data forward output pin. ¾ 51 DVDD3 ¾ DA converter 3.3 V power supply pin. ¾ 52 DVR ¾ Reference voltage pin. ¾ 53 LO O AI/F L-channel data forward output pin. ¾ 54 DVSS3 ¾ DA converter GND pin. ¾ Analog output (AVSS3~AVDD3) ¾ Analog reference power supply voltage pin. Analog 3.3 V power supply voltage pin. 3-state output (PWM carrier = 88.2 kHz) (AVDD3, VREF, AVSS3) 3-state output ¾ 3-state output (PWM carrier = 88.2 kHz) (AVDD3, VREF, AVSS3) 4 2002-11-18 TC94A14F/FA/FB Pin No. Symbol I/O 55 ZDET O 3-5I/F 56 VSS5 ¾ 57 BUS0 58 BUS1 Function Description Remarks 1 bit DA converter zero data detection flag output pin. ¾ Microcontroller interface GND pin. ¾ Schmitt input I/O 3-5I/F Microcontroller interface data I/O pins. CMOS ports 59 BUS2 60 BUS3 61 BUCK I 3-5I/F Microcontroller interface clock input pin. Schmitt input 62 /CCE I 3-5I/F Microcontroller interface chip enable signal input pin. At “L”, BUS0 to BUS3 are active. Schmitt input 63 /RST I 3-5I/F Reset signal input pin. At reset, “L”. Built-in pull-up resistor 64 VDD5 ¾ ¾ Microcontroller interface 5 V power supply pin. Note: AI/F: analog input/output pin 3-5I/F: 3-5 interface built-in pin (5 V input/output pin) 3I/F: 3 V input/output pin Maximum Ratings (unless otherwise specified, GND reference, Ta = 25°C) Characteristics Symbol Rating VDD5 -0.3~6.0 Unit Remarks 64-56 pin 6-7 pin Power supply voltage VDD3 -0.3~4.5 V 15, 25, 39-22 pin 43-42 pin 48-45 pin 51-49, 54 pin Input voltage VIN5 -0.3~ VDD5 + 0.3 VIN3 -0.3~ VDD3 + 0.3 9, 13, 14, 57~63 pin V 18, 24, 26~32, 44 pin 1910 Power dissipation PD 1000 TC94A14F mW 1310 TC94A14FA TC94A14FB Operating temperature Topr -40~+85 °C ¾ Storage temperature Tstg -55~+150 °C ¾ 5 2002-11-18 TC94A14F/FA/FB Electrical Characteristics DC Characteristics (1) (unless otherwise specified, VDD5 = 5 V, VDD3 = AVDD3 = DVDD3 = XVDD3 = PVDD3 = 3.3 V, Ta = 25°C) Characteristics Operating power supply voltage Normal speed Operating power supply current Double speed 4 times speed Symbol Test Circuit Test Condition Min Typ. Max VDD5 ¾ ¾ 4.5 5.0 5.5 VDD3 ¾ ¾ AVDD3 ¾ ¾ DVDD3 ¾ ¾ 3.0 3.3 3.6 XVDD3 ¾ ¾ PVDD3 ¾ ¾ IDD5 (1) ¾ ¾ 2 5 IDD3 (1) ¾ ¾ 30 50 IDD5 (2) ¾ ¾ 2.5 6 IDD3 (2) ¾ ¾ 35 60 IDD5 (3) ¾ ¾ 3 7 XI = 16.9344 MHz Unit V mA IDD3 (3) ¾ ¾ 40 70 “H” level VIH5 ¾ ¾ ¾ “L” level VIL5 ¾ CMOS input pins except for analog input pins (5 V) 3.5 ¾ ¾ 1.5 “H” level IIH5 ¾ VIH5 = 5 V ¾ ¾ 1.0 “L” level IIL5 ¾ VIL5 = 0 V -1.0 ¾ ¾ “H” level ITLH5 ¾ VIH5 = 5 V ¾ ¾ 1.0 “L” level ITLL5 ¾ VIL5 = 0 V -1.0 ¾ ¾ “H” level IOH5 (1) ¾ ¾ ¾ -2.0 “L” level IOL5 (1) ¾ VOH5 = 4.6 V Pins grouped as 1 in V = 0.4 V the following table 2.0 ¾ ¾ “H” level IOH5 (2) ¾ ¾ ¾ -4.0 “L” level IOL5 (2) ¾ 4.0 ¾ ¾- “H” level VIH3 ¾ 2.3 ¾ ¾ “L” level VIL3 ¾ CMOS input pins except for analog input pins (3 V) ¾ ¾ 1.0 “H” level IIH3 ¾ VIH3 = 3.3 V ¾ ¾ 1.0 “L” level IIL3 ¾ VIL3 = 0 V -1.0 ¾ ¾ “H” level ITLH3 ¾ VIH3 = 3.3 V ¾ ¾ 1.0 “L” level ITLL3 ¾ VIL3 = 0 V -1.0 ¾ ¾ “H” level IOH3 (1) ¾ ¾ ¾ -2.0 “L” level IOL3 (1) ¾ VOH3 = 2.9 V Pins grouped as 4 in V = 0.4 V the following table 2.0 ¾ ¾ “H” level IOH3 (2) ¾ ¾ -80 ¾ “L” level IOL3 (2) ¾ VOH3 = 2.9 V Pins grouped as 5 in V = 0.4 V the following table ¾ 80 ¾ “H” level IOH3 (3) ¾ ¾ -121 ¾ “L” level IOL3 (3) ¾ VOH3 = 2.9 V Pins grouped as 6 in V = 0.4 V the following table ¾ 121 ¾ VREF output on resistance RON ¾ ¾ ¾ ¾ 500 W Pull-up resistance RUP ¾ Pins grouped as 8 in the following table 25 50 75 kW RO1 ¾ Pins grouped as 5 in the following table ¾ 5.0 ¾ RO2 ¾ Pins grouped as 6 and 7 in the following table ¾ 3.3 ¾ Input voltage 1 Input current 1 Tri-state leak current 1 Output current 1 Input voltage 2 Input current 2 Tri-state leak current 2 Output current 2 Pins grouped as 1, 2, 3 in the following table OL5 VOH5 = 4.6 V Pins grouped as 2 and 3 in the VOL5 = 0.4 V following table Pins grouped as 4 and 5 in the following table OL3 OL3 OL3 V mA mA mA V mA mA mA mA kW Pin built-in output resistance 6 2002-11-18 TC94A14F/FA/FB DC Characteristics (2) (unless otherwise specified, VDD5 = VDD3 = AVDD3 = DVDD3 = XVDD3 = PVDD3 = 3.3 V, Ta = 25°C) Symbol Test Circuit Test Condition VDD5 ¾ ¾ VDD3 ¾ ¾ AVDD3 ¾ ¾ DVDD3 ¾ ¾ XVDD3 ¾ ¾ PVDD3 ¾ ¾ Normal speed IDD3 (1) ¾ Double speed IDD3 (2) ¾ 4 times speed IDD3 (3) ¾ “H” level VIH3 ¾ “L” level VIL3 ¾ “H” level IIH3 “L” level Characteristics Min Typ. Max Unit 3.0 3.3 3.6 V ¾ 32 55 ¾ 37.5 66 ¾ 43 77 CMOS input pins except for analog input pins (3 V) 2.3 ¾ ¾ ¾ ¾ 1.0 ¾ VIH3 = 3.3 V ¾ ¾ 1.0 IIL3 ¾ VIL3 = 0 V -1.0 ¾ ¾ “H” level ITLH3 ¾ VIH3 = 3.3 V ¾ ¾ 1.0 “L” level ITLL3 ¾ VIL3 = 0 V -1.0 ¾ ¾ “H” level IOH3 (1) ¾ ¾ ¾ -1.0 “L” level IOL3 (1) ¾ VOH3 = 2.9 V Pins grouped as 1 in V = 0.4 V the following table 1.0 ¾ ¾ “H” level IOH3 (2) ¾ ¾ ¾ -2.0 “L” level IOL3 (2) ¾ 2.0 ¾ ¾- “H” level IOH3 (3) ¾ ¾ ¾ -2.0 “L” level IOL3 (3) ¾ 2.0 ¾ ¾ “H” level IOH3 (4) ¾ ¾ -80 ¾ “L” level IOL3 (4) ¾ VOH3 = 2.9 V Pins grouped as 5 in V = 0.4 V the following table ¾ 80 ¾ “H” level IOH3 (5) ¾ ¾ -121 ¾ “L” level IOL3 (5) ¾ VOH3 = 2.9 V Pins grouped as 6 in V = 0.4 V the following table ¾ 121 ¾ VREF output on resistance RON ¾ ¾ ¾ ¾ 500 W Pull-up resistance RUP ¾ Pins grouped as 8 in the following table 50 80 120 kW RO1 ¾ Pins grouped as 5 in the following table ¾ 5.0 ¾ RO2 ¾ Pins grouped as 6 and 7 in the following table ¾ 3.3 ¾ Operating power supply voltage Operating power supply current Input voltage Input current Tri-state leak current Output current XI = 16.9344 MHz Pins grouped as 4 and 5 in the following table OL3 VOH3 = 2.9 V Pins grouped as 2 and 3 in the VOL3 = 0.4 V following table VOH3 = 2.9 V Pins grouped as 4 in V = 0.4 V the following table OL3 OL3 OL3 Pin built-in output resistance mA V mA mA mA mA mA kW 7 2002-11-18 TC94A14F/FA/FB Pin Group Pin Name 1 SBOK, SFSY, SBSY, IO0, IO1, ZDET 2 BCK, LRCK, AOUT, DOUT, IPF, CLCK, DATA 3 BUS3, BUS2, BUS1, BUS0 4 SEL, TMAX 5 PDO 6 RFGC, TEBC, FMO, DMO 7 FOO, TRO 8 /RST AC Characteristics (unless otherwise specified, VDD5 = 5 V, VDD3 = AVDD3 = DVDD3 = XVDD3 = PVDD3 = 3.3 V, Ta = 25°C) 1. Microcontroller Interface Timing Symbol Test Circuit Test Condition Min Typ. Max /CCE = “H” pulse width tCC ¾ ¾ 120 ¾ ¾ Data disable time tSZ1 ¾ BUCK rise reference 0 ¾ ¾ /CCE, BUCK delay time tCB ¾ /CCE fall reference 0 ¾ ¾ BUCK, /CCE delay time tBC ¾ BUCK rise reference 0 ¾ ¾ tBLW ¾ Write, SRC mode 120 ¾ ¾ tBLW ¾ QDRC mode 240 ¾ ¾ BUCK = “H” pulse width (1) tBHW ¾ Write, SRC mode 120 ¾ ¾ BUCK = “H” pulse width (2) tBHW ¾ QDRC mode (normal speed) 3000 ¾ ¾ BUCK = “H” pulse width (3) tBHW ¾ QDRC mode (double speed) 1500 ¾ ¾ BUCK = “H” pulse width (4) tBHW ¾ QDRC mode (´4 speed) 800 ¾ ¾ Write data setup time tWS ¾ BUCK rise reference 60 ¾ ¾ Write data hold time tWH ¾ BUCK rise reference 20 ¾ ¾ Data disable time tSZ2 ¾ BUCK fall reference 0 ¾ ¾ Read data access time tRD ¾ BUCK fall reference 0 ¾ ¾ Characteristics BUCK = “L” pulse width (1) Unit ns Write command mode tCB tBC tCC /CCE tBLW tBHW BUCK tSZ2 BUSi (input) tWS CM tWH CL DM DL Write mode 8 2002-11-18 TC94A14F/FA/FB (2) Write command mode: Bxxxxx, Fxxxxx commands tBC tCC tBC tCC Min Typ. Max ¾ ¾ 5 ¾ ¾ 5 ¾ ¾ 5 ¾ ¾ 5 tCB /CCE tBLW tBHW BUCK tSZ2 BUSi (input) tWS tWH CM CL DM DL EM EL Write mode (3) Read command mode tCB /CCE tBLW tBHW BUCK tSZ2 BUSi (input) tWS tWH CM tRD BUSi (input) tSZ1 RDO RDn Read mode 2. AOUT Data Output Timing Symbol Test Circuit “H” level tpLH1 ¾ “L” level tpHL1 ¾ “H” level tpLH2 ¾ “L” level tpHL2 ¾ Characteristics Transfer time (1) Transfer time (2) tpHL2 tpLH2 Test Condition LRCK AOUT Unit ns tpHL1 tpLH1 BCK LRCK AOUT 9 2002-11-18 TC94A14F/FA/FB 3. DATA, CLCK Input/Output Timing (1) CLCK input mode (regardless of setting of HS and UHS bits of SPEED command) Symbol Test Circuit “H” level tHW ¾ “L” level tLW ¾ tSU ¾ “L” level tpHL1 ¾ “H” level tpLH52 ¾ “L” level tpHL52 ¾ “H” level tpLH52 ¾ “L” level tpHL52 ¾ Characteristics Clock pulse width Input setup time Transfer time (1) Transfer time (2) Test Condition Min Typ. Max 50 ¾ ¾ 50 ¾ ¾ CLCK input mode ¾ ¾ ¾ CLCK input mode ¾ ¾ 5 ¾ ¾ 15 ¾ ¾ 15 ¾ ¾ 20 ¾ ¾ 20 Min Typ. Max ¾ ¾ 950 ¾ ¾ 950 ¾ ¾ 5 CLCK input mode CLCK input mode VDD5 = 3.3 V tpHL1 Unit ns tpHL52, tpLH52 tpHL32, tpLH32 SFSY tSU tHW tLW CLCK SUBP DATA (2) SUBQ CLCK output mode (tHW, tLW, tpLH3 only, ´ 1/n at ´n speed) Symbol Test Circuit “H” level tHW ¾ “L” level tLW ¾ “L” level tpHL1 ¾ “H” level tpLH52 ¾ “L” level tpHL52 ¾ “H” level tpLH32 ¾ “L” level tpHL32 ¾ “H” level tpLH3 ¾ Characteristics Clock pulse width Transfer time (1) Transfer time (2) Transfer time (3) Test Condition CLCK output mode CLCK output mode CLCK output mode VDD5 = 3.3 V CLCK output mode tpHL1 ¾ ¾ 15 ¾ ¾ 15 ¾ ¾ 20 ¾ ¾ 20 ¾ ¾ 850 Unit ns tpHL52, tpLH52 tpHL32, tpLH32 SFSY tpLH3 tHW tLW CLCK DATA SUBP SUBQ 10 2002-11-18 TC94A14F/FA/FB 4. SBSY, SBOK Input/Output Timing Symbol Test Circuit “H” level tpLH1 ¾ “L” level tpHL1 ¾ “H” level tpLH2 ¾ “L” level tpHL2 ¾ Characteristics Transfer time (1) Transfer time (2) Test Condition SBSY SBOK tpLH1 Min Typ. Max ¾ ¾ 5 ¾ ¾ 10 ¾ ¾ 15 ¾ ¾ 20 Min Typ. Max ¾ ¾ 7 ¾ ¾ 12 ¾ ¾ 14 ¾ ¾ 24 ¾ ¾ 7 ¾ ¾ 7 ¾ ¾ 14 ¾ ¾ 14 ¾ ¾ 7 ¾ ¾ 7 ¾ ¾ 14 ¾ ¾ 14 ¾ ¾ 10 ¾ ¾ 10 Unit ns tpHL1 SFSY tpLH2 tpHL2 SBSY SBOK 5. Output Pin Timing Characteristics Symbol Output rise time 5 (1) tor51 Output fall time 5 (1) tof51 Output rise time 3 (1) tor31 Output fall time 3 (1) tof31 Output rise time 5 (2) tor52 Output fall time 5 (2) tof52 Output rise time 3 (2) tor32 Output fall time 3 (2) tof32 Output rise time 5 (3) tor53 Output fall time 5 (3) tof53 Output rise time 3 (3) tor33 Test Circuit Pins grouped as 1 below ¾ VDD5 = 3.3 V Pins grouped as 2 below ¾ VDD5 = 3.3 V Pins grouped as 3 below ¾ VDD5 = 3.3 V Output fall time 3 (3) tof33 Output rise time 5 (4) tor54 ¾ tof54 ¾ Output fall time 5 (4) Pin Group Test Condition Pins grouped as 4 below Pin Name VOH 1 SBOK, SFSY, SBSY, IO0, IO1, ZDET 2 BCK, LRCK, AOUT, DOUT, IPF, CLCK, DATA 3 BUS3, BUS2, BUS1, BUS0 4 TMAX, SEL ns 90% VOH/2 10% VSS tor 11 Unit tof 2002-11-18 TC94A14F/FA/FB Analog Circuit Characteristics 1. AD Converter Characteristics Test Circuit Test Condition Min Typ. Max Unit ¾ ¾ ¾ 8 ¾ bit ¾ 176.4 ¾ ¾ 176.4 ¾ ¾ 88.2 ¾ ¾ 176.4 ¾ 0.15 ´ AVDD3 ¾ 0.85 ´ AVDD3 V Resolution FE ¾ TE ¾ SBAD ¾ RFRP ¾ Sampling frequency ¾ Conversion input range ¾ AVSS = 0 V AVDD3 = 3.3 V kHz 2. DA Converter (focus and tracking equalizer output) Test Circuit Test Condition Min Typ. Max Unit Number of bits ¾ ¾ ¾ ¾ 5 bit Sampling frequency ¾ ¾ ¾ ¾ 2.8 MHz Signal output range ¾ AVSS3 ¾ AVDD3 V Characteristics AVSS = 0 V, AVDD3 = 3.3 V 3. PLL Filter Amp Test Circuit Test Condition Min Typ. Max Unit I/O signal range ¾ ¾ AVSS3 ¾ PVDD3 V Frequency characteristic ¾ ¾ 8 ¾ MHz Min Typ. Max Unit MHz Characteristics -3dB point (Gain = 1) 4. VCO (PLL) Characteristics Test Circuit Center oscillation frequency Frequency variable range Test Condition ¾ LPFO = VREF ¾ 34 ¾ ¾ [VCOGSL] bit = “L” ¾ ±50 ¾ ¾ [VCOGSL] bit = “H” ¾ ±60 ¾ % 5. TEZI Signal Comparator Test Circuit Test Condition Min Typ. Max Unit Input range ¾ ¾ AVSS3 ¾ AVDD3 V Hysteresis voltage ¾ ¾ ±50 ¾ mV Characteristics VREF reference 6. RFZI Signal Comparator Test Circuit Test Condition Min Typ. Max Unit Input range ¾ ¾ AVSS3 ¾ AVDD3 V Hysteresis voltage ¾ ¾ ±50 ¾ mV Characteristics VREF reference 12 2002-11-18 TC94A14F/FA/FB 7. Data Slicer Circuit (1) Comparator Test Circuit Characteristics ¾ Input amplitude (2) Test Condition VREF reference Min Typ. Max Unit 0.6 1.2 2.0 Vpp R-2R DAC (digital slicer DAC) Test Circuit Test Condition Min Typ. Max Unit Output conversion range ¾ ¾ AVSS3 ¾ AVDD3 V Output impedance ¾ ¾ ¾ 2.5 ¾ kW Characteristics 8. Audio DAC Characteristics Characteristics Test Circuit Symbol THD + N (1) Total harmonic distortion + noise 1 THD + N (2) S/N (1) S/N ratio 1 S/N (2) Test Condition Min Typ. Max 1 kHz sine wave, full-scale input ¾ -88 -80 10 kHz sine wave, full-scale input ¾ -80 -75 Internal Zero detect = OFF 87 92 ¾ Internal Zero detect = ON 95 100 ¾ Unit dB dB Dynamic range DR 1 1 kHz sine wave, -60dB input conversion 85 90 ¾ dB Cross talk CT 1 1 kHz sine wave, full-scale input ¾ -90 -85 dB DAC out 1 1 kHz sine wave, full-scale input 790 820 850 mVrms Analog output amplitude Test Circuit 1: Application circuit is used. Lout TC94A14F/FA/FB application circuit Distortion meter 20 kHz ideal LPF Rout LPF: Filter with built-in Shibasoku 725D Distortion meter: Shibasoku 725D equivalent Characteristic Distortion Filter Setting A-weight THD + N, CT OFF S/N, DR ON A-weight: IEC-A equivalent Application Circuit TC94A14F/FA/FB DVSS3 3.3 V DVDD3 R-ch analog output 22 mF DVR XO 270 W 3.3 mF LO DVSS3 13 L-ch analog output 10 k9 XVSS3 2200 pF 16.9344 MHz 1 M9 XI 3.3 V 10 k9 XVDD3 2200 pF 270 W 3.3 mF RO 2002-11-18 TC94A14F/FA/FB Package Dimensions Weight: 0.5 g (typ.) 14 2002-11-18 TC94A14F/FA/FB Package Dimensions Weight: 0.4 g (typ.) 15 2002-11-18 TC94A14F/FA/FB Package Dimensions Weight: 0.45 g (typ.) 16 2002-11-18 TC94A14F/FA/FB RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 17 2002-11-18